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| author | Andy Fleming <afleming@freescale.com> | 2008-02-27 15:50:50 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-02-27 16:28:57 -0600 |
| commit | 534ea6b6f86f8b75ef2ac061ef110a98f103d7d6 (patch) | |
| tree | 844f1c5f4cdc5a5d2899b14f08741046440887ad | |
| parent | 21fae8b2b4e4e6e648796e07e20ab13e9cb18923 (diff) | |
| download | olio-uboot-2014.01-534ea6b6f86f8b75ef2ac061ef110a98f103d7d6.tar.xz olio-uboot-2014.01-534ea6b6f86f8b75ef2ac061ef110a98f103d7d6.zip | |
Fix source for ECM error IVPR
The source vector for the ECM was being set to 2,
but that's what the source vector for DDR was being
set to. Change it to 1.
Signed-off-by: Andy Fleming <afleming@freescale.com>
| -rw-r--r-- | cpu/mpc85xx/interrupts.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index 18e5377b3..4fe1facf4 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -91,7 +91,7 @@ int interrupt_init (void) set_msr (get_msr () | MSR_EE); #ifdef CONFIG_INTERRUPTS - pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */ + pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1); pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ |