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| author | Jerry Van Baren <gvb.uboot@gmail.com> | 2009-03-13 11:40:10 -0400 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2009-03-14 17:44:07 -0500 |
| commit | 394d30dd1ee23b80fd5e59e17ebe0feca927ab31 (patch) | |
| tree | 4e8ccb2887c57557133c1b59364838bbe793fd84 | |
| parent | b581626c1e2474a3dadf69d4f0e0582eccbc4235 (diff) | |
| download | olio-uboot-2014.01-394d30dd1ee23b80fd5e59e17ebe0feca927ab31.tar.xz olio-uboot-2014.01-394d30dd1ee23b80fd5e59e17ebe0feca927ab31.zip | |
mpc83xx: Add bank configuration to FSL spd_sdram.c
The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8
bank SDRAMs.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| -rw-r--r-- | cpu/mpc83xx/spd_sdram.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index ff15cda7a..4704d2006 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -219,7 +219,8 @@ long int spd_sdram() ddr->cs_config[0] = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) | (spd.ncol_addr - 8) ); debug("\n"); debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); @@ -231,8 +232,9 @@ long int spd_sdram() ddr->cs_config[1] = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr-12) << 8 - | (spd.ncol_addr-8) ); + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) + | (spd.ncol_addr - 8) ); debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); } @@ -242,7 +244,8 @@ long int spd_sdram() ddr->cs_config[2] = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) | (spd.ncol_addr - 8) ); debug("\n"); debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); @@ -254,8 +257,9 @@ long int spd_sdram() ddr->cs_config[3] = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr-12) << 8 - | (spd.ncol_addr-8) ); + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) + | (spd.ncol_addr - 8) ); debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); } |