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| author | Stefano Babic <sbabic@denx.de> | 2012-04-09 13:29:06 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-04-16 14:53:59 +0200 |
| commit | 2f002eceae44c21656b7f596624c636157ffdf1c (patch) | |
| tree | f23dabf5ed61b5dd7f9bad69bbadd36c57544038 | |
| parent | fbf4a074e0b7eb4864836084eff2a747617be0b4 (diff) | |
| download | olio-uboot-2014.01-2f002eceae44c21656b7f596624c636157ffdf1c.tar.xz olio-uboot-2014.01-2f002eceae44c21656b7f596624c636157ffdf1c.zip | |
MX35: mx35pdk: wrong board revision
The board revision is detected accessing to the pmic,
that is not available before relocation (I2C).
This generates the following error:
CPU: Freescale i.MX35 rev 2.0 at 532 MHz.
Reset cause: WDOG
<reg num> = 7 is invalid. Should be less than 0
Board: MX35 PDK 1.0
The revision number is wrong, as a default value is printed
(tested on a mx35pdk Rev. 2.0).
Move the output in the board_late_init(), when
pmic can be accessed.
Signed-off-by: Stefano Babic <sbabic@denx.de>
| -rw-r--r-- | board/freescale/mx35pdk/mx35pdk.c | 11 | ||||
| -rw-r--r-- | include/configs/mx35pdk.h | 1 |
2 files changed, 0 insertions, 12 deletions
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index cce712354..bc415b846 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -258,17 +258,6 @@ int board_late_init(void) val |= 0x80; mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); - return 0; -} - -int checkboard(void) -{ - /* - * Be sure that I2C is initialized to check - * the board revision - */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - /* Print board revision */ printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F); diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 1e03639ad..de4b954a5 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -34,7 +34,6 @@ #define CONFIG_MX35_HCLK_FREQ 24000000 #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO /* Set TEXT at the beginning of the NOR flash */ #define CONFIG_SYS_TEXT_BASE 0xA0000000 |