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| author | Poonam Aggrwal <poonam.aggrwal@freescale.com> | 2009-10-27 09:36:38 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-10-27 09:12:36 -0500 |
| commit | 273a28ad9ef59dcfcd4c056ec1f61f1e0896cfaa (patch) | |
| tree | 224dfc7d84e95f18a4a9572077f71dc942929ce0 | |
| parent | 924024c396761c267b948f38d78e9905f2036501 (diff) | |
| download | olio-uboot-2014.01-273a28ad9ef59dcfcd4c056ec1f61f1e0896cfaa.tar.xz olio-uboot-2014.01-273a28ad9ef59dcfcd4c056ec1f61f1e0896cfaa.zip | |
85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data rate
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | board/freescale/p1_p2_rdb/ddr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 5cb4a13e0..fccc4f8f5 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -85,8 +85,8 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #define CONFIG_SYS_DDR_TIMING_0_800 0x55770802 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x00440862 +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 +#define CONFIG_SYS_DDR_MODE_1_800 0x00040852 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 #define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100 |