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| author | Nick Spence <nick.spence@freescale.com> | 2008-08-22 23:52:40 -0700 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2008-08-25 17:04:40 -0500 |
| commit | 002d27caf26e7eb913d474d3a91f67d56c8c31d5 (patch) | |
| tree | 22b01e49addf03b5a4c1bc52e91183061139e154 | |
| parent | 447ad5768abda669ac0e7f46fcdb62fbe828d637 (diff) | |
| download | olio-uboot-2014.01-002d27caf26e7eb913d474d3a91f67d56c8c31d5.tar.xz olio-uboot-2014.01-002d27caf26e7eb913d474d3a91f67d56c8c31d5.zip | |
MPC83XX: Add miscellaneous registers and #defines to support MPC83xx family devices
This patch adds elements to the 83xx sysconf structure and #define values that are used
by mpc83xx family devices.
Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| -rw-r--r-- | include/asm-ppc/immap_83xx.h | 4 | ||||
| -rw-r--r-- | include/mpc83xx.h | 7 |
2 files changed, 10 insertions, 1 deletions
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 5b215393e..ff183033c 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -61,7 +61,9 @@ typedef struct sysconf83xx { u32 spcr; /* System Priority Configuration Register */ u32 sicrl; /* System I/O Configuration Register Low */ u32 sicrh; /* System I/O Configuration Register High */ - u8 res6[0x0C]; + u8 res6[0x04]; + u32 sidcr0; /* System I/O Delay Configuration Register 0 */ + u32 sidcr1; /* System I/O Delay Configuration Register 1 */ u32 ddrcdr; /* DDR Control Driver Register */ u32 ddrdsr; /* DDR Debug Status Register */ u32 obir; /* Output Buffer Impedance Register */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 70a4de70d..5d82bb46f 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -350,7 +350,9 @@ /* ATR - Arbiter Timers Register */ #define ATR_DTO 0x00FF0000 /* Data time out */ +#define ATR_DTO_SHIFT 16 #define ATR_ATO 0x000000FF /* Address time out */ +#define ATR_ATO_SHIFT 0 /* AER - Arbiter Event Register */ @@ -364,10 +366,15 @@ /* AEATR - Arbiter Event Address Register */ #define AEATR_EVENT 0x07000000 /* Event type */ +#define AEATR_EVENT_SHIFT 24 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ +#define AEATR_MSTR_ID_SHIFT 16 #define AEATR_TBST 0x00000800 /* Transfer burst */ +#define AEATR_TBST_SHIFT 11 #define AEATR_TSIZE 0x00000700 /* Transfer Size */ +#define AEATR_TSIZE_SHIFT 8 #define AEATR_TTYPE 0x0000001F /* Transfer Type */ +#define AEATR_TTYPE_SHIFT 0 /* HRCWL - Hard Reset Configuration Word Low */ |