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/*
* SDRC register values for the Micron MT29C4G48MAYAPAKQ-5
*
* Copyright (C) 2015 Olio Devices
* Copyright (C) 2008 Texas Instruments, Inc.
* Copyright (C) 2008-2009 Nokia Corporation
*
* Mattis Fjallstrom (mattis at oliodevices.com)
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT29C8G96
#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT29C8G96
#include "sdrc.h"
/* MT29C8G96MAZBBDJV-48 IT */
/* 4.8ns -> 208.333 MHz */
/* 5ns -> 200MHz */
static struct omap_sdrc_params mt29c8g96_sdrc_params[] = {
[0] = {
.rate = 208333333,
.actim_ctrla = 0x7AE1B4C6,
.actim_ctrlb = 0x00021217,
.rfr_ctrl = 0x00062701,
.mr = 0x00000032,
},
[1] = {
.rate = 0,
},
};
/*
[1] = {
.rate = 200000000,
.actim_ctrla = 0x7AE1B4C6,
.actim_ctrlb = 0x00021217,
.rfr_ctrl = 0x0005E601,
.mr = 0x00000032,
},
*/
#endif
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