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Change-Id: I631c65e0028328d3d9f1906a2b858edd11ca6e82
Signed-off-by: Vladimir Tsunaev <vladimirt@motorola.com>
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OMAP 36xx has 192Mhz source clock, which is used as parent of 96MHz.
Clock tree is modified by substitution omap_96m_alwon_fck with copy
of omap_96m_alwon_fck_3630, but hw structure was not modified to
reflect this substitution.
Change-Id: Ib68586b7807177d2798b1cb301215789cd325742
Signed-off-by: Vladimir Tsunaev <vladimirt@motorola.com>
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VP clock configuration should match with device name.
Change-Id: I98404176bdc7d4144f9ae0e21646bafd077da5b6
Signed-off-by: Vladimir Tsunaev <vladimirt@motorola.com>
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Change-Id: I1d6cf816aa9115a0a2baf9762162336d4204c071
Signed-off-by: Vladimir Tsunaev <vladimirt@motorola.com>
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The cpu0 cpufreq driver will request the clock using
devm_clk_get(cpu_dev, NULL). Without a clk mechanism
in the device tree, a clock setting to matching the
ofd name for cpu0 device needs to be added to the
current clk table.
Change-Id: Id2a362e2c5329bc677945861176da2b6d8f3257b
Signed-off-by: James Wylder <jwylder@motorola.com>
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Convert the device data for the OMAP3 AES crypto IP
from explicit platform_data to hwmod.
CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
[paul@pwsan.com: fixed lines causing sparse warnings]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Convert the device data for the OMAP3 SHAM2 (SHA1/MD5) crypto IP
from explicit platform_data to hwmod.
CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
[paul@pwsan.com: updated to use per-SoC registration lists for GP-only hwmods;
fixed lines causing sparse warnings]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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The patch removes all the CK_* which were used to identify the family of
processors for which the individual clocks belonged to. Instead now separate
lists are created based on the family of processors.
Boot Tested on: OMAP4430, OMAP4460, Beagle-board, AM33X boards, OMAP2 boards.
Signed-off-by: J Keerthy <j-keerthy@ti.com>
Tested-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Tested-by: Jon Hunter <jon-hunter@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: changed omap_clock_register_links() to omap_clocks_register();
updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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The cam_mclk clock is generated through the following clocks chain:
dpll4 -> dpll4_m5 -> dpll4_m5x2 -> cam_mclk
As dpll4_m5 and dpll4_m5x2 do not driver any clock other than cam_mclk,
back-propagate the cam_clk rate changes up to dpll4_m5.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Sakari Ailus <sakari.ailus@iki.fi>
Tested-by: Sakari Ailus <sakari.ailus@iki.fi>
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The ETM/ETB drivers for OMAP3, enable the emu_src_ck clock in order
to access the ETM/ETB hardware. The emu_src_ck should enable the EMU
clock domain so that the ETM/ETB hardware is accessible. However,
currently when enabling the emu_src_ck the EMU clock domain is not
being enabled and so the ETM/ETB drivers are failing. Add enable/disable
clock functions to enable the EMU clock domain when enabling the
emu_src_ck.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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The patch is the output from a python script which converts
from the old OMAP clk format to COMMON clk format using a
JSON parser in between which was developed by Paul Walmsley.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: AM3517/05: dropped bogus hsotgusb "ick" and "fck"
clkdev aliases; added hsotgusb_fck alias; added emac_ick and emac_fck
aliases; replace omap2_init_clksel_parent() with
omap2_clksel_find_parent_index(); reflow macros and parent name
lists; add clkdm_name argument to DEFINE_STRUCT_CLK_HW_OMAP macros]
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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