diff options
| author | Wengang Wu <wgw@motorola.com> | 2014-05-21 09:29:41 -0500 |
|---|---|---|
| committer | Wengang Wu <wgw@motorola.com> | 2014-05-21 09:29:41 -0500 |
| commit | 53a835f5057367679eb3db728bbdd427aab8aa8a (patch) | |
| tree | 03e5bbde7d371e885d1c67210b2b0c9bb0130d40 /drivers/gpu/pvr/services4/srvkm/devices | |
| parent | 7489b569ffb64cdb998544405b6774bd43aab70b (diff) | |
| download | olio-linux-3.10-53a835f5057367679eb3db728bbdd427aab8aa8a.tar.xz olio-linux-3.10-53a835f5057367679eb3db728bbdd427aab8aa8a.zip | |
IKXCLOCK-1501 Upgrade to TI SGX Android OpenGL 1.12@2701748
Initial codes of TI SGX DDK 1.12@2701748
Change-Id: I75a8f6521968346ea1b2ea9fa54817ba186442ce
Diffstat (limited to 'drivers/gpu/pvr/services4/srvkm/devices')
13 files changed, 1105 insertions, 645 deletions
diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/mmu.c b/drivers/gpu/pvr/services4/srvkm/devices/sgx/mmu.c index 44dc824ec50..8e4f159da4f 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/mmu.c +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/mmu.c @@ -274,6 +274,10 @@ struct _MMU_HEAP_ static IMG_VOID _DeferredFreePageTable (MMU_HEAP *pMMUHeap, IMG_UINT32 ui32PTIndex, IMG_BOOL bOSFreePT); +#if defined (MEM_TRACK_INFO_DEBUG) +IMG_IMPORT IMG_VOID PVRSRVPrintMemTrackInfo(IMG_UINT32 ui32FaultAddr); +#endif + #if defined(PDUMP) static IMG_VOID MMU_PDumpPageTables (MMU_HEAP *pMMUHeap, @@ -332,7 +336,7 @@ static IMG_VOID CheckPT(MMU_PT_INFO *psPTInfoList) PVR_DPF((PVR_DBG_ERROR, "ui32ValidPTECount: %u ui32Count: %u\n", psPTInfoList->ui32ValidPTECount, ui32Count)); DumpPT(psPTInfoList); - BUG(); + PVR_DBG_BREAK; } } #else /* PT_DEBUG */ @@ -348,7 +352,7 @@ static INLINE IMG_VOID CheckPT(MMU_PT_INFO *psPTInfoList) it read/write when we alter it. This allows us to check that our memory isn't being overwritten */ -#if defined(PVRSRV_MMU_MAKE_READWRITE_ON_DEMAND) +#if defined(__linux__) && defined(PVRSRV_MMU_MAKE_READWRITE_ON_DEMAND) #include <linux/version.h> @@ -848,6 +852,15 @@ _AllocPageTableMemory (MMU_HEAP *pMMUHeap, } else { + /* + We cannot use IMG_SYS_PHYADDR here, as that is 64-bit for 32-bit PAE builds. + The physical address in this call to RA_Alloc is specifically the SysPAddr + of local (card) space, and it is highly unlikely we would ever need to + support > 4GB of local (card) memory (this does assume that such local + memory will be mapped into System physical memory space at a low address so + that any and all local memory exists within the 4GB SYSPAddr range). + */ + IMG_UINTPTR_T uiLocalPAddr; IMG_SYS_PHYADDR sSysPAddr; /* @@ -864,12 +877,15 @@ _AllocPageTableMemory (MMU_HEAP *pMMUHeap, 0, IMG_NULL, 0, - &(sSysPAddr.uiAddr))!= IMG_TRUE) + &uiLocalPAddr)!= IMG_TRUE) { PVR_DPF((PVR_DBG_ERROR, "_AllocPageTableMemory: ERROR call to RA_Alloc failed")); return IMG_FALSE; } + /* Munge the local PAddr back into the SysPAddr */ + sSysPAddr.uiAddr = uiLocalPAddr; + /* derive the CPU virtual address */ sCpuPAddr = SysSysPAddrToCpuPAddr(sSysPAddr); /* note: actual ammount is pMMUHeap->ui32PTSize but must be a multiple of 4k pages */ @@ -986,8 +1002,9 @@ _FreePageTableMemory (MMU_HEAP *pMMUHeap, MMU_PT_INFO *psPTInfoList) /* just free from the first local memory arena (unlikely to be more than one local mem area(?)) + Note that the cast to IMG_UINTPTR_T is ok as we're local mem. */ - RA_Free (pMMUHeap->psDevArena->psDeviceMemoryHeapInfo->psLocalDevMemArena, sSysPAddr.uiAddr, IMG_FALSE); + RA_Free (pMMUHeap->psDevArena->psDeviceMemoryHeapInfo->psLocalDevMemArena, (IMG_UINTPTR_T)sSysPAddr.uiAddr, IMG_FALSE); } } @@ -1308,8 +1325,9 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT if((UINT32_MAX_VALUE - DevVAddr.uiAddr) < (ui32Size + pMMUHeap->ui32DataPageMask + pMMUHeap->ui32PTMask)) { - /* detected overflow, clamp to highest address */ + /* detected overflow, clamp to highest address, reserve all PDs */ sHighDevVAddr.uiAddr = UINT32_MAX_VALUE; + ui32PageTableCount = 1024; } else { @@ -1317,9 +1335,10 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT + ui32Size + pMMUHeap->ui32DataPageMask + pMMUHeap->ui32PTMask; + + ui32PageTableCount = sHighDevVAddr.uiAddr >> pMMUHeap->ui32PDShift; } - ui32PageTableCount = sHighDevVAddr.uiAddr >> pMMUHeap->ui32PDShift; /* Fix allocation of last 4MB */ if (ui32PageTableCount == 0) @@ -1343,10 +1362,18 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT DevVAddr.uiAddr = DevVAddr.uiAddr & (~BRN31620_PDE_CACHE_FILL_MASK); /* Round the end address of the PD allocation to cacheline */ - sHighDevVAddr.uiAddr = ((sHighDevVAddr.uiAddr + (BRN31620_PDE_CACHE_FILL_SIZE - 1)) & (~BRN31620_PDE_CACHE_FILL_MASK)); + if (UINT32_MAX_VALUE - sHighDevVAddr.uiAddr < (BRN31620_PDE_CACHE_FILL_SIZE - 1)) + { + sHighDevVAddr.uiAddr = UINT32_MAX_VALUE; + ui32PageTableCount = 1024; + } + else + { + sHighDevVAddr.uiAddr = ((sHighDevVAddr.uiAddr + (BRN31620_PDE_CACHE_FILL_SIZE - 1)) & (~BRN31620_PDE_CACHE_FILL_MASK)); + ui32PageTableCount = sHighDevVAddr.uiAddr >> pMMUHeap->ui32PDShift; + } ui32PDIndex = DevVAddr.uiAddr >> pMMUHeap->ui32PDShift; - ui32PageTableCount = sHighDevVAddr.uiAddr >> pMMUHeap->ui32PDShift; /* Fix allocation of last 4MB */ if (ui32PageTableCount == 0) @@ -1371,10 +1398,11 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT { ui32Flags |= PDUMP_FLAGS_CONTINUOUS; } - PDUMPCOMMENTWITHFLAGS(ui32Flags, "Alloc PTs (MMU Context ID == %u, PDBaseIndex == %u, Size == 0x%x)", + PDUMPCOMMENTWITHFLAGS(ui32Flags, "Alloc PTs (MMU Context ID == %u, PDBaseIndex == %u, Size == 0x%x, Shared = %s)", pMMUHeap->psMMUContext->ui32PDumpMMUContextID, pMMUHeap->ui32PDBaseIndex, - ui32Size); + ui32Size, + MMU_IsHeapShared(pMMUHeap)?"True":"False"); PDUMPCOMMENTWITHFLAGS(ui32Flags, "Alloc page table (page count == %08X)", ui32PageTableCount); PDUMPCOMMENTWITHFLAGS(ui32Flags, "Page directory mods (page count == %08X)", ui32PageTableCount); } @@ -1424,7 +1452,7 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT if(ppsPTInfoList[i]->hPTPageOSMemHandle == IMG_NULL && ppsPTInfoList[i]->PTPageCpuVAddr == IMG_NULL) { - IMG_DEV_PHYADDR sDevPAddr; + IMG_DEV_PHYADDR sDevPAddr = { 0 }; #if defined(SUPPORT_SGX_MMU_DUMMY_PAGE) IMG_UINT32 *pui32Tmp; IMG_UINT32 j; @@ -1473,7 +1501,9 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT { /* insert Page Table into all memory contexts */ MMU_CONTEXT *psMMUContext = (MMU_CONTEXT*)pMMUHeap->psMMUContext->psDevInfo->pvMMUContextList; - +#if defined(SUPPORT_PDUMP_MULTI_PROCESS) + PVRSRV_SGXDEV_INFO *psDevInfo = psMMUContext->psDevInfo; +#endif while(psMMUContext) { MakeKernelPageReadWrite(psMMUContext->pvPDCpuVAddr); @@ -1482,7 +1512,7 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT pui32PDEntry += ui32PDIndex; /* insert the page, specify the data page size and make the pde valid */ - pui32PDEntry[i] = (sDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT) + pui32PDEntry[i] = (IMG_UINT32)(sDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT) | pMMUHeap->ui32PDEPageSizeCtrl | SGX_MMU_PDE_VALID; MakeKernelPageReadOnly(psMMUContext->pvPDCpuVAddr); @@ -1492,8 +1522,16 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT if(psMMUContext->bPDumpActive) #endif { - //PDUMPCOMMENT("_DeferredAllocPTs: Dumping shared PDEs on context %d (%s)", psMMUContext->ui32PDumpMMUContextID, (psMMUContext->bPDumpActive) ? "active" : ""); - PDUMPPDENTRIES(&pMMUHeap->sMMUAttrib, psMMUContext->hPDOSMemHandle, (IMG_VOID*)&pui32PDEntry[i], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG); +#if defined(SUPPORT_PDUMP_MULTI_PROCESS) + /* + Any modification of the uKernel memory context + needs to be PDumped when we're multi-process + */ + IMG_UINT32 ui32HeapFlags = ( psMMUContext->sPDDevPAddr.uiAddr == psDevInfo->sKernelPDDevPAddr.uiAddr ) ? PDUMP_FLAGS_PERSISTENT : 0; +#else + IMG_UINT32 ui32HeapFlags = 0; +#endif + PDUMPPDENTRIES(&pMMUHeap->sMMUAttrib, psMMUContext->hPDOSMemHandle, (IMG_VOID*)&pui32PDEntry[i], sizeof(IMG_UINT32), ui32HeapFlags, IMG_FALSE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG); } #endif /* PDUMP */ /* advance to next context */ @@ -1509,12 +1547,11 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT { MakeKernelPageReadWrite(pMMUHeap->psMMUContext->pvPDCpuVAddr); /* insert Page Table into only this memory context */ - pui32PDEntry[i] = (sDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT) + pui32PDEntry[i] = (IMG_UINT32)(sDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT) | pMMUHeap->ui32PDEPageSizeCtrl | SGX_MMU_PDE_VALID; MakeKernelPageReadOnly(pMMUHeap->psMMUContext->pvPDCpuVAddr); /* pdump the PD Page modifications */ - //PDUMPCOMMENT("_DeferredAllocPTs: Dumping kernel PDEs on context %d (%s)", pMMUHeap->psMMUContext->ui32PDumpMMUContextID, (pMMUHeap->psMMUContext->bPDumpActive) ? "active" : ""); PDUMPPDENTRIES(&pMMUHeap->sMMUAttrib, pMMUHeap->psMMUContext->hPDOSMemHandle, (IMG_VOID*)&pui32PDEntry[i], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG); break; } @@ -1918,6 +1955,15 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I } else { + /* + We cannot use IMG_SYS_PHYADDR here, as that is 64-bit for 32-bit PAE builds. + The physical address in this call to RA_Alloc is specifically the SysPAddr + of local (card) space, and it is highly unlikely we would ever need to + support > 4GB of local (card) memory (this does assume that such local + memory will be mapped into System physical memory space at a low address so + that any and all local memory exists within the 4GB SYSPAddr range). + */ + IMG_UINTPTR_T uiLocalPAddr; IMG_SYS_PHYADDR sSysPAddr; /* allocate from the device's local memory arena */ @@ -1930,12 +1976,15 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I 0, IMG_NULL, 0, - &(sSysPAddr.uiAddr))!= IMG_TRUE) + &uiLocalPAddr)!= IMG_TRUE) { PVR_DPF((PVR_DBG_ERROR, "MMU_Initialise: ERROR call to RA_Alloc failed")); return PVRSRV_ERROR_FAILED_TO_ALLOC_VIRT_MEMORY; } + /* Munge the local PAddr back into the SysPAddr */ + sSysPAddr.uiAddr = uiLocalPAddr; + /* derive the CPU virtual address */ sCpuPAddr = SysSysPAddrToCpuPAddr(sSysPAddr); sPDDevPAddr = SysSysPAddrToDevPAddr(PVRSRV_DEVICE_TYPE_SGX, sSysPAddr); @@ -1967,12 +2016,15 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I 0, IMG_NULL, 0, - &(sSysPAddr.uiAddr))!= IMG_TRUE) + &uiLocalPAddr)!= IMG_TRUE) { PVR_DPF((PVR_DBG_ERROR, "MMU_Initialise: ERROR call to RA_Alloc failed")); return PVRSRV_ERROR_FAILED_TO_ALLOC_VIRT_MEMORY; } + /* Munge the local PAddr back into the SysPAddr */ + sSysPAddr.uiAddr = uiLocalPAddr; + /* derive the CPU virtual address */ sCpuPAddr = SysSysPAddrToCpuPAddr(sSysPAddr); psDevInfo->sDummyPTDevPAddr = SysSysPAddrToDevPAddr(PVRSRV_DEVICE_TYPE_SGX, sSysPAddr); @@ -1996,12 +2048,15 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I 0, IMG_NULL, 0, - &(sSysPAddr.uiAddr))!= IMG_TRUE) + &uiLocalPAddr)!= IMG_TRUE) { PVR_DPF((PVR_DBG_ERROR, "MMU_Initialise: ERROR call to RA_Alloc failed")); return PVRSRV_ERROR_FAILED_TO_ALLOC_VIRT_MEMORY; } + /* Munge the local PAddr back into the SysPAddr */ + sSysPAddr.uiAddr = uiLocalPAddr; + /* derive the CPU virtual address */ sCpuPAddr = SysSysPAddrToCpuPAddr(sSysPAddr); psDevInfo->sDummyDataDevPAddr = SysSysPAddrToDevPAddr(PVRSRV_DEVICE_TYPE_SGX, sSysPAddr); @@ -2031,12 +2086,15 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I 0, IMG_NULL, 0, - &(sSysPAddr.uiAddr))!= IMG_TRUE) + &uiLocalPAddr)!= IMG_TRUE) { PVR_DPF((PVR_DBG_ERROR, "MMU_Initialise: ERROR call to RA_Alloc failed")); return PVRSRV_ERROR_FAILED_TO_ALLOC_VIRT_MEMORY; } + /* Munge the local PAddr back into the SysPAddr */ + sSysPAddr.uiAddr = uiLocalPAddr; + /* derive the CPU virtual address */ sCpuPAddr = SysSysPAddrToCpuPAddr(sSysPAddr); psDevInfo->sBRN31620DummyPageDevPAddr = SysSysPAddrToDevPAddr(PVRSRV_DEVICE_TYPE_SGX, sSysPAddr); @@ -2069,12 +2127,15 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I 0, IMG_NULL, 0, - &(sSysPAddr.uiAddr))!= IMG_TRUE) + &uiLocalPAddr)!= IMG_TRUE) { PVR_DPF((PVR_DBG_ERROR, "MMU_Initialise: ERROR call to RA_Alloc failed")); return PVRSRV_ERROR_FAILED_TO_ALLOC_VIRT_MEMORY; } + /* Munge the local PAddr back into the SysPAddr */ + sSysPAddr.uiAddr = uiLocalPAddr; + /* derive the CPU virtual address */ sCpuPAddr = SysSysPAddrToCpuPAddr(sSysPAddr); psDevInfo->sBRN31620DummyPTDevPAddr = SysSysPAddrToDevPAddr(PVRSRV_DEVICE_TYPE_SGX, sSysPAddr); @@ -2123,13 +2184,7 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I } #endif /* SUPPORT_PDUMP_MULTI_PROCESS */ /* pdump the PD malloc */ -#if IMG_ADDRSPACE_PHYSADDR_BITS == 32 - PDUMPCOMMENT("Alloc page directory for new MMU context (PDDevPAddr == 0x%08x)", - sPDDevPAddr.uiAddr); -#else - PDUMPCOMMENT("Alloc page directory for new MMU context, 64-bit arch detected (PDDevPAddr == 0x%08x%08x)", - sPDDevPAddr.uiHighAddr, sPDDevPAddr.uiAddr); -#endif + PDUMPCOMMENT("Alloc page directory for new MMU context (PDDevPAddr == 0x" DEVPADDR_FMT ")", sPDDevPAddr.uiAddr); PDUMPMALLOCPAGETABLE(&psDeviceNode->sDevId, hPDOSMemHandle, 0, pvPDCpuVAddr, SGX_MMU_PAGE_SIZE, 0, PDUMP_PD_UNIQUETAG); #endif /* PDUMP */ @@ -2377,13 +2432,8 @@ MMU_Finalise (MMU_CONTEXT *psMMUContext) PDUMPCLEARMMUCONTEXT(PVRSRV_DEVICE_TYPE_SGX, psMMUContext->psDeviceNode->sDevId.pszPDumpDevName, psMMUContext->ui32PDumpMMUContextID, 2); /* pdump the PD free */ -#if IMG_ADDRSPACE_PHYSADDR_BITS == 32 - PDUMPCOMMENT("Free page directory (PDDevPAddr == 0x%08x)", + PDUMPCOMMENT("Free page directory (PDDevPAddr == 0x" DEVPADDR_FMT ")", psMMUContext->sPDDevPAddr.uiAddr); -#else - PDUMPCOMMENT("Free page directory, 64-bit arch detected (PDDevPAddr == 0x%08x%08x)", - psMMUContext->sPDDevPAddr.uiHighAddr, psMMUContext->sPDDevPAddr.uiAddr); -#endif #endif /* PDUMP */ PDUMPFREEPAGETABLE(&psMMUContext->psDeviceNode->sDevId, psMMUContext->hPDOSMemHandle, psMMUContext->pvPDCpuVAddr, SGX_MMU_PAGE_SIZE, 0, PDUMP_PT_UNIQUETAG); @@ -2467,8 +2517,8 @@ MMU_Finalise (MMU_CONTEXT *psMMUContext) SGX_MMU_PAGE_SIZE, PVRSRV_HAP_WRITECOMBINE|PVRSRV_HAP_KERNEL_ONLY, psMMUContext->hPDOSMemHandle); - /* and free the memory */ - RA_Free (psMMUContext->psDeviceNode->psLocalDevMemArena, sSysPAddr.uiAddr, IMG_FALSE); + /* and free the memory, Note that the cast to IMG_UINTPTR_T is ok as we're local mem. */ + RA_Free (psMMUContext->psDeviceNode->psLocalDevMemArena, (IMG_UINTPTR_T)sSysPAddr.uiAddr, IMG_FALSE); #if defined(SUPPORT_SGX_MMU_DUMMY_PAGE) /* if this is the last context free the dummy pages too */ @@ -2819,16 +2869,16 @@ MMU_UnmapPagesAndFreePTs (MMU_HEAP *psMMUHeap, RETURNS: ******************************************************************************/ static IMG_VOID MMU_FreePageTables(IMG_PVOID pvMMUHeap, - IMG_SIZE_T ui32Start, - IMG_SIZE_T ui32End, + IMG_SIZE_T uStart, + IMG_SIZE_T uEnd, IMG_HANDLE hUniqueTag) { MMU_HEAP *pMMUHeap = (MMU_HEAP*)pvMMUHeap; IMG_DEV_VIRTADDR Start; - Start.uiAddr = (IMG_UINT32)ui32Start; + Start.uiAddr = (IMG_UINT32)uStart; - MMU_UnmapPagesAndFreePTs(pMMUHeap, Start, (IMG_UINT32)((ui32End - ui32Start) >> pMMUHeap->ui32PTShift), hUniqueTag); + MMU_UnmapPagesAndFreePTs(pMMUHeap, Start, (IMG_UINT32)((uEnd - uStart) >> pMMUHeap->ui32PTShift), hUniqueTag); } /*! @@ -3086,7 +3136,7 @@ MMU_Alloc (MMU_HEAP *pMMUHeap, IMG_BOOL bStatus; PVR_DPF ((PVR_DBG_MESSAGE, - "MMU_Alloc: uSize=0x%x, flags=0x%x, align=0x%x", + "MMU_Alloc: uSize=0x%" SIZE_T_FMT_LEN "x, flags=0x%x, align=0x%x", uSize, uFlags, uDevVAddrAlignment)); /* @@ -3108,10 +3158,19 @@ MMU_Alloc (MMU_HEAP *pMMUHeap, &uiAddr); if(!bStatus) { - PVR_DPF((PVR_DBG_ERROR,"MMU_Alloc: RA_Alloc of VMArena failed")); - PVR_DPF((PVR_DBG_ERROR,"MMU_Alloc: Alloc of DevVAddr failed from heap %s ID%d", - pMMUHeap->psDevArena->pszName, - pMMUHeap->psDevArena->ui32HeapID)); + IMG_CHAR asCurrentProcessName[128]; + + PVR_DPF((PVR_DBG_ERROR,"MMU_Alloc: RA_Alloc of VMArena failed")); + OSGetCurrentProcessNameKM(asCurrentProcessName, 128); + PVR_DPF((PVR_DBG_ERROR,"MMU_Alloc: Alloc of DevVAddr failed from heap %s ID%d, pid: %d, task: %s", + pMMUHeap->psDevArena->pszName, + pMMUHeap->psDevArena->ui32HeapID, + OSGetCurrentProcessIDKM(), + asCurrentProcessName)); + #if defined (MEM_TRACK_INFO_DEBUG) + PVRSRVPrintMemTrackInfo(0); + #endif + return bStatus; } @@ -3467,7 +3526,10 @@ MMU_MapPage (MMU_HEAP *pMMUHeap, DevVAddr.uiAddr >> pMMUHeap->ui32PDShift, ui32Index )); PVR_DPF((PVR_DBG_ERROR, "MMU_MapPage: Page table entry value: 0x%08X", uTmp)); - PVR_DPF((PVR_DBG_ERROR, "MMU_MapPage: Physical page to map: 0x%08X", DevPAddr.uiAddr)); + + PVR_DPF((PVR_DBG_ERROR, "MMU_MapPage: Physical page to map: 0x" DEVPADDR_FMT, + DevPAddr.uiAddr)); + #if PT_DUMP DumpPT(ppsPTInfoList[0]); #endif @@ -3483,7 +3545,7 @@ MMU_MapPage (MMU_HEAP *pMMUHeap, MakeKernelPageReadWrite(ppsPTInfoList[0]->PTPageCpuVAddr); /* map in the physical page */ - pui32Tmp[ui32Index] = ((DevPAddr.uiAddr>>SGX_MMU_PTE_ADDR_ALIGNSHIFT) + pui32Tmp[ui32Index] = ((IMG_UINT32)(DevPAddr.uiAddr>>SGX_MMU_PTE_ADDR_ALIGNSHIFT) & ((~pMMUHeap->ui32DataPageMask)>>SGX_MMU_PTE_ADDR_ALIGNSHIFT)) | SGX_MMU_PTE_VALID | ui32MMUFlags; @@ -3546,10 +3608,14 @@ MMU_MapScatter (MMU_HEAP *pMMUHeap, DevVAddr.uiAddr += pMMUHeap->ui32DataPageSize; PVR_DPF ((PVR_DBG_MESSAGE, - "MMU_MapScatter: devVAddr=%08X, SysAddr=%08X, size=0x%x/0x%x", + "MMU_MapScatter: devVAddr=%x, SysAddr=" SYSPADDR_FMT ", size=0x%x/0x%" SIZE_T_FMT_LEN "x", DevVAddr.uiAddr, sSysAddr.uiAddr, uCount, uSize)); } +#if (SGX_FEATURE_PT_CACHE_ENTRIES_PER_LINE > 1) + MMU_InvalidatePageTableCache(pMMUHeap->psMMUContext->psDevInfo); +#endif + #if defined(PDUMP) MMU_PDumpPageTables (pMMUHeap, MapBaseDevVAddr, uSize, IMG_FALSE, hUniqueTag); #endif /* #if defined(PDUMP) */ @@ -3589,7 +3655,7 @@ MMU_MapPages (MMU_HEAP *pMMUHeap, PVR_ASSERT (pMMUHeap != IMG_NULL); - PVR_DPF ((PVR_DBG_MESSAGE, "MMU_MapPages: heap:%s, heap_id:%d devVAddr=%08X, SysPAddr=%08X, size=0x%x", + PVR_DPF ((PVR_DBG_MESSAGE, "MMU_MapPages: heap:%s, heap_id:%d devVAddr=%08X, SysPAddr=" SYSPADDR_FMT ", size=0x%" SIZE_T_FMT_LEN "x", pMMUHeap->psDevArena->pszName, pMMUHeap->psDevArena->ui32HeapID, DevVAddr.uiAddr, @@ -3627,6 +3693,10 @@ MMU_MapPages (MMU_HEAP *pMMUHeap, DevPAddr.uiAddr += ui32PAdvance; } +#if (SGX_FEATURE_PT_CACHE_ENTRIES_PER_LINE > 1) + MMU_InvalidatePageTableCache(pMMUHeap->psMMUContext->psDevInfo); +#endif + #if defined(PDUMP) MMU_PDumpPageTables (pMMUHeap, MapBaseDevVAddr, uSize, IMG_FALSE, hUniqueTag); #endif /* #if defined(PDUMP) */ @@ -3677,7 +3747,7 @@ MMU_MapPagesSparse (MMU_HEAP *pMMUHeap, PVR_ASSERT (pMMUHeap != IMG_NULL); - PVR_DPF ((PVR_DBG_MESSAGE, "MMU_MapPagesSparse: heap:%s, heap_id:%d devVAddr=%08X, SysPAddr=%08X, VM space=0x%x, PHYS space=0x%x", + PVR_DPF ((PVR_DBG_MESSAGE, "MMU_MapPagesSparse: heap:%s, heap_id:%d devVAddr=%08X, SysPAddr=" SYSPADDR_FMT ", VM space=0x%" SIZE_T_FMT_LEN "x, PHYS space=0x%x", pMMUHeap->psDevArena->pszName, pMMUHeap->psDevArena->ui32HeapID, DevVAddr.uiAddr, @@ -3720,6 +3790,10 @@ MMU_MapPagesSparse (MMU_HEAP *pMMUHeap, } pMMUHeap->bHasSparseMappings = IMG_TRUE; +#if (SGX_FEATURE_PT_CACHE_ENTRIES_PER_LINE > 1) + MMU_InvalidatePageTableCache(pMMUHeap->psMMUContext->psDevInfo); +#endif + #if defined(PDUMP) MMU_PDumpPageTables (pMMUHeap, MapBaseDevVAddr, uSizeVM, IMG_FALSE, hUniqueTag); #endif /* #if defined(PDUMP) */ @@ -3772,10 +3846,10 @@ MMU_MapShadow (MMU_HEAP *pMMUHeap, #endif PVR_DPF ((PVR_DBG_MESSAGE, - "MMU_MapShadow: DevVAddr:%08X, Bytes:0x%x, CPUVAddr:%08X", + "MMU_MapShadow: DevVAddr:%08X, Bytes:0x%" SIZE_T_FMT_LEN "x, CPUVAddr:%p", MapBaseDevVAddr.uiAddr, uByteSize, - (IMG_UINTPTR_T)CpuVAddr)); + CpuVAddr)); /* set the virtual and physical advance */ ui32VAdvance = pMMUHeap->ui32DataPageSize; @@ -3817,9 +3891,9 @@ MMU_MapShadow (MMU_HEAP *pMMUHeap, PVR_ASSERT((DevPAddr.uiAddr & pMMUHeap->ui32DataPageMask) == 0); PVR_DPF ((PVR_DBG_MESSAGE, - "Offset=0x%x: CpuVAddr=%08X, CpuPAddr=%08X, DevVAddr=%08X, DevPAddr=%08X", + "Offset=0x%x: CpuVAddr=%p, CpuPAddr=" CPUPADDR_FMT ", DevVAddr=%08X, DevPAddr=" DEVPADDR_FMT, uOffset, - (IMG_UINTPTR_T)CpuVAddr + uOffset, + (IMG_PVOID)((IMG_UINTPTR_T)CpuVAddr + uOffset), CpuPAddr.uiAddr, MapDevVAddr.uiAddr, DevPAddr.uiAddr)); @@ -3831,6 +3905,10 @@ MMU_MapShadow (MMU_HEAP *pMMUHeap, uOffset += ui32PAdvance; } +#if (SGX_FEATURE_PT_CACHE_ENTRIES_PER_LINE > 1) + MMU_InvalidatePageTableCache(pMMUHeap->psMMUContext->psDevInfo); +#endif + #if defined(PDUMP) MMU_PDumpPageTables (pMMUHeap, MapBaseDevVAddr, uByteSize, IMG_FALSE, hUniqueTag); #endif /* #if defined(PDUMP) */ @@ -3894,10 +3972,10 @@ MMU_MapShadowSparse (MMU_HEAP *pMMUHeap, #endif PVR_DPF ((PVR_DBG_MESSAGE, - "MMU_MapShadowSparse: DevVAddr:%08X, VM space:0x%x, CPUVAddr:%08X PHYS space:0x%x", + "MMU_MapShadowSparse: DevVAddr:%08X, VM space:0x%" SIZE_T_FMT_LEN "x, CPUVAddr:%p PHYS space:0x%x", MapBaseDevVAddr.uiAddr, uiSizeVM, - (IMG_UINTPTR_T)CpuVAddr, + CpuVAddr, ui32ChunkSize * ui32NumPhysChunks)); /* set the virtual and physical advance */ @@ -3937,9 +4015,9 @@ MMU_MapShadowSparse (MMU_HEAP *pMMUHeap, PVR_ASSERT((DevPAddr.uiAddr & pMMUHeap->ui32DataPageMask) == 0); PVR_DPF ((PVR_DBG_MESSAGE, - "Offset=0x%x: CpuVAddr=%08X, CpuPAddr=%08X, DevVAddr=%08X, DevPAddr=%08X", + "Offset=0x%x: CpuVAddr=%p, CpuPAddr=" CPUPADDR_FMT ", DevVAddr=%08X, DevPAddr=" DEVPADDR_FMT, uOffset, - (IMG_UINTPTR_T)CpuVAddr + uOffset, + (void *)((IMG_UINTPTR_T)CpuVAddr + uOffset), CpuPAddr.uiAddr, MapDevVAddr.uiAddr, DevPAddr.uiAddr)); @@ -3959,6 +4037,11 @@ MMU_MapShadowSparse (MMU_HEAP *pMMUHeap, } pMMUHeap->bHasSparseMappings = IMG_TRUE; + +#if (SGX_FEATURE_PT_CACHE_ENTRIES_PER_LINE > 1) + MMU_InvalidatePageTableCache(pMMUHeap->psMMUContext->psDevInfo); +#endif + #if defined(PDUMP) MMU_PDumpPageTables (pMMUHeap, MapBaseDevVAddr, uiSizeVM, IMG_FALSE, hUniqueTag); #endif /* #if defined(PDUMP) */ @@ -4261,6 +4344,16 @@ PVRSRV_ERROR MMU_BIFResetPDAlloc(PVRSRV_SGXDEV_INFO *psDevInfo) { /* non-UMA system */ + /* + We cannot use IMG_SYS_PHYADDR here, as that is 64-bit for 32-bit PAE builds. + The physical address in this call to RA_Alloc is specifically the SysPAddr + of local (card) space, and it is highly unlikely we would ever need to + support > 4GB of local (card) memory (this does assume that such local + memory will be mapped into System physical memory space at a low address so + that any and all local memory exists within the 4GB SYSPAddr range). + */ + IMG_UINTPTR_T uiLocalPAddr; + if(RA_Alloc(psLocalDevMemArena, 3 * SGX_MMU_PAGE_SIZE, IMG_NULL, @@ -4270,12 +4363,15 @@ PVRSRV_ERROR MMU_BIFResetPDAlloc(PVRSRV_SGXDEV_INFO *psDevInfo) 0, IMG_NULL, 0, - &(sMemBlockSysPAddr.uiAddr)) != IMG_TRUE) + &uiLocalPAddr) != IMG_TRUE) { PVR_DPF((PVR_DBG_ERROR, "MMU_BIFResetPDAlloc: ERROR call to RA_Alloc failed")); return PVRSRV_ERROR_OUT_OF_MEMORY; } + /* Munge the local PAddr back into the SysPAddr */ + sMemBlockSysPAddr.uiAddr = uiLocalPAddr; + /* derive the CPU virtual address */ sMemBlockCpuPAddr = SysSysPAddrToCpuPAddr(sMemBlockSysPAddr); pui8MemBlock = OSMapPhysToLin(sMemBlockCpuPAddr, @@ -4342,7 +4438,8 @@ IMG_VOID MMU_BIFResetPDFree(PVRSRV_SGXDEV_INFO *psDevInfo) psDevInfo->hBIFResetPDOSMemHandle); sPDSysPAddr = SysDevPAddrToSysPAddr(PVRSRV_DEVICE_TYPE_SGX, psDevInfo->sBIFResetPDDevPAddr); - RA_Free(psLocalDevMemArena, sPDSysPAddr.uiAddr, IMG_FALSE); + /* Note that the cast to IMG_UINTPTR_T is ok as we're local mem. */ + RA_Free(psLocalDevMemArena, (IMG_UINTPTR_T)sPDSysPAddr.uiAddr, IMG_FALSE); } } @@ -4421,7 +4518,7 @@ PVRSRV_ERROR MMU_MapExtSystemCacheRegs(PVRSRV_DEVICE_NODE *psDeviceNode) { IMG_CHAR szScript[128]; - sprintf(szScript, "MALLOC :EXTSYSCACHE:PA_%08X%08X %u %u 0x%08X\r\n", 0, psDevInfo->sExtSysCacheRegsDevPBase.uiAddr, SGX_MMU_PAGE_SIZE, SGX_MMU_PAGE_SIZE, psDevInfo->sExtSysCacheRegsDevPBase.uiAddr); + sprintf(szScript, "MALLOC :EXTSYSCACHE:PA_%08X%08X %u %u 0x%p\r\n", 0, psDevInfo->sExtSysCacheRegsDevPBase.uiAddr, SGX_MMU_PAGE_SIZE, SGX_MMU_PAGE_SIZE, psDevInfo->sExtSysCacheRegsDevPBase.uiAddr); PDumpOSWriteString2(szScript, PDUMP_FLAGS_CONTINUOUS); } #endif @@ -4454,13 +4551,13 @@ PVRSRV_ERROR MMU_MapExtSystemCacheRegs(PVRSRV_DEVICE_NODE *psDeviceNode) eErr = PDumpOSBufprintf(hScript, ui32MaxLenScript, - "WRW :%s:PA_%08X%08X:0x%08X :%s:PA_%08X%08X:0x%08X\r\n", + "WRW :%s:PA_%p%p:0x%08X :%s:PA_%p%08X:0x%08X\r\n", sMMUAttrib.sDevId.pszPDumpDevName, - (IMG_UINT32)(IMG_UINTPTR_T)PDUMP_PT_UNIQUETAG, - (sDevPAddr.uiAddr) & ~ui32PageMask, + PDUMP_PT_UNIQUETAG, + (IMG_PVOID)((sDevPAddr.uiAddr) & ~ui32PageMask), (sDevPAddr.uiAddr) & ui32PageMask, "EXTSYSCACHE", - (IMG_UINT32)(IMG_UINTPTR_T)PDUMP_PD_UNIQUETAG, + PDUMP_PD_UNIQUETAG, (ui32PTE & sMMUAttrib.ui32PDEMask) << sMMUAttrib.ui32PTEAlignShift, ui32PTE & ~sMMUAttrib.ui32PDEMask); if(eErr != PVRSRV_OK) @@ -4560,7 +4657,7 @@ static IMG_VOID PageTest(IMG_VOID* pMem, IMG_DEV_PHYADDR sDevPAddr) if (ui32WriteData != ui32ReadData) { // Mem fault - PVR_DPF ((PVR_DBG_ERROR, "Error - memory page test failed at device phys address 0x%08X", sDevPAddr.uiAddr + (n<<2) )); + PVR_DPF ((PVR_DBG_ERROR, "Error - memory page test failed at device phys address 0x" DEVPADDR_FMT, sDevPAddr.uiAddr + (n<<2) )); PVR_DBG_BREAK; bOK = IMG_FALSE; } @@ -4576,7 +4673,7 @@ static IMG_VOID PageTest(IMG_VOID* pMem, IMG_DEV_PHYADDR sDevPAddr) if (ui32WriteData != ui32ReadData) { // Mem fault - PVR_DPF ((PVR_DBG_ERROR, "Error - memory page test failed at device phys address 0x%08X", sDevPAddr.uiAddr + (n<<2) )); + PVR_DPF ((PVR_DBG_ERROR, "Error - memory page test failed at device phys address 0x" DEVPADDR_FMT, sDevPAddr.uiAddr + (n<<2))); PVR_DBG_BREAK; bOK = IMG_FALSE; } @@ -4584,11 +4681,11 @@ static IMG_VOID PageTest(IMG_VOID* pMem, IMG_DEV_PHYADDR sDevPAddr) if (bOK) { - PVR_DPF ((PVR_DBG_VERBOSE, "MMU Page 0x%08X is OK", sDevPAddr.uiAddr)); + PVR_DPF ((PVR_DBG_VERBOSE, "MMU Page 0x" DEVPADDR_FMT " is OK", sDevPAddr.uiAddr)); } else { - PVR_DPF ((PVR_DBG_VERBOSE, "MMU Page 0x%08X *** FAILED ***", sDevPAddr.uiAddr)); + PVR_DPF ((PVR_DBG_VERBOSE, "MMU Page 0x" DEVPADDR_FMT " *** FAILED ***", sDevPAddr.uiAddr)); } } #endif diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/mmu.h b/drivers/gpu/pvr/services4/srvkm/devices/sgx/mmu.h index 3c849fc982b..3c849fc982b 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/mmu.h +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/mmu.h diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/pb.c b/drivers/gpu/pvr/services4/srvkm/devices/sgx/pb.c index 4ed18bb97e6..26e2ded8053 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/pb.c +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/pb.c @@ -100,7 +100,7 @@ SGXFindSharedPBDescKM(PVRSRV_PER_PROCESS_DATA *psPerProc, ui32TotalPBSize, psStubPBDesc->ui32TotalPBSize)); } - if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, + if(OSAllocMem(PVRSRV_OS_NON_PAGEABLE_HEAP, sizeof(PVRSRV_KERNEL_MEM_INFO *) * psStubPBDesc->ui32SubKernelMemInfosCount, (IMG_VOID **)&ppsSharedPBDescSubKernelMemInfos, diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgx_bridge_km.h b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgx_bridge_km.h index f281c4e141d..260a26506c1 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgx_bridge_km.h +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgx_bridge_km.h @@ -55,28 +55,16 @@ extern "C" { #endif IMG_IMPORT -#if defined (SUPPORT_SID_INTERFACE) -PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSFER_SGX_KICK_KM *psKick); -#else PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSFER_SGX_KICK *psKick); -#endif #if defined(SGX_FEATURE_2D_HARDWARE) IMG_IMPORT -#if defined (SUPPORT_SID_INTERFACE) -PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK_KM *psKick); -#else PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK *psKick); #endif -#endif IMG_IMPORT PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, -#if defined (SUPPORT_SID_INTERFACE) - SGX_CCB_KICK_KM *psCCBKick); -#else SGX_CCB_KICK *psCCBKick); -#endif IMG_IMPORT PVRSRV_ERROR SGXGetPhysPageAddrKM(IMG_HANDLE hDevMemHeap, @@ -114,21 +102,12 @@ PVRSRV_ERROR SGX2DQueryBlitsCompleteKM(PVRSRV_SGXDEV_INFO *psDevInfo, IMG_IMPORT PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, -#if defined (SUPPORT_SID_INTERFACE) - PVRSRV_HEAP_INFO_KM *pasHeapInfo, - IMG_DEV_PHYADDR *psPDDevPAddr); -#else SGX_BRIDGE_INFO_FOR_SRVINIT *psInitInfo); -#endif IMG_IMPORT PVRSRV_ERROR DevInitSGXPart2KM(PVRSRV_PER_PROCESS_DATA *psPerProc, IMG_HANDLE hDevHandle, -#if defined (SUPPORT_SID_INTERFACE) - SGX_BRIDGE_INIT_INFO_KM *psInitInfo); -#else SGX_BRIDGE_INIT_INFO *psInitInfo); -#endif /*! * ***************************************************************************** @@ -262,11 +241,7 @@ SGXAddSharedPBDescKM(PVRSRV_PER_PROCESS_DATA *psPerProc, ********************************************************************************/ IMG_IMPORT PVRSRV_ERROR SGXGetInternalDevInfoKM(IMG_HANDLE hDevCookie, -#if defined (SUPPORT_SID_INTERFACE) - SGX_INTERNAL_DEVINFO_KM *psSGXInternalDevInfo); -#else SGX_INTERNAL_DEVINFO *psSGXInternalDevInfo); -#endif #if defined (__cplusplus) } diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxconfig.h b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxconfig.h index b9ebab9894a..632ab5150ff 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxconfig.h +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxconfig.h @@ -56,13 +56,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SGX_KERNEL_DATA_HEAP_OFFSET 0x00000000 #endif -#if !defined(ION_HEAP_SIZE) && defined(SUPPORT_ION) - /* Default the Ion heap to 16MB */ - #define ION_HEAP_SIZE 0x01000000 -#else - #define ION_HEAP_SIZE 0 -#endif - #if SGX_FEATURE_ADDRESS_SPACE_SIZE == 32 #if defined(FIX_HW_BRN_31620) @@ -78,7 +71,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * For hybrid PB we have to split virtual PB range between the shared * PB and percontext PB due to the fact we only have one heap config * per device. - * If hybrid PB is enabled we split the space acording to HYBRID_SHARED_PB_SIZE. + * If hybrid PB is enabled we split the space according to HYBRID_SHARED_PB_SIZE. * i.e. HYBRID_SHARED_PB_SIZE defines the size of the shared PB and the * remainder is the size of the percontext PB. * If hybrid PB is not enabled then we still create both heaps (helps keep @@ -109,10 +102,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #endif #define SGX_SHARED_3DPARAMETERS_HEAP_BASE 0xC0000000 - /* Size is defiend above */ + /* Size is defined above */ #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_BASE (SGX_SHARED_3DPARAMETERS_HEAP_BASE + SGX_SHARED_3DPARAMETERS_SIZE) - /* Size is defiend above */ + /* Size is defined above */ #define SGX_TADATA_HEAP_BASE 0xD0000000 #define SGX_TADATA_HEAP_SIZE (0x0D000000-0x00001000) @@ -151,16 +144,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #endif #if !defined(SUPPORT_MEMORY_TILING) - #if defined (SUPPORT_ION) - #define SGX_GENERAL_HEAP_BASE 0x10000000 - #define SGX_GENERAL_HEAP_SIZE (0xC2000000-ION_HEAP_SIZE-0x00001000) - - #define SGX_ION_HEAP_BASE (SGX_GENERAL_HEAP_BASE+SGX_GENERAL_HEAP_SIZE+0x00001000) - #define SGX_ION_HEAP_SIZE (ION_HEAP_SIZE-0x00001000) - #else - #define SGX_GENERAL_HEAP_BASE 0x10000000 - #define SGX_GENERAL_HEAP_SIZE (0xC2000000-0x00001000) - #endif + #define SGX_GENERAL_HEAP_BASE 0x10000000 + #define SGX_GENERAL_HEAP_SIZE (0xC2000000-0x00001000) #else #include <sgx_msvdx_defs.h> /* Create heaps with memory tiling enabled. @@ -185,7 +170,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * For hybrid PB we have to split virtual PB range between the shared * PB and percontext PB due to the fact we only have one heap config * per device. - * If hybrid PB is enabled we split the space acording to HYBRID_SHARED_PB_SIZE. + * If hybrid PB is enabled we split the space according to HYBRID_SHARED_PB_SIZE. * i.e. HYBRID_SHARED_PB_SIZE defines the size of the shared PB and the * remainder is the size of the percontext PB. * If hybrid PB is not enabled then we still create both heaps (helps keep @@ -216,10 +201,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #endif #define SGX_SHARED_3DPARAMETERS_HEAP_BASE 0xD2000000 - /* Size is defiend above */ + /* Size is defined above */ #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_BASE (SGX_SHARED_3DPARAMETERS_HEAP_BASE + SGX_SHARED_3DPARAMETERS_SIZE) - /* Size is defiend above */ + /* Size is defined above */ #define SGX_TADATA_HEAP_BASE 0xE2000000 #define SGX_TADATA_HEAP_SIZE (0x0D000000-0x00001000) @@ -258,26 +243,22 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SGX_GENERAL_MAPPING_HEAP_SIZE (0x01800000-0x00001000-0x00001000) #define SGX_GENERAL_HEAP_BASE 0x01800000 - #define SGX_GENERAL_HEAP_SIZE (0x07000000-ION_HEAP_SIZE-0x00001000) + #define SGX_GENERAL_HEAP_SIZE (0x07000000-0x00001000) #else #define SGX_GENERAL_HEAP_BASE 0x00001000 #if defined(SUPPORT_LARGE_GENERAL_HEAP) - #define SGX_GENERAL_HEAP_SIZE (0x0B800000-ION_HEAP_SIZE-0x00001000-0x00001000) + #define SGX_GENERAL_HEAP_SIZE (0x0B800000-0x00001000-0x00001000) #else - #define SGX_GENERAL_HEAP_SIZE (0x08800000-ION_HEAP_SIZE-0x00001000-0x00001000) + #define SGX_GENERAL_HEAP_SIZE (0x08800000-0x00001000-0x00001000) #endif #endif -#if defined(SUPPORT_ION) - #define SGX_ION_HEAP_BASE (SGX_GENERAL_HEAP_BASE+SGX_GENERAL_HEAP_SIZE+0x00001000) - #define SGX_ION_HEAP_SIZE (ION_HEAP_SIZE-0x00001000) -#endif /* * For hybrid PB we have to split virtual PB range between the shared * PB and percontext PB due to the fact we only have one heap config * per device. - * If hybrid PB is enabled we split the space acording to HYBRID_SHARED_PB_SIZE. + * If hybrid PB is enabled we split the space according to HYBRID_SHARED_PB_SIZE. * i.e. HYBRID_SHARED_PB_SIZE defines the size of the shared PB and the * remainder is the size of the percontext PB. * If hybrid PB is not enabled then we still create both heaps (helps keep @@ -428,11 +409,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #error "sgxconfig.h: ERROR: SGX_VPB_TILED_HEAP overlaps SGX_3DPARAMETERS_HEAP" #endif #else - #if defined(SUPPORT_ION) - #if ((SGX_ION_HEAP_BASE + SGX_ION_HEAP_SIZE) >= SGX_SHARED_3DPARAMETERS_HEAP_BASE) - #error "sgxconfig.h: ERROR: SGX_ION_HEAP overlaps SGX_3DPARAMETERS_HEAP" - #endif - #endif #if ((SGX_GENERAL_HEAP_BASE + SGX_GENERAL_HEAP_SIZE) >= SGX_SHARED_3DPARAMETERS_HEAP_BASE) #error "sgxconfig.h: ERROR: SGX_GENERAL_HEAP overlaps SGX_3DPARAMETERS_HEAP" #endif diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxinfokm.h b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxinfokm.h index 125da097bf8..9a1ffcd452a 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxinfokm.h +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxinfokm.h @@ -71,7 +71,37 @@ extern "C" { /*Forward declaration*/ typedef struct _PVRSRV_STUB_PBDESC_ PVRSRV_STUB_PBDESC; +#if defined(SUPPORT_PVRSRV_ANDROID_SYSTRACE) +typedef struct _PVRSRV_SYSTRACE_JOB_ +{ + IMG_UINT32 ui32JobID; + IMG_UINT32 ui32FrameNum; + IMG_UINT32 ui32RTData; + +} PVRSRV_SYSTRACE_JOB; + +typedef struct _PVRSRV_SYSTRACE_CONTEXT_ +{ + IMG_UINT32 ui32PID; + IMG_UINT32 ui32CtxID; + /*Every PID has a circular buffer of jobs*/ + IMG_UINT32 ui32Start; + IMG_UINT32 ui32End; + IMG_UINT32 ui32CurrentJobID; + PVRSRV_SYSTRACE_JOB asJobs[16]; + +} PVRSRV_SYSTRACE_CONTEXT; + +typedef struct _PVRSRV_SYSTRACE_DATA_ +{ + IMG_UINT64 ui64LastHostTimestamp; + IMG_UINT32 ui32LastSGXClocksx16; + IMG_UINT32 ui32Index; + IMG_UINT32 ui32CurrentCtxID; + PVRSRV_SYSTRACE_CONTEXT asSystraceContext[8]; +} PVRSRV_SYSTRACE_DATA; +#endif typedef struct _PVRSRV_SGX_CCB_INFO_ *PPVRSRV_SGX_CCB_INFO; @@ -149,16 +179,6 @@ typedef struct _PVRSRV_SGXDEV_INFO_ PPVRSRV_KERNEL_MEM_INFO psKernelHWPerfCBMemInfo; /*!< Meminfo for hardware performace circular buffer */ PPVRSRV_KERNEL_MEM_INFO psKernelTASigBufferMemInfo; /*!< Meminfo for TA signature buffer */ PPVRSRV_KERNEL_MEM_INFO psKernel3DSigBufferMemInfo; /*!< Meminfo for 3D signature buffer */ -#if defined(FIX_HW_BRN_29702) - PPVRSRV_KERNEL_MEM_INFO psKernelCFIMemInfo; /*!< Meminfo for cfi */ -#endif -#if defined(FIX_HW_BRN_29823) - PPVRSRV_KERNEL_MEM_INFO psKernelDummyTermStreamMemInfo; /*!< Meminfo for dummy terminate stream */ -#endif -#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31559) - PPVRSRV_KERNEL_MEM_INFO psKernelVDMSnapShotBufferMemInfo; /*!< Meminfo for dummy snapshot buffer */ - PPVRSRV_KERNEL_MEM_INFO psKernelVDMCtrlStreamBufferMemInfo; /*!< Meminfo for dummy control stream */ -#endif #if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && \ defined(FIX_HW_BRN_33657) && defined(SUPPORT_SECURE_33657_FIX) PPVRSRV_KERNEL_MEM_INFO psKernelVDMStateUpdateBufferMemInfo; /*!< Meminfo for state update buffer */ @@ -269,6 +289,11 @@ typedef struct _PVRSRV_SGXDEV_INFO_ IMG_HANDLE hKernelMMUContext; #endif +#if defined(SUPPORT_PVRSRV_ANDROID_SYSTRACE) + IMG_BOOL bSystraceInitialised; + PVRSRV_SYSTRACE_DATA *psSystraceData; +#endif + } PVRSRV_SGXDEV_INFO; @@ -385,12 +410,6 @@ typedef struct _SGX_BRIDGE_INIT_INFO_KM_ IMG_HANDLE hKernelTASigBufferMemInfo; IMG_HANDLE hKernel3DSigBufferMemInfo; -#if defined(FIX_HW_BRN_29702) - IMG_HANDLE hKernelCFIMemInfo; -#endif -#if defined(FIX_HW_BRN_29823) - IMG_HANDLE hKernelDummyTermStreamMemInfo; -#endif #if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) IMG_HANDLE hKernelEDMStatusBufferMemInfo; #endif @@ -570,6 +589,8 @@ PVRSRV_ERROR SGXPostClockSpeedChange(IMG_HANDLE hDevHandle, IMG_VOID SGXPanic(PVRSRV_SGXDEV_INFO *psDevInfo); +IMG_VOID RunSGXREGDebugScripts(PVRSRV_SGXDEV_INFO *psDevInfo); + IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo, IMG_BOOL bDumpSGXRegs); diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxinit.c b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxinit.c index c8292818b4b..04b1748448e 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxinit.c +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxinit.c @@ -68,7 +68,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "srvkm.h" #include "ttrace.h" -extern int powering_down; +#if defined(SUPPORT_PVRSRV_ANDROID_SYSTRACE) +#include "systrace.h" +#endif + +IMG_UINT32 g_ui32HostIRQCountSample = 0; #if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) @@ -195,11 +199,7 @@ static IMG_UINT32 DeinitDevInfo(PVRSRV_SGXDEV_INFO *psDevInfo) ******************************************************************************/ static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc, PVRSRV_DEVICE_NODE *psDeviceNode, -#if defined (SUPPORT_SID_INTERFACE) - SGX_BRIDGE_INIT_INFO_KM *psInitInfo) -#else SGX_BRIDGE_INIT_INFO *psInitInfo) -#endif { PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice; PVRSRV_ERROR eError; @@ -237,16 +237,6 @@ static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc, #endif psDevInfo->psKernelTASigBufferMemInfo = psInitInfo->hKernelTASigBufferMemInfo; psDevInfo->psKernel3DSigBufferMemInfo = psInitInfo->hKernel3DSigBufferMemInfo; -#if defined(FIX_HW_BRN_29702) - psDevInfo->psKernelCFIMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelCFIMemInfo; -#endif -#if defined(FIX_HW_BRN_29823) - psDevInfo->psKernelDummyTermStreamMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelDummyTermStreamMemInfo; -#endif -#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31559) - psDevInfo->psKernelVDMSnapShotBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelVDMSnapShotBufferMemInfo; - psDevInfo->psKernelVDMCtrlStreamBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelVDMCtrlStreamBufferMemInfo; -#endif #if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && \ defined(FIX_HW_BRN_33657) && defined(SUPPORT_SECURE_33657_FIX) psDevInfo->psKernelVDMStateUpdateBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelVDMStateUpdateBufferMemInfo; @@ -344,13 +334,21 @@ static PVRSRV_ERROR SGXRunScript(PVRSRV_SGXDEV_INFO *psDevInfo, SGX_INIT_COMMAND } case SGX_INIT_OP_READ_HW_REG: { - OSReadHWReg(psDevInfo->pvRegsBaseKM, psComm->sReadHWReg.ui32Offset); + psComm->sReadHWReg.ui32Value = OSReadHWReg(psDevInfo->pvRegsBaseKM, psComm->sReadHWReg.ui32Offset); #if defined(PDUMP) PDUMPCOMMENT("SGXRunScript: Read HW reg operation"); PDumpRegRead(SGX_PDUMPREG_NAME, psComm->sReadHWReg.ui32Offset, PDUMP_FLAGS_CONTINUOUS); #endif break; } + case SGX_INIT_OP_PRINT_HW_REG: + { + psComm->sReadHWReg.ui32Value = OSReadHWReg(psDevInfo->pvRegsBaseKM, psComm->sReadHWReg.ui32Offset); + PVR_LOG(("\t(SGXREG) 0x%08X : 0x%08X", psComm->sReadHWReg.ui32Offset, psComm->sReadHWReg.ui32Value)); + + break; + } + #if defined(PDUMP) case SGX_INIT_OP_PDUMP_HW_REG: { @@ -377,6 +375,72 @@ static PVRSRV_ERROR SGXRunScript(PVRSRV_SGXDEV_INFO *psDevInfo, SGX_INIT_COMMAND return PVRSRV_ERROR_UNKNOWN_SCRIPT_OPERATION; } +/* Run scripts on given core */ +static PVRSRV_ERROR SGXRunScriptOnCore(PVRSRV_SGXDEV_INFO *psDevInfo, SGX_INIT_COMMAND *psScript, IMG_UINT32 ui32NumInitCommands, IMG_UINT32 ui32CoreNum) +{ + IMG_UINT32 ui32PC; + SGX_INIT_COMMAND *psComm; + +#if !defined(SGX_FEATURE_MP) + PVR_UNREFERENCED_PARAMETER(ui32CoreNum); +#endif + + for (ui32PC = 0, psComm = psScript; + ui32PC < ui32NumInitCommands; + ui32PC++, psComm++) + { + switch (psComm->eOp) + { + case SGX_INIT_OP_WRITE_HW_REG: + { + OSWriteHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(psComm->sWriteHWReg.ui32Offset,ui32CoreNum), psComm->sWriteHWReg.ui32Value); + PDUMPCOMMENT("SGXRunScriptOnCore: Write HW reg operation"); + PDUMPREG(SGX_PDUMPREG_NAME, SGX_MP_CORE_SELECT(psComm->sWriteHWReg.ui32Offset,ui32CoreNum), psComm->sWriteHWReg.ui32Value); + break; + } + case SGX_INIT_OP_READ_HW_REG: + { + psComm->sReadHWReg.ui32Value = OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(psComm->sReadHWReg.ui32Offset, ui32CoreNum)); +#if defined(PDUMP) + PDUMPCOMMENT("SGXRunScriptOnCore: Read HW reg operation"); + PDumpRegRead(SGX_PDUMPREG_NAME, SGX_MP_CORE_SELECT(psComm->sReadHWReg.ui32Offset,ui32CoreNum), PDUMP_FLAGS_CONTINUOUS); +#endif + break; + } + case SGX_INIT_OP_PRINT_HW_REG: + { + psComm->sReadHWReg.ui32Value = OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(psComm->sReadHWReg.ui32Offset,ui32CoreNum)); + PVR_LOG(("\t(SGXREG) 0x%08X : 0x%08X", SGX_MP_CORE_SELECT(psComm->sReadHWReg.ui32Offset, ui32CoreNum), psComm->sReadHWReg.ui32Value)); + + break; + } + +#if defined(PDUMP) + case SGX_INIT_OP_PDUMP_HW_REG: + { + PDUMPCOMMENT("SGXRunScriptOnCore: Dump HW reg operation"); + PDUMPREG(SGX_PDUMPREG_NAME, SGX_MP_CORE_SELECT(psComm->sPDumpHWReg.ui32Offset, ui32CoreNum), psComm->sPDumpHWReg.ui32Value); + break; + } +#endif + case SGX_INIT_OP_HALT: + { + return PVRSRV_OK; + } + case SGX_INIT_OP_ILLEGAL: + /* FALLTHROUGH */ + default: + { + PVR_DPF((PVR_DBG_ERROR,"SGXRunScriptOnCore: PC %d: Illegal command: %d", ui32PC, psComm->eOp)); + return PVRSRV_ERROR_UNKNOWN_SCRIPT_OPERATION; + } + } + + } + + return PVRSRV_ERROR_UNKNOWN_SCRIPT_OPERATION; +} + #if defined(SUPPORT_MEMORY_TILING) static PVRSRV_ERROR SGX_AllocMemTilingRangeInt(PVRSRV_SGXDEV_INFO *psDevInfo, IMG_UINT32 ui32Start, @@ -852,11 +916,7 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode) ******************************************************************************/ IMG_EXPORT -#if defined (SUPPORT_SID_INTERFACE) -PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, PVRSRV_HEAP_INFO_KM *pasHeapInfo, IMG_DEV_PHYADDR *psPDDevPAddr) -#else PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, SGX_BRIDGE_INFO_FOR_SRVINIT *psInitInfo) -#endif { PVRSRV_DEVICE_NODE *psDeviceNode; PVRSRV_SGXDEV_INFO *psDevInfo; @@ -867,15 +927,9 @@ PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, SGX_BRIDGE_INFO_FOR_S psDeviceNode = (PVRSRV_DEVICE_NODE *)hDevHandle; psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice; -#if defined (SUPPORT_SID_INTERFACE) - *psPDDevPAddr = psDevInfo->sKernelPDDevPAddr; - - eError = PVRSRVGetDeviceMemHeapsKM(hDevHandle, pasHeapInfo); -#else psInitInfo->sPDDevPAddr = psDevInfo->sKernelPDDevPAddr; eError = PVRSRVGetDeviceMemHeapsKM(hDevHandle, &psInitInfo->asHeapInfo[0]); -#endif if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR,"SGXGetInfoForSrvinit: PVRSRVGetDeviceMemHeapsKM failed (%d)", eError)); @@ -902,11 +956,7 @@ PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, SGX_BRIDGE_INFO_FOR_S IMG_EXPORT PVRSRV_ERROR DevInitSGXPart2KM (PVRSRV_PER_PROCESS_DATA *psPerProc, IMG_HANDLE hDevHandle, -#if defined (SUPPORT_SID_INTERFACE) - SGX_BRIDGE_INIT_INFO_KM *psInitInfo) -#else SGX_BRIDGE_INIT_INFO *psInitInfo) -#endif { PVRSRV_DEVICE_NODE *psDeviceNode; PVRSRV_SGXDEV_INFO *psDevInfo; @@ -1162,8 +1212,7 @@ static PVRSRV_ERROR DevDeInitSGX (IMG_VOID *pvDeviceNode) } } #endif /* #ifdef SGX_FEATURE_HOST_PORT */ - - + /* DeAllocate devinfo */ OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP, sizeof(PVRSRV_SGXDEV_INFO), @@ -1185,35 +1234,6 @@ static PVRSRV_ERROR DevDeInitSGX (IMG_VOID *pvDeviceNode) } -#if defined(RESTRICTED_REGISTERS) && defined(SGX_FEATURE_MP) - -/*! -******************************************************************************* - - @Function SGXDumpMasterDebugReg - - @Description - - Dump a single SGX debug register value - - @Input psDevInfo - SGX device info - @Input pszName - string used for logging - @Input ui32RegAddr - SGX register offset - - @Return IMG_VOID - -******************************************************************************/ -static IMG_VOID SGXDumpMasterDebugReg (PVRSRV_SGXDEV_INFO *psDevInfo, - IMG_CHAR *pszName, - IMG_UINT32 ui32RegAddr) -{ - IMG_UINT32 ui32RegVal; - ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, ui32RegAddr); - PVR_LOG(("(HYD) %s%08X", pszName, ui32RegVal)); -} - -#endif /* defined(RESTRICTED_REGISTERS) */ - /*! ******************************************************************************* @@ -1255,9 +1275,45 @@ static INLINE IMG_UINT32 GetDirListBaseReg(IMG_UINT32 ui32Index) } #endif -#if defined(CONFIG_DSSCOMP) -void dsscomp_kdump(void); +/*! + * ************************************************************************** + * @Function RunSGXREGDebugScripts + * @Description Runs the SGXREG debug scripts + * + * @Input PVRSRV_SGXDEV_INFO + * @Output + * @Return IMG_VOID + * **************************************************************************/ + +IMG_VOID RunSGXREGDebugScripts (PVRSRV_SGXDEV_INFO *psDevInfo) +{ + IMG_UINT32 ui32Core; + PVRSRV_ERROR eError; + + /* Run SGXREGDebug scripts */ +#if defined(SGX_FEATURE_MP) + PVR_LOG(("(HYD)")); + eError = SGXRunScript(psDevInfo, psDevInfo->sScripts.asSGXREGDebugCommandsMaster, SGX_MAX_PRINT_COMMANDS); + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR,"RunSGXREGDebugScripts: SGXREGDebugCommandsMaster SGXRunScript failed (%d)", eError)); + } #endif + + /* Run on each core */ + for (ui32Core = 0; ui32Core < SGX_FEATURE_MP_CORE_COUNT_3D; ui32Core++) + { + PVR_LOG(("(P%u)",ui32Core)); + eError = SGXRunScriptOnCore(psDevInfo, psDevInfo->sScripts.asSGXREGDebugCommandsSlave, SGX_MAX_PRINT_COMMANDS, ui32Core); + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR,"RunSGXREGDebugScripts: SGXREGDebugCommandsSlave SGXRunScript failed (%d)", eError)); + } + } + /* Scripts end */ +} + + /*! ******************************************************************************* @@ -1279,43 +1335,23 @@ IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo, { IMG_UINT32 ui32CoreNum; -#if defined(CONFIG_DSSCOMP) - dsscomp_kdump(); -#endif - PVR_LOG(("SGX debug (%s)", PVRVERSION_STRING)); if (bDumpSGXRegs) { - PVR_DPF((PVR_DBG_ERROR,"SGX Register Base Address (Linear): 0x%08X", (IMG_UINTPTR_T)psDevInfo->pvRegsBaseKM)); - PVR_DPF((PVR_DBG_ERROR,"SGX Register Base Address (Physical): 0x%08X", psDevInfo->sRegsPhysBase.uiAddr)); + PVR_DPF((PVR_DBG_ERROR,"SGX Register Base Address (Linear): 0x%p", psDevInfo->pvRegsBaseKM)); + PVR_DPF((PVR_DBG_ERROR,"SGX Register Base Address (Physical): 0x" SYSPADDR_FMT, psDevInfo->sRegsPhysBase.uiAddr)); + + /* Run SGXREGDebug Scripts */ + PVR_LOG(("Running SGXREG Debug Scripts:")); + RunSGXREGDebugScripts(psDevInfo); + PVR_LOG(("SGX Register Dump:")); SGXDumpDebugReg(psDevInfo, 0, "EUR_CR_CORE_ID: ", EUR_CR_CORE_ID); SGXDumpDebugReg(psDevInfo, 0, "EUR_CR_CORE_REVISION: ", EUR_CR_CORE_REVISION); -#if defined(RESTRICTED_REGISTERS) && defined(SGX_FEATURE_MP) - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_BIF_INT_STAT: ", EUR_CR_MASTER_BIF_INT_STAT); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_BIF_FAULT: ",EUR_CR_MASTER_BIF_FAULT); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_CLKGATESTATUS2: ",EUR_CR_MASTER_CLKGATESTATUS2 ); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_PIM_STATUS: ",EUR_CR_MASTER_VDM_PIM_STATUS); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_BIF_BANK_SET: ",EUR_CR_MASTER_BIF_BANK_SET); - - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_EVENT_STATUS: ",EUR_CR_MASTER_EVENT_STATUS); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_EVENT_STATUS2: ",EUR_CR_MASTER_EVENT_STATUS2); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_MP_PRIMITIVE: ",EUR_CR_MASTER_MP_PRIMITIVE); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_DPM_DPLIST_STATUS: ",EUR_CR_MASTER_DPM_DPLIST_STATUS); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_DPM_PROACTIVE_PIM_SPEC: ",EUR_CR_MASTER_DPM_PROACTIVE_PIM_SPEC); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_PAGE_MANAGEOP: ",EUR_CR_MASTER_DPM_PAGE_MANAGEOP); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_CONTEXT_STORE_SNAPSHOT: ",EUR_CR_MASTER_VDM_CONTEXT_STORE_SNAPSHOT); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_CONTEXT_LOAD_STATUS: ",EUR_CR_MASTER_VDM_CONTEXT_LOAD_STATUS); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_CONTEXT_STORE_STREAM: ",EUR_CR_MASTER_VDM_CONTEXT_STORE_STREAM); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_CONTEXT_STORE_STATUS: ",EUR_CR_MASTER_VDM_CONTEXT_STORE_STATUS); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_CONTEXT_STORE_STATE0: ",EUR_CR_MASTER_VDM_CONTEXT_STORE_STATE0); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_CONTEXT_STORE_STATE1: ",EUR_CR_MASTER_VDM_CONTEXT_STORE_STATE1); - SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_WAIT_FOR_KICK: ",EUR_CR_MASTER_VDM_WAIT_FOR_KICK); -#endif + for (ui32CoreNum = 0; ui32CoreNum < SGX_FEATURE_MP_CORE_COUNT_3D; ui32CoreNum++) { - /* Dump HW event status */ SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_STATUS: ", EUR_CR_EVENT_STATUS); SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_STATUS2: ", EUR_CR_EVENT_STATUS2); SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_BIF_CTRL: ", EUR_CR_BIF_CTRL); @@ -1329,37 +1365,6 @@ IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo, #if defined(EUR_CR_PDS_PC_BASE) SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_PDS_PC_BASE: ", EUR_CR_PDS_PC_BASE); #endif -#if defined(RESTRICTED_REGISTERS) - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_BIF_BANK_SET: ", EUR_CR_BIF_BANK_SET); - - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_CLKGATECTL: ", EUR_CR_CLKGATECTL); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_CLKGATESTATUS: ", EUR_CR_CLKGATESTATUS); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_MTE_CTRL: ", EUR_CR_MTE_CTRL); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_OTHER_PDS_EXEC: ", EUR_CR_EVENT_OTHER_PDS_EXEC); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_OTHER_PDS_DATA: ", EUR_CR_EVENT_OTHER_PDS_DATA); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_OTHER_PDS_INFO: ", EUR_CR_EVENT_OTHER_PDS_INFO); - - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_ZLS_PAGE_THRESHOLD: ", EUR_CR_DPM_ZLS_PAGE_THRESHOLD); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_TA_GLOBAL_LIST: ", EUR_CR_DPM_TA_GLOBAL_LIST); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_STATE_CONTEXT_ID: ", EUR_CR_DPM_STATE_CONTEXT_ID); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_CONTEXT_PB_BASE: ", EUR_CR_DPM_CONTEXT_PB_BASE); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_TA_ALLOC_FREE_LIST_STATUS1: ", EUR_CR_DPM_TA_ALLOC_FREE_LIST_STATUS1); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_3D_FREE_LIST_STATUS1: ", EUR_CR_DPM_3D_FREE_LIST_STATUS1); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_TA_ALLOC_FREE_LIST_STATUS2: ", EUR_CR_DPM_TA_ALLOC_FREE_LIST_STATUS2); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_3D_FREE_LIST_STATUS2: ", EUR_CR_DPM_3D_FREE_LIST_STATUS2); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_ABORT_STATUS_MTILE: ", EUR_CR_DPM_ABORT_STATUS_MTILE); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_PAGE_STATUS: ", EUR_CR_DPM_PAGE_STATUS); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_PAGE: ", EUR_CR_DPM_PAGE); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_GLOBAL_PAGE_STATUS: ", EUR_CR_DPM_GLOBAL_PAGE_STATUS); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_VDM_CONTEXT_LOAD_STATUS: ", EUR_CR_VDM_CONTEXT_LOAD_STATUS); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_VDM_CONTEXT_STORE_STATUS: ", EUR_CR_VDM_CONTEXT_STORE_STATUS); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_VDM_TASK_KICK_STATUS: ", EUR_CR_VDM_TASK_KICK_STATUS); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_VDM_CONTEXT_STORE_STATE0: ", EUR_CR_VDM_CONTEXT_STORE_STATE0); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_VDM_CONTEXT_STORE_STATE1: ", EUR_CR_VDM_CONTEXT_STORE_STATE1); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_REQUESTING: ", EUR_CR_DPM_REQUESTING); - SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_DPM_REQUESTING: ", EUR_CR_DPM_REQUESTING); - -#endif } #if !defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS) && !defined(FIX_HW_BRN_31620) @@ -1387,67 +1392,149 @@ IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo, IMG_UINT32 ui32Bank0; IMG_UINT32 ui32DirListIndex; IMG_UINT32 ui32PDDevPAddr; + IMG_UINT32 ui32RegVal; + +#if defined(SGX_FEATURE_MP) + ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_INT_STAT); +#if defined(EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK) + if( ui32RegVal & EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK) +#else + if( ui32RegVal & EUR_CR_BIF_INT_STAT_PF_N_RW_MASK) +#endif + { + ui32FaultAddress = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_FAULT); + if(ui32FaultAddress) + { + ui32Bank0 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0); + + /* Check the EDM's's memory context */ + ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_EDM_MASK) >> EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT; + ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, + GetDirListBaseReg(ui32DirListIndex)); + PVR_LOG(("Checking EDM memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); + MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + + /* Check the TA's memory context */ + ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_TA_MASK) >> EUR_CR_BIF_BANK0_INDEX_TA_SHIFT; + ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, + GetDirListBaseReg(ui32DirListIndex)); + PVR_LOG(("Checking TA memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); + MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + + /* Check the 3D's memory context */ + ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_3D_MASK) >> EUR_CR_BIF_BANK0_INDEX_3D_SHIFT; + ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, + GetDirListBaseReg(ui32DirListIndex)); + PVR_LOG(("Checking 3D memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); + MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + + #if defined(EUR_CR_BIF_BANK0_INDEX_2D_MASK) + /* Check the 2D's memory context */ + ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_2D_MASK) >> EUR_CR_BIF_BANK0_INDEX_2D_SHIFT; + ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, + GetDirListBaseReg(ui32DirListIndex)); + PVR_LOG(("Checking 2D memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); + MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + #endif + + #if defined(EUR_CR_BIF_BANK0_INDEX_PTLA_MASK) + /* Check the 2D's memory context */ + ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_PTLA_MASK) >> EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT; + ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, + GetDirListBaseReg(ui32DirListIndex)); + PVR_LOG(("Checking PTLA memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); + MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + #endif - ui32FaultAddress = OSReadHWReg(psDevInfo->pvRegsBaseKM, - EUR_CR_BIF_FAULT); - ui32FaultAddress = ui32FaultAddress & EUR_CR_BIF_FAULT_ADDR_MASK; - - ui32Bank0 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0); - - /* Check the EDM's's memory context */ - ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_EDM_MASK) >> EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT; - ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, - GetDirListBaseReg(ui32DirListIndex)); - PVR_LOG(("Checking EDM memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); - MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); - - /* Check the TA's memory context */ - ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_TA_MASK) >> EUR_CR_BIF_BANK0_INDEX_TA_SHIFT; - ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, - GetDirListBaseReg(ui32DirListIndex)); - PVR_LOG(("Checking TA memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); - MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); - - /* Check the 3D's memory context */ - ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_3D_MASK) >> EUR_CR_BIF_BANK0_INDEX_3D_SHIFT; - ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, - GetDirListBaseReg(ui32DirListIndex)); - PVR_LOG(("Checking 3D memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); - MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); - - #if defined(EUR_CR_BIF_BANK0_INDEX_2D_MASK) - /* Check the 2D's memory context */ - ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_2D_MASK) >> EUR_CR_BIF_BANK0_INDEX_2D_SHIFT; - ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, - GetDirListBaseReg(ui32DirListIndex)); - PVR_LOG(("Checking 2D memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); - MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); - #endif - - #if defined(EUR_CR_BIF_BANK0_INDEX_PTLA_MASK) - /* Check the 2D's memory context */ - ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_PTLA_MASK) >> EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT; - ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, - GetDirListBaseReg(ui32DirListIndex)); - PVR_LOG(("Checking PTLA memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); - MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); - #endif - - #if defined(EUR_CR_BIF_BANK0_INDEX_HOST_MASK) - /* Check the Host's memory context */ - ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_HOST_MASK) >> EUR_CR_BIF_BANK0_INDEX_HOST_SHIFT; - ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, - GetDirListBaseReg(ui32DirListIndex)); - PVR_LOG(("Checking Host memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); - MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + #if defined(EUR_CR_BIF_BANK0_INDEX_HOST_MASK) + /* Check the Host's memory context */ + ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_HOST_MASK) >> EUR_CR_BIF_BANK0_INDEX_HOST_SHIFT; + ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, + GetDirListBaseReg(ui32DirListIndex)); + PVR_LOG(("Checking Host memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); + MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + + #endif + } + } +#endif + for (ui32CoreNum = 0; ui32CoreNum < SGX_FEATURE_MP_CORE_COUNT_3D; ui32CoreNum++) + { + + ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BIF_INT_STAT, ui32CoreNum)); + #if defined(EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK) + if( ui32RegVal & EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK) + #else + if( ui32RegVal & EUR_CR_BIF_INT_STAT_PF_N_RW_MASK) #endif + { + ui32FaultAddress = OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BIF_FAULT, ui32CoreNum)); + ui32FaultAddress &= EUR_CR_BIF_FAULT_ADDR_MASK; + if(ui32FaultAddress) + { + ui32Bank0 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0); + + /* Check the EDM's's memory context */ + ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_EDM_MASK) >> EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT; + ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, + GetDirListBaseReg(ui32DirListIndex)); + PVR_LOG(("Checking EDM memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); + MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + + /* Check the TA's memory context */ + ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_TA_MASK) >> EUR_CR_BIF_BANK0_INDEX_TA_SHIFT; + ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, + GetDirListBaseReg(ui32DirListIndex)); + PVR_LOG(("Checking TA memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); + MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + + /* Check the 3D's memory context */ + ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_3D_MASK) >> EUR_CR_BIF_BANK0_INDEX_3D_SHIFT; + ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, + GetDirListBaseReg(ui32DirListIndex)); + PVR_LOG(("Checking 3D memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); + MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + + #if defined(EUR_CR_BIF_BANK0_INDEX_2D_MASK) + /* Check the 2D's memory context */ + ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_2D_MASK) >> EUR_CR_BIF_BANK0_INDEX_2D_SHIFT; + ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, + GetDirListBaseReg(ui32DirListIndex)); + PVR_LOG(("Checking 2D memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); + MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + #endif + + #if defined(EUR_CR_BIF_BANK0_INDEX_PTLA_MASK) + /* Check the 2D's memory context */ + ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_PTLA_MASK) >> EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT; + ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, + GetDirListBaseReg(ui32DirListIndex)); + PVR_LOG(("Checking PTLA memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); + MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + #endif + + #if defined(EUR_CR_BIF_BANK0_INDEX_HOST_MASK) + /* Check the Host's memory context */ + ui32DirListIndex = (ui32Bank0 & EUR_CR_BIF_BANK0_INDEX_HOST_MASK) >> EUR_CR_BIF_BANK0_INDEX_HOST_SHIFT; + ui32PDDevPAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, + GetDirListBaseReg(ui32DirListIndex)); + PVR_LOG(("Checking Host memory context (index = %d, PD = 0x%08x)", ui32DirListIndex, ui32PDDevPAddr)); + MMU_CheckFaultAddr(psDevInfo, ui32PDDevPAddr, ui32FaultAddress); + + #endif + } + } + } } #endif } + +#if defined(SUPPORT_PVRSRV_DEVICE_CLASS) /* Dump out the outstanding queue items. */ QueueDumpDebugInfo(); +#endif { /* @@ -1456,7 +1543,25 @@ IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo, SGXMKIF_HOST_CTL *psSGXHostCtl = psDevInfo->psSGXHostCtl; IMG_UINT32 *pui32HostCtlBuffer = (IMG_UINT32 *)psSGXHostCtl; IMG_UINT32 ui32LoopCounter; - + + /* Report which defines are enabled that affect the HostCTL structure being dumped-out here */ + { + IMG_UINT32 ui32CtlFlags = 0; + #if defined(PVRSRV_USSE_EDM_BREAKPOINTS) + ui32CtlFlags = ui32CtlFlags | 0x0001; + #endif + #if defined(FIX_HW_BRN_28889) + ui32CtlFlags = ui32CtlFlags | 0x0002; + #endif + #if defined(SUPPORT_HW_RECOVERY) + ui32CtlFlags = ui32CtlFlags | 0x0004; + #endif + #if defined(SGX_FEATURE_EXTENDED_PERF_COUNTERS) + ui32CtlFlags = ui32CtlFlags | 0x0008; + #endif + PVR_LOG((" Host Ctl flags= %08x", ui32CtlFlags)); + } + if (psSGXHostCtl->ui32AssertFail != 0) { PVR_LOG(("SGX Microkernel assert fail: 0x%08X", psSGXHostCtl->ui32AssertFail)); @@ -1469,7 +1574,8 @@ IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo, ui32LoopCounter < sizeof(*psDevInfo->psSGXHostCtl) / sizeof(*pui32HostCtlBuffer); ui32LoopCounter += 4) { - PVR_LOG(("\t(HC-%X) 0x%08X 0x%08X 0x%08X 0x%08X", ui32LoopCounter * sizeof(*pui32HostCtlBuffer), + PVR_LOG(("\t(HC-%" SIZE_T_FMT_LEN "X) 0x%08X 0x%08X 0x%08X 0x%08X", + ui32LoopCounter * sizeof(*pui32HostCtlBuffer), pui32HostCtlBuffer[ui32LoopCounter + 0], pui32HostCtlBuffer[ui32LoopCounter + 1], pui32HostCtlBuffer[ui32LoopCounter + 2], pui32HostCtlBuffer[ui32LoopCounter + 3])); } @@ -1488,7 +1594,8 @@ IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo, ui32LoopCounter < psDevInfo->psKernelSGXTA3DCtlMemInfo->uAllocSize / sizeof(*pui32TA3DCtlBuffer); ui32LoopCounter += 4) { - PVR_LOG(("\t(T3C-%X) 0x%08X 0x%08X 0x%08X 0x%08X", ui32LoopCounter * sizeof(*pui32TA3DCtlBuffer), + PVR_LOG(("\t(T3C-%" SIZE_T_FMT_LEN "X) 0x%08X 0x%08X 0x%08X 0x%08X", + ui32LoopCounter * sizeof(*pui32TA3DCtlBuffer), pui32TA3DCtlBuffer[ui32LoopCounter + 0], pui32TA3DCtlBuffer[ui32LoopCounter + 1], pui32TA3DCtlBuffer[ui32LoopCounter + 2], pui32TA3DCtlBuffer[ui32LoopCounter + 3])); } @@ -1561,6 +1668,24 @@ IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo, PVRSRVDumpTimeTraceBuffers(); #endif + #if defined (SUPPORT_FORCE_SYNC_DUMP) + PVRSRVDumpSyncs(IMG_FALSE); + #else + PVRSRVDumpSyncs(IMG_TRUE); + #endif + + +#if defined (MEM_TRACK_INFO_DEBUG) + { + IMG_UINT32 ui32FaultAddress = OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BIF_FAULT, 0)); + PVRSRVPrintMemTrackInfo(ui32FaultAddress); + } +#endif + + +#if defined(PVRSRV_DEBUG_CCB_MAX) + PVRSRVDebugPrintfDumpCCB(); +#endif } @@ -1600,9 +1725,6 @@ IMG_VOID HWRecoveryResetSGX (PVRSRV_DEVICE_NODE *psDeviceNode, PVR_UNREFERENCED_PARAMETER(ui32Component); - /* Debug dumps associated with HWR can be long. Delay system suspend */ - SysLockSystemSuspend(); - /* Ensure that hardware recovery is serialised with any power transitions. */ @@ -1620,7 +1742,7 @@ IMG_VOID HWRecoveryResetSGX (PVRSRV_DEVICE_NODE *psDeviceNode, psSGXHostCtl->ui32InterruptClearFlags |= PVRSRV_USSE_EDM_INTERRUPT_HWR; PVR_LOG(("HWRecoveryResetSGX: SGX Hardware Recovery triggered")); - + #if defined(SUPPORT_HWRECOVERY_TRACE_LIMIT) /* * The following defines are system specific and should be defined in @@ -1658,13 +1780,13 @@ IMG_VOID HWRecoveryResetSGX (PVRSRV_DEVICE_NODE *psDeviceNode, PVRSRVPowerUnlock(ui32CallerID); - SysUnlockSystemSuspend(); - /* Send a dummy kick so that we start processing again */ SGXScheduleProcessQueuesKM(psDeviceNode); +#if defined(SUPPORT_PVRSRV_DEVICE_CLASS) /* Flush any old commands from the queues. */ PVRSRVProcessQueues(IMG_TRUE); +#endif } #endif /* #if defined(SYS_USING_INTERRUPTS) || defined(SUPPORT_HW_RECOVERY) */ @@ -1823,7 +1945,7 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData) /* Real Hardware */ { - IMG_UINT32 ui32EventStatus = 0, ui32EventEnable = 0; + IMG_UINT32 ui32EventStatus, ui32EventEnable; IMG_UINT32 ui32EventClear = 0; #if defined(SGX_FEATURE_DATA_BREAKPOINTS) IMG_UINT32 ui32EventStatus2, ui32EventEnable2; @@ -1842,19 +1964,15 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData) psDeviceNode = (PVRSRV_DEVICE_NODE *)pvData; psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice; - if(!powering_down) { - ui32EventStatus = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS); - ui32EventEnable = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE); - } + ui32EventStatus = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS); + ui32EventEnable = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE); /* test only the unmasked bits */ ui32EventStatus &= ui32EventEnable; #if defined(SGX_FEATURE_DATA_BREAKPOINTS) - if(!powering_down) { - ui32EventStatus2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2); - ui32EventEnable2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE2); - } + ui32EventStatus2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2); + ui32EventEnable2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE2); /* test only the unmasked bits */ ui32EventStatus2 &= ui32EventEnable2; @@ -1888,17 +2006,86 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData) /* Clear master interrupt bit */ ui32EventClear |= EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK; - if(!powering_down) { - /* clear the events */ - OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32EventClear); - OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32EventClear2); - } + /* clear the events */ + OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32EventClear); + OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32EventClear2); + + /* + Sample the current count from the uKernel _after_ we've cleared the + interrupt. + */ + g_ui32HostIRQCountSample = psDevInfo->psSGXHostCtl->ui32InterruptCount; } } return bInterruptProcessed; } +/* + SGX Systrace Handler +*/ +#if defined(SUPPORT_PVRSRV_ANDROID_SYSTRACE) +static IMG_VOID SGXSystraceHandler(PVRSRV_DEVICE_NODE *psDeviceNode) +{ + PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice; + IMG_UINT32 ui32SgxClockSpeed, ui32DataCount, ui32HostTimestamp; + + /* NOTE: Not thread safe. MISR should only run in one thread */ + static PVRSRV_SGX_HWPERF_CB_ENTRY asSGXHWPerf[8]; + + if(SystraceIsCapturingHWData() && psDevInfo->bSystraceInitialised) + { + SGXReadHWPerfCBKM((IMG_HANDLE) psDeviceNode, + 8, + asSGXHWPerf, + (IMG_UINT32 *)&ui32DataCount, + (IMG_UINT32 *)&ui32SgxClockSpeed, + (IMG_UINT32 *)&ui32HostTimestamp); + + SystraceHWPerfPackets(psDevInfo, asSGXHWPerf, ui32DataCount, ui32SgxClockSpeed); + } + else if(SystraceIsCapturingHWData() && !psDevInfo->bSystraceInitialised) + { + SGX_MISC_INFO sSGXMiscInfo; + + if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(PVRSRV_SYSTRACE_DATA), + (IMG_VOID **)&psDevInfo->psSystraceData, 0, + "Systrace data storage") != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR, "SGXSystraceHandler: Failed to allocate systrace data")); + return; + } + + OSMemSet(psDevInfo->psSystraceData, 0, sizeof(PVRSRV_SYSTRACE_DATA)); + + /* Prepare the SGXMiscInfo request in order to stop recording data*/ + sSGXMiscInfo.eRequest = SGX_MISC_INFO_REQUEST_SET_HWPERF_STATUS; + sSGXMiscInfo.uData.sSetHWPerfStatus.ui32NewHWPerfStatus = PVRSRV_SGX_HWPERF_STATUS_GRAPHICS_ON | PVRSRV_SGX_HWPERF_STATUS_PERIODIC_ON; + + /* Call into SGX DDK KM Services*/ + SGXGetMiscInfoKM(psDevInfo, &sSGXMiscInfo, psDeviceNode, NULL); + + psDevInfo->bSystraceInitialised = IMG_TRUE; + + /* Initialize the first context to be 1 (0 is idle)*/ + psDevInfo->psSystraceData->ui32CurrentCtxID = 1; + } + else if(psDevInfo->bSystraceInitialised) + { + SGX_MISC_INFO sSGXMiscInfo; + + /* Prepare the SGXMiscInfo request in order to stop recording data*/ + sSGXMiscInfo.eRequest = SGX_MISC_INFO_REQUEST_SET_HWPERF_STATUS; + sSGXMiscInfo.uData.sSetHWPerfStatus.ui32NewHWPerfStatus = 0; + + /* Call into SGX DDK KM Services*/ + SGXGetMiscInfoKM(psDevInfo, &sSGXMiscInfo, psDeviceNode, NULL); + + OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(PVRSRV_SYSTRACE_DATA), psDevInfo->psSystraceData, NULL); + psDevInfo->bSystraceInitialised = IMG_FALSE; + } +} +#endif /* SGX MISR Handler @@ -1923,6 +2110,11 @@ static IMG_VOID SGX_MISRHandler (IMG_VOID *pvData) #endif SGXTestActivePowerEvent(psDeviceNode, ISR_ID); + +#if defined(SUPPORT_PVRSRV_ANDROID_SYSTRACE) + SGXSystraceHandler(psDeviceNode); +#endif + } #endif /* #if defined (SYS_USING_INTERRUPTS) */ @@ -2139,23 +2331,6 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode) psDeviceMemoryHeap++;/* advance to the next heap */ #endif -#if defined(SUPPORT_ION) - /************* Ion Heap ***************/ - psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_ION_HEAP_ID); - psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_ION_HEAP_BASE; - psDeviceMemoryHeap->ui32HeapSize = SGX_ION_HEAP_SIZE; - psDeviceMemoryHeap->ui32Attribs = PVRSRV_HAP_WRITECOMBINE - | PVRSRV_HAP_SINGLE_PROCESS; - psDeviceMemoryHeap->pszName = "Ion"; - psDeviceMemoryHeap->pszBSName = "Ion BS"; - psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT; - /* specify the ion heap ID for this device */ - psDevMemoryInfo->ui32IonHeapID = SGX_ION_HEAP_ID; - /* set the default (4k). System can override these as required */ - psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE; - psDeviceMemoryHeap++;/* advance to the next heap */ -#endif - /************* TA data ***************/ psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_TADATA_HEAP_ID); psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_TADATA_HEAP_BASE; @@ -2498,8 +2673,7 @@ PVRSRV_ERROR SGXDevInitCompatCheck(PVRSRV_DEVICE_NODE *psDeviceNode) /* * 1. Check kernel-side and client-side build options - * 2. Ensure ukernel DDK version and driver DDK version are compatible - * 3. Check ukernel build options against kernel-side build options + * 2. Check ukernel build options against kernel-side build options */ /* @@ -2540,32 +2714,12 @@ PVRSRV_ERROR SGXDevInitCompatCheck(PVRSRV_DEVICE_NODE *psDeviceNode) psSGXMiscInfoInt->ui32MiscInfoFlags |= PVRSRV_USSE_MISCINFO_GET_STRUCT_SIZES; eError = SGXGetMiscInfoUkernel(psDevInfo, psDeviceNode, IMG_NULL); - /* - * Validate DDK version - */ if(eError != PVRSRV_OK) { - PVR_LOG(("(FAIL) SGXInit: Unable to validate device DDK version")); + PVR_LOG(("(FAIL) SGXInit: Unable to validate hardware core revision")); goto chk_exit; } psSGXFeatures = &((PVRSRV_SGX_MISCINFO_INFO*)(psMemInfo->pvLinAddrKM))->sSGXFeatures; - if( (psSGXFeatures->ui32DDKVersion != - ((PVRVERSION_MAJ << 16) | - (PVRVERSION_MIN << 8) | - PVRVERSION_BRANCH) ) || - (psSGXFeatures->ui32DDKBuild != PVRVERSION_BUILD) ) - { - PVR_LOG(("(FAIL) SGXInit: Incompatible driver DDK revision (%d)/device DDK revision (%d).", - PVRVERSION_BUILD, psSGXFeatures->ui32DDKBuild)); - eError = PVRSRV_ERROR_DDK_VERSION_MISMATCH; - goto chk_exit; - } - else - { - PVR_DPF((PVR_DBG_MESSAGE, "SGXInit: driver DDK (%d) and device DDK (%d) match. [ OK ]", - PVRVERSION_BUILD, psSGXFeatures->ui32DDKBuild)); - } - /* * Check hardware core revision is compatible with the one in software */ @@ -3099,6 +3253,17 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo, return PVRSRV_OK; } + case SGX_MISC_INFO_REQUEST_CLOCKSPEED_SLCSIZE: + { + psMiscInfo->uData.sQueryClockSpeedSLCSize.ui32SGXClockSpeed = SYS_SGX_CLOCK_SPEED; +#if defined(SGX_FEATURE_SYSTEM_CACHE) && defined(SYS_SGX_SLC_SIZE) + psMiscInfo->uData.sQueryClockSpeedSLCSize.ui32SGXSLCSize = SYS_SGX_SLC_SIZE; +#else + psMiscInfo->uData.sQueryClockSpeedSLCSize.ui32SGXSLCSize = 0; +#endif /* defined(SGX_FEATURE_SYSTEM_CACHE) && defined(SYS_SGX_SLC_SIZE) */ + return PVRSRV_OK; + } + case SGX_MISC_INFO_REQUEST_ACTIVEPOWER: { psMiscInfo->uData.sActivePower.ui32NumActivePowerEvents = psDevInfo->psSGXHostCtl->ui32NumActivePowerEvents; @@ -3167,24 +3332,27 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo, psSGXFeatures->ui32DDKVersion = (PVRVERSION_MAJ << 16) | - (PVRVERSION_MIN << 8) | - PVRVERSION_BRANCH; + (PVRVERSION_MIN << 8); psSGXFeatures->ui32DDKBuild = PVRVERSION_BUILD; /* Also report the kernel module build options -- used in SGXConnectionCheck() */ psSGXFeatures->ui32BuildOptions = (SGX_BUILD_OPTIONS); -#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) - /* Report the EDM status buffer location in memory */ - psSGXFeatures->sDevVAEDMStatusBuffer = psDevInfo->psKernelEDMStatusBufferMemInfo->sDevVAddr; - psSGXFeatures->pvEDMStatusBuffer = psDevInfo->psKernelEDMStatusBufferMemInfo->pvLinAddrKM; -#endif - /* Copy SGX features into misc info struct, to return to client */ psMiscInfo->uData.sSGXFeatures = *psSGXFeatures; return PVRSRV_OK; } +#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) + case SGX_MISC_INFO_REQUEST_EDM_STATUS_BUFFER_INFO: + { + /* Report the EDM status buffer location in memory */ + psMiscInfo->uData.sEDMStatusBufferInfo.sDevVAEDMStatusBuffer = psDevInfo->psKernelEDMStatusBufferMemInfo->sDevVAddr; + psMiscInfo->uData.sEDMStatusBufferInfo.pvEDMStatusBuffer = psDevInfo->psKernelEDMStatusBufferMemInfo->pvLinAddrKM; + return PVRSRV_OK; + } +#endif + #if defined(SUPPORT_SGX_EDM_MEMORY_DEBUG) case SGX_MISC_INFO_REQUEST_MEMREAD: case SGX_MISC_INFO_REQUEST_MEMCOPY: @@ -3350,6 +3518,14 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo, case SGX_MISC_INFO_DUMP_DEBUG_INFO_FORCE_REGS: { + if(!OSProcHasPrivSrvInit()) + { + PVR_DPF((PVR_DBG_ERROR, "Insufficient privileges to dump SGX " + "debug info with registers")); + + return PVRSRV_ERROR_INVALID_MISCINFO; + } + PVR_LOG(("User requested SGX debug info")); /* Dump SGX debug data to the kernel log. */ diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxkick.c b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxkick.c index 584f53899b1..a03f51a702c 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxkick.c +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxkick.c @@ -53,6 +53,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "sgxutils.h" #include "ttrace.h" +#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) +#include "pvr_sync.h" +#endif + +#if defined(SUPPORT_PVRSRV_ANDROID_SYSTRACE) +#include "systrace.h" +#endif + /*! ****************************************************************************** @@ -68,11 +76,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ******************************************************************************/ IMG_EXPORT -#if defined (SUPPORT_SID_INTERFACE) -PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK_KM *psCCBKick) -#else PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) -#endif { PVRSRV_ERROR eError; PVRSRV_KERNEL_SYNC_INFO *psSyncInfo; @@ -80,6 +84,13 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) SGXMKIF_CMDTA_SHARED *psTACmd; IMG_UINT32 i; IMG_HANDLE hDevMemContext = IMG_NULL; +#if defined(SUPPORT_PVRSRV_ANDROID_SYSTRACE) + PVRSRV_DEVICE_NODE *psDeviceNode; + PVRSRV_SGXDEV_INFO *psDevInfo; + + psDeviceNode = (PVRSRV_DEVICE_NODE *)hDevHandle; + psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice; +#endif #if defined(FIX_HW_BRN_31620) hDevMemContext = psCCBKick->hDevMemContext; #endif @@ -97,6 +108,11 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) PVR_TTRACE(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_CMD_START, KICK_TOKEN_DOKICK); + PVR_TTRACE_UI32(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_FRAMENUM, KICK_TOKEN_FRAMENUM, psCCBKick->ui32FrameNum); + PVR_TTRACE_UI32(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_NONE, KICK_TOKEN_RENDERCONTEXT, psCCBKick->sCommand.ui32Data[1]); + PVR_TTRACE_DEV_VIRTADDR(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_DEVVADDR, KICK_TOKEN_HWRTDATASET, psCCBKick->sHWRTDataSetDevAddr); + PVR_TTRACE_DEV_VIRTADDR(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_DEVVADDR, KICK_TOKEN_HWRTDATA, psCCBKick->sHWRTDataDevAddr); + #if defined(TTRACE) if (psCCBKick->bFirstKickOrResume) { @@ -129,7 +145,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) if (psCCBKick->bTADependency) { - psSyncInfo->psSyncData->ui32WriteOpsPending++; + SyncTakeWriteOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); } } @@ -143,7 +159,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) psTACmd->sTATQSyncReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; psTACmd->sTATQSyncWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; - psTACmd->ui32TATQSyncReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending++; + psTACmd->ui32TATQSyncReadOpsPendingVal = SyncTakeReadOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); psTACmd->ui32TATQSyncWriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending; } @@ -157,7 +173,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) psTACmd->s3DTQSyncReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; psTACmd->s3DTQSyncWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; - psTACmd->ui323DTQSyncReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending++; + psTACmd->ui323DTQSyncReadOpsPendingVal = SyncTakeReadOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); psTACmd->ui323DTQSyncWriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending; } @@ -205,7 +221,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) psTACmd->asTASrcSyncs[i].sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; /* Get ui32ReadOpsPending snapshot and copy into the CCB - before incrementing. */ - psTACmd->asTASrcSyncs[i].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending++; + psTACmd->asTASrcSyncs[i].ui32ReadOpsPendingVal = SyncTakeReadOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); /* Copy ui32WriteOpsPending snapshot into the CCB. */ psTACmd->asTASrcSyncs[i].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending; } @@ -221,7 +237,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) /* Get ui32ReadOpsPending snapshot and copy into the CCB */ psTACmd->asTADstSyncs[i].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; /* Copy ui32WriteOpsPending snapshot into the CCB - before incrementing */ - psTACmd->asTADstSyncs[i].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++; + psTACmd->asTADstSyncs[i].ui32WriteOpsPendingVal = SyncTakeWriteOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); } psTACmd->ui32Num3DSrcSyncs = psCCBKick->ui32Num3DSrcSyncs; @@ -233,13 +249,47 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) psTACmd->as3DSrcSyncs[i].sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; /* Get ui32ReadOpsPending snapshot and copy into the CCB - before incrementing. */ - psTACmd->as3DSrcSyncs[i].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending++; + psTACmd->as3DSrcSyncs[i].ui32ReadOpsPendingVal = SyncTakeReadOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); /* Copy ui32WriteOpsPending snapshot into the CCB. */ psTACmd->as3DSrcSyncs[i].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending; } #else /* SUPPORT_SGX_GENERALISED_SYNCOBJECTS */ /* texture dependencies */ - psTACmd->ui32NumSrcSyncs = psCCBKick->ui32NumSrcSyncs; +#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) + eError = PVRSyncPatchCCBKickSyncInfos(psCCBKick->ahSrcKernelSyncInfo, + psTACmd->asSrcSyncs, + &psCCBKick->ui32NumSrcSyncs); + if(eError != PVRSRV_OK) + { + /* We didn't kick yet, or perform PDUMP processing, so we should + * be able to trivially roll back any changes made to the sync + * data. If we don't do this, we'll wedge services cleanup. + */ + + if (psCCBKick->h3DSyncInfo != IMG_NULL) + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->h3DSyncInfo; + psSyncInfo->psSyncData->ui32ReadOpsPending--; + } + + if (psCCBKick->hTASyncInfo != IMG_NULL) + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTASyncInfo; + psSyncInfo->psSyncData->ui32ReadOpsPending--; + } + + if (psCCBKick->hTA3DSyncInfo && psCCBKick->bTADependency) + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTA3DSyncInfo; + psSyncInfo->psSyncData->ui32WriteOpsPending--; + } + + PVR_DPF((PVR_DBG_ERROR, "SGXDoKickKM: PVRSyncPatchCCBKickSyncInfos failed.")); + PVR_TTRACE(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_FUNCTION_EXIT, + KICK_TOKEN_DOKICK); + return eError; + } +#else /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */ for (i=0; i<psCCBKick->ui32NumSrcSyncs; i++) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *) psCCBKick->ahSrcKernelSyncInfo[i]; @@ -251,11 +301,13 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) psTACmd->asSrcSyncs[i].sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; /* Get ui32ReadOpsPending snapshot and copy into the CCB - before incrementing. */ - psTACmd->asSrcSyncs[i].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending++; + psTACmd->asSrcSyncs[i].ui32ReadOpsPendingVal = SyncTakeReadOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); /* Copy ui32WriteOpsPending snapshot into the CCB. */ psTACmd->asSrcSyncs[i].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending; } -#endif/* SUPPORT_SGX_GENERALISED_SYNCOBJECTS */ +#endif /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */ + psTACmd->ui32NumSrcSyncs = psCCBKick->ui32NumSrcSyncs; +#endif /* defined(SUPPORT_SGX_GENERALISED_SYNCOBJECTS) */ if (psCCBKick->bFirstKickOrResume && psCCBKick->ui32NumDstSyncObjects > 0) { @@ -297,7 +349,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) psHWDeviceSyncList->asSyncData[i].sReadOps2CompleteDevVAddr = psSyncInfo->sReadOps2CompleteDevVAddr; psHWDeviceSyncList->asSyncData[i].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; - psHWDeviceSyncList->asSyncData[i].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++; + psHWDeviceSyncList->asSyncData[i].ui32WriteOpsPendingVal = SyncTakeWriteOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); psHWDeviceSyncList->asSyncData[i].ui32ReadOps2PendingVal = psSyncInfo->psSyncData->ui32ReadOps2Pending; #if defined(PDUMP) @@ -322,37 +374,17 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) 0, MAKEUNIQUETAG(psHWDstSyncListMemInfo)); - if ((psSyncInfo->psSyncData->ui32LastOpDumpVal == 0) && - (psSyncInfo->psSyncData->ui32LastReadOpDumpVal == 0)) - { - /* - * Init the ROpsComplete value to 0. - */ - PDUMPCOMMENT("Init RT ROpsComplete\r\n"); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, - psSyncInfo->psSyncDataMemInfoKM, - offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete), - sizeof(psSyncInfo->psSyncData->ui32ReadOpsComplete), - 0, - MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM)); - /* - * Init the WOpsComplete value to 0. - */ - PDUMPCOMMENT("Init RT WOpsComplete\r\n"); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, - psSyncInfo->psSyncDataMemInfoKM, - offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete), - sizeof(psSyncInfo->psSyncData->ui32WriteOpsComplete), - 0, - MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM)); - } - psSyncInfo->psSyncData->ui32LastOpDumpVal++; ui32ModifiedValue = psSyncInfo->psSyncData->ui32LastOpDumpVal - 1; PDUMPCOMMENT("Modify RT %d WOpPendingVal in HWDevSyncList\r\n", i); +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENT("TA Dst: PDump sync sample: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + ui32ModifiedValue); +#endif PDUMPMEM(&ui32ModifiedValue, psHWDstSyncListMemInfo, ui32WOpsOffset, @@ -380,6 +412,11 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psHWDstSyncListMemInfo)); +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_PERSISTENT, "TA Dst: PDump sync update: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif } #endif /* defined(PDUMP) */ } @@ -420,31 +457,6 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) IMG_UINT32 ui32ModifiedValue; psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *) psCCBKick->ahTASrcKernelSyncInfo[i]; - if ((psSyncInfo->psSyncData->ui32LastOpDumpVal == 0) && - (psSyncInfo->psSyncData->ui32LastReadOpDumpVal == 0)) - { - /* - * Init the ROpsComplete value to 0. - */ - PDUMPCOMMENT("Init RT TA-SRC ROpsComplete\r\n", i); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, - psSyncInfo->psSyncDataMemInfoKM, - offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete), - sizeof(psSyncInfo->psSyncData->ui32ReadOpsComplete), - 0, - MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM)); - /* - * Init the WOpsComplete value to 0. - */ - PDUMPCOMMENT("Init RT TA-SRC WOpsComplete\r\n"); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, - psSyncInfo->psSyncDataMemInfoKM, - offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete), - sizeof(psSyncInfo->psSyncData->ui32WriteOpsComplete), - 0, - MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM)); - } - psSyncInfo->psSyncData->ui32LastReadOpDumpVal++; ui32ModifiedValue = psSyncInfo->psSyncData->ui32LastReadOpDumpVal - 1; @@ -475,37 +487,18 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) IMG_UINT32 ui32ModifiedValue; psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *) psCCBKick->ahTADstKernelSyncInfo[i]; - if ((psSyncInfo->psSyncData->ui32LastOpDumpVal == 0) && - (psSyncInfo->psSyncData->ui32LastReadOpDumpVal == 0)) - { - /* - * Init the ROpsComplete value to 0. - */ - PDUMPCOMMENT("Init RT TA-DST ROpsComplete\r\n", i); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, - psSyncInfo->psSyncDataMemInfoKM, - offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete), - sizeof(psSyncInfo->psSyncData->ui32ReadOpsComplete), - 0, - MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM)); - /* - * Init the WOpsComplete value to 0. - */ - PDUMPCOMMENT("Init RT TA-DST WOpsComplete\r\n"); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, - psSyncInfo->psSyncDataMemInfoKM, - offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete), - sizeof(psSyncInfo->psSyncData->ui32WriteOpsComplete), - 0, - MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM)); - } - psSyncInfo->psSyncData->ui32LastOpDumpVal++; ui32ModifiedValue = psSyncInfo->psSyncData->ui32LastOpDumpVal - 1; PDUMPCOMMENT("Modify TA DstSync %d WOpPendingVal\r\n", i); +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENT("TA TADst: PDump sync sample: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr + ui32ModifiedValue; +#endif + PDUMPMEM(&ui32ModifiedValue, psCCBMemInfo, psCCBKick->ui32CCBDumpWOff + offsetof(SGXMKIF_CMDTA_SHARED, asTADstSyncs) + @@ -523,6 +516,12 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psCCBMemInfo)); + +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_PERSISTENT, "TA TADst: PDump sync update: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif } for (i=0; i<psCCBKick->ui32Num3DSrcSyncs; i++) @@ -530,31 +529,6 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) IMG_UINT32 ui32ModifiedValue; psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *) psCCBKick->ah3DSrcKernelSyncInfo[i]; - if ((psSyncInfo->psSyncData->ui32LastOpDumpVal == 0) && - (psSyncInfo->psSyncData->ui32LastReadOpDumpVal == 0)) - { - /* - * Init the ROpsComplete value to 0. - */ - PDUMPCOMMENT("Init RT 3D-SRC ROpsComplete\r\n", i); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, - psSyncInfo->psSyncDataMemInfoKM, - offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete), - sizeof(psSyncInfo->psSyncData->ui32ReadOpsComplete), - 0, - MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM)); - /* - * Init the WOpsComplete value to 0. - */ - PDUMPCOMMENT("Init RT 3D-SRC WOpsComplete\r\n"); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, - psSyncInfo->psSyncDataMemInfoKM, - offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete), - sizeof(psSyncInfo->psSyncData->ui32WriteOpsComplete), - 0, - MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM)); - } - psSyncInfo->psSyncData->ui32LastReadOpDumpVal++; ui32ModifiedValue = psSyncInfo->psSyncData->ui32LastReadOpDumpVal - 1; @@ -585,41 +559,6 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) IMG_UINT32 ui32ModifiedValue; psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *) psCCBKick->ahSrcKernelSyncInfo[i]; - if ((psSyncInfo->psSyncData->ui32LastOpDumpVal == 0) && - (psSyncInfo->psSyncData->ui32LastReadOpDumpVal == 0)) - { - /* - * Init the ROpsComplete value to 0. - */ - PDUMPCOMMENT("Init RT ROpsComplete\r\n"); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, - psSyncInfo->psSyncDataMemInfoKM, - offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete), - sizeof(psSyncInfo->psSyncData->ui32ReadOpsComplete), - 0, - MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM)); - /* - * Init the WOpsComplete value to 0. - */ - PDUMPCOMMENT("Init RT WOpsComplete\r\n"); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, - psSyncInfo->psSyncDataMemInfoKM, - offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete), - sizeof(psSyncInfo->psSyncData->ui32WriteOpsComplete), - 0, - MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM)); - /* - * Init the ROps2Complete value to 0. - */ - PDUMPCOMMENT("Init RT WOpsComplete\r\n"); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, - psSyncInfo->psSyncDataMemInfoKM, - offsetof(PVRSRV_SYNC_DATA, ui32ReadOps2Complete), - sizeof(psSyncInfo->psSyncData->ui32ReadOps2Complete), - 0, - MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM)); - } - psSyncInfo->psSyncData->ui32LastReadOpDumpVal++; ui32ModifiedValue = psSyncInfo->psSyncData->ui32LastReadOpDumpVal - 1; @@ -636,6 +575,12 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) PDUMPCOMMENT("Modify SrcSync %d WOpPendingVal\r\n", i); +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENT("TA Src: PDump sync sample: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif + PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, psCCBMemInfo, psCCBKick->ui32CCBDumpWOff + offsetof(SGXMKIF_CMDTA_SHARED, asSrcSyncs) + @@ -643,6 +588,43 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psCCBMemInfo)); + +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_PERSISTENT, "TA Src: PDump sync update: uiAddr = 0x%08x, ui32LastReadOpDumpVal = 0x%08x\r\n", + psSyncInfo->sReadOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastReadOpDumpVal); +#endif + } + + if (psCCBKick->hTA3DSyncInfo != IMG_NULL) + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTA3DSyncInfo; + + PDUMPCOMMENT("Modify TA/3D dependency WOpPendingVal\r\n"); + +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENT("TA TADep: PDump sync sample: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif + + PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, + psCCBMemInfo, + psCCBKick->ui32CCBDumpWOff + offsetof(SGXMKIF_CMDTA_SHARED, sTA3DDependency.ui32WriteOpsPendingVal), + sizeof(IMG_UINT32), + 0, + MAKEUNIQUETAG(psCCBMemInfo)); + + if (psCCBKick->bTADependency) + { + psSyncInfo->psSyncData->ui32LastOpDumpVal++; + +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_PERSISTENT, "TA TADep: PDump sync update: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif + } } if (psCCBKick->hTASyncInfo != IMG_NULL) @@ -657,6 +639,22 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psCCBMemInfo)); + + PDUMPCOMMENT("Modify TA/TQ WOpPendingVal\r\n"); + +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENT("TA TATQ: PDump sync sample: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif + + PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, + psCCBMemInfo, + psCCBKick->ui32CCBDumpWOff + offsetof(SGXMKIF_CMDTA_SHARED, ui32TATQSyncWriteOpsPendingVal), + sizeof(IMG_UINT32), + 0, + MAKEUNIQUETAG(psCCBMemInfo)); + psSyncInfo->psSyncData->ui32LastReadOpDumpVal++; } @@ -672,6 +670,22 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psCCBMemInfo)); + + PDUMPCOMMENT("Modify 3D/TQ WOpPendingVal\r\n"); + +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENT("TA 3DTQ: PDump sync sample: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif + + PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, + psCCBMemInfo, + psCCBKick->ui32CCBDumpWOff + offsetof(SGXMKIF_CMDTA_SHARED, ui323DTQSyncWriteOpsPendingVal), + sizeof(IMG_UINT32), + 0, + MAKEUNIQUETAG(psCCBMemInfo)); + psSyncInfo->psSyncData->ui32LastReadOpDumpVal++; } @@ -723,6 +737,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) if (psSyncInfo) { psSyncInfo->psSyncData->ui32WriteOpsPending--; + SyncRollBackWriteOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); #if defined(PDUMP) if (PDumpIsCaptureFrameKM()) { @@ -738,22 +753,26 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *) psCCBKick->ahTASrcKernelSyncInfo[i]; psSyncInfo->psSyncData->ui32ReadOpsPending--; + SyncRollBackReadOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); } for (i=0; i<psCCBKick->ui32NumTADstSyncs; i++) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *) psCCBKick->ahTADstKernelSyncInfo[i]; psSyncInfo->psSyncData->ui32WriteOpsPending--; + SyncRollBackReadOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); } for (i=0; i<psCCBKick->ui32Num3DSrcSyncs; i++) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *) psCCBKick->ah3DSrcKernelSyncInfo[i]; psSyncInfo->psSyncData->ui32ReadOpsPending--; + SyncRollBackReadOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); } #else/* SUPPORT_SGX_GENERALISED_SYNCOBJECTS */ for (i=0; i<psCCBKick->ui32NumSrcSyncs; i++) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *) psCCBKick->ahSrcKernelSyncInfo[i]; psSyncInfo->psSyncData->ui32ReadOpsPending--; + SyncRollBackReadOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); } #endif/* SUPPORT_SGX_GENERALISED_SYNCOBJECTS */ @@ -761,18 +780,21 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTA3DSyncInfo; psSyncInfo->psSyncData->ui32ReadOpsPending--; + SyncRollBackReadOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); } if (psCCBKick->hTASyncInfo) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTASyncInfo; psSyncInfo->psSyncData->ui32ReadOpsPending--; + SyncRollBackReadOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); } if (psCCBKick->h3DSyncInfo) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->h3DSyncInfo; psSyncInfo->psSyncData->ui32ReadOpsPending--; + SyncRollBackReadOp(psSyncInfo, SYNC_OP_CLASS_KICKTA); } PVR_TTRACE(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_FUNCTION_EXIT, @@ -891,6 +913,9 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) #endif PVR_TTRACE(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_FUNCTION_EXIT, KICK_TOKEN_DOKICK); +#if defined(SUPPORT_PVRSRV_ANDROID_SYSTRACE) + SystraceTAKick(psDevInfo, psCCBKick->ui32FrameNum, psCCBKick->sHWRTDataDevAddr.uiAddr, psCCBKick->bIsFirstKick); +#endif return eError; } diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxpower.c b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxpower.c index 2acd28d4481..a4ef2761630 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxpower.c +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxpower.c @@ -48,8 +48,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "sgxutils.h" #include "pdump_km.h" -int powering_down = 0; - +extern IMG_UINT32 g_ui32HostIRQCountSample; #if defined(SUPPORT_HW_RECOVERY) static PVRSRV_ERROR SGXAddTimer(PVRSRV_DEVICE_NODE *psDeviceNode, @@ -333,8 +332,6 @@ PVRSRV_ERROR SGXPrePowerState (IMG_HANDLE hDevHandle, PDUMPCOMMENT("SGX idle request"); } - powering_down = 1; - sCommand.ui32Data[1] = ui32PowerCmd; eError = SGXScheduleCCBCommand(psDeviceNode, SGXMKIF_CMD_POWER, &sCommand, KERNEL_ID, 0, IMG_NULL, IMG_FALSE); @@ -359,7 +356,11 @@ PVRSRV_ERROR SGXPrePowerState (IMG_HANDLE hDevHandle, } #endif /* NO_HARDWARE */ - psDevInfo->bSGXIdle = IMG_TRUE; + if (psDevInfo->bSGXIdle == IMG_FALSE) + { + psDevInfo->bSGXIdle = IMG_TRUE; + SysSGXIdleEntered(); + } #if defined(PDUMP) PDUMPCOMMENT("TA/3D CCB Control - Wait for power event on uKernel."); @@ -372,6 +373,20 @@ PVRSRV_ERROR SGXPrePowerState (IMG_HANDLE hDevHandle, MAKEUNIQUETAG(psDevInfo->psKernelSGXHostCtlMemInfo)); #endif /* PDUMP */ + /* Wait for the pending ukernel to host interrupts to come back. */ + #if !defined(NO_HARDWARE) && defined(SUPPORT_LISR_MISR_SYNC) + if (PollForValueKM(&g_ui32HostIRQCountSample, + psDevInfo->psSGXHostCtl->ui32InterruptCount, + 0xffffffff, + MAX_HW_TIME_US, + MAX_HW_TIME_US/WAIT_TRY_COUNT, + IMG_FALSE) != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR,"SGXPrePowerState: Wait for pending interrupts failed.")); + SGXDumpDebugInfo(psDevInfo, IMG_FALSE); + PVR_DBG_BREAK; + } + #endif /* NO_HARDWARE && SUPPORT_LISR_MISR_SYNC*/ #if defined(SGX_FEATURE_MP) ui32CoresEnabled = ((OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_CORE) & EUR_CR_MASTER_CORE_ENABLE_MASK) >> EUR_CR_MASTER_CORE_ENABLE_SHIFT) + 1; #else @@ -479,7 +494,6 @@ PVRSRV_ERROR SGXPostPowerState (IMG_HANDLE hDevHandle, PVR_DPF((PVR_DBG_ERROR,"SGXPostPowerState: SGXInitialise failed")); return eError; } - powering_down = 0; } else { @@ -548,6 +562,18 @@ PVRSRV_ERROR SGXPreClockSpeedChange (IMG_HANDLE hDevHandle, return eError; } } + else + { + #if defined(SUPPORT_HW_RECOVERY) + PVRSRV_ERROR eError; + + eError = OSDisableTimer(psDevInfo->hTimer); + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR,"SGXStartTimer : Failed to enable host timer")); + } + #endif /* SUPPORT_HW_RECOVERY */ + } } PVR_DPF((PVR_DBG_MESSAGE,"SGXPreClockSpeedChange: SGX clock speed was %uHz", diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxreset.c b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxreset.c index dcdefae9a46..2b7aa4ce85c 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxreset.c +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxreset.c @@ -191,7 +191,7 @@ static IMG_VOID SGXResetSetupBIFContexts(PVRSRV_SGXDEV_INFO *psDevInfo, ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (SGX_BIF_DIR_LIST_INDEX_EDM - 1); #endif /* SGX_BIF_DIR_LIST_INDEX_EDM */ - ui32RegVal = psDevInfo->sKernelPDDevPAddr.uiAddr >> SGX_MMU_PDE_ADDR_ALIGNSHIFT; + ui32RegVal = (IMG_UINT32)(psDevInfo->sKernelPDDevPAddr.uiAddr >> SGX_MMU_PDE_ADDR_ALIGNSHIFT); #if defined(FIX_HW_BRN_28011) OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal); @@ -506,6 +506,16 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo, /* enable 36bit addressing mode if the MMU supports it*/ OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK); PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK, ui32PDUMPFlags); +#else + #if defined(EUR_CR_BIF_36BIT_ADDRESSING) + OSWriteHWReg(psDevInfo->pvRegsBaseKM, + EUR_CR_BIF_36BIT_ADDRESSING, + 0); + PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, + EUR_CR_BIF_36BIT_ADDRESSING, + 0, + ui32PDUMPFlags); + #endif #endif SGXResetInitBIFContexts(psDevInfo, ui32PDUMPFlags); @@ -589,11 +599,11 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo, SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_FALSE); /* Map in the dummy page. */ - psDevInfo->pui32BIFResetPD[ui32PDIndex] = (psDevInfo->sBIFResetPTDevPAddr.uiAddr + psDevInfo->pui32BIFResetPD[ui32PDIndex] = (IMG_UINT32)(psDevInfo->sBIFResetPTDevPAddr.uiAddr >>SGX_MMU_PDE_ADDR_ALIGNSHIFT) | SGX_MMU_PDE_PAGE_SIZE_4K | SGX_MMU_PDE_VALID; - psDevInfo->pui32BIFResetPT[ui32PTIndex] = (psDevInfo->sBIFResetPageDevPAddr.uiAddr + psDevInfo->pui32BIFResetPT[ui32PTIndex] = (IMG_UINT32)(psDevInfo->sBIFResetPageDevPAddr.uiAddr >>SGX_MMU_PTE_ADDR_ALIGNSHIFT) | SGX_MMU_PTE_VALID; @@ -715,7 +725,7 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo, (4 << EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SHIFT) | #endif #if defined(FIX_HW_BRN_33809) - (2 << EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SHIFT) | + (1 << EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SHIFT) | #endif (0xC << EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SHIFT); OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL, ui32RegVal); diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxtransfer.c b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxtransfer.c index 81f3b0742b7..74dbc9969e6 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxtransfer.c +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxtransfer.c @@ -58,11 +58,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "sgxutils.h" #include "ttrace.h" -#if defined (SUPPORT_SID_INTERFACE) -IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSFER_SGX_KICK_KM *psKick) -#else -IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSFER_SGX_KICK *psKick) +#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) +#include "pvr_sync.h" #endif + +IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSFER_SGX_KICK *psKick) { PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psKick->hCCBMemInfo; SGXMKIF_COMMAND sCommand = {0}; @@ -125,7 +125,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_TA_SYNC, psSyncInfo, PVRSRV_SYNCOP_SAMPLE); - psSharedTransferCmd->ui32TASyncWriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++; + psSharedTransferCmd->ui32TASyncWriteOpsPendingVal = SyncTakeWriteOp(psSyncInfo, SYNC_OP_CLASS_TQ_3D); psSharedTransferCmd->ui32TASyncReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; psSharedTransferCmd->sTASyncWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; @@ -144,7 +144,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_3D_SYNC, psSyncInfo, PVRSRV_SYNCOP_SAMPLE); - psSharedTransferCmd->ui323DSyncWriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++; + psSharedTransferCmd->ui323DSyncWriteOpsPendingVal = SyncTakeWriteOp(psSyncInfo,SYNC_OP_CLASS_TQ_3D); psSharedTransferCmd->ui323DSyncReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; psSharedTransferCmd->s3DSyncWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; @@ -210,9 +210,6 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF } } - psSharedTransferCmd->ui32NumSrcSyncs = ui32RealSrcSyncNum; - psSharedTransferCmd->ui32NumDstSyncs = ui32RealDstSyncNum; - if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING) == 0UL) { IMG_UINT32 i = 0; @@ -271,7 +268,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF if (abSrcSyncEnable[loop]) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; - psSyncInfo->psSyncData->ui32ReadOpsPending++; + SyncTakeReadOp(psSyncInfo, SYNC_OP_CLASS_TQ_3D); } } for (loop = 0; loop < psKick->ui32NumDstSync; loop++) @@ -279,15 +276,92 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF if (abDstSyncEnable[loop]) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; - psSyncInfo->psSyncData->ui32WriteOpsPending++; + SyncTakeWriteOp(psSyncInfo, SYNC_OP_CLASS_TQ_3D); } } + +#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) + if (ui32RealDstSyncNum < SGX_MAX_TRANSFER_SYNC_OPS - 2 && psKick->iFenceFd > 0) + { + IMG_HANDLE ahSyncInfo[SGX_MAX_SRC_SYNCS_TA]; + PVRSRV_DEVICE_SYNC_OBJECT *apsDevSyncs = &psSharedTransferCmd->asDstSyncs[ui32RealDstSyncNum]; + IMG_UINT32 ui32NumSrcSyncs = 1; + IMG_UINT32 i; + ahSyncInfo[0] = (IMG_HANDLE)(psKick->iFenceFd - 1); + + eError = PVRSyncPatchTransferSyncInfos(ahSyncInfo, apsDevSyncs, &ui32NumSrcSyncs); + if (eError != PVRSRV_OK) + { + /* We didn't kick yet, or perform PDUMP processing, so we should + * be able to trivially roll back any changes made to the sync + * data. If we don't do this, we'll wedge services cleanup. + */ + + for (loop = 0; loop < psKick->ui32NumDstSync; loop++) + { + if (abDstSyncEnable[loop]) + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; + psSyncInfo->psSyncData->ui32WriteOpsPending--; + } + } + + for (loop = 0; loop < psKick->ui32NumSrcSync; loop++) + { + if (abSrcSyncEnable[loop]) + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; + psSyncInfo->psSyncData->ui32ReadOpsPending--; + } + } + + if (psKick->h3DSyncInfo != IMG_NULL) + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo; + psSyncInfo->psSyncData->ui32WriteOpsPending++; + } + + if (psKick->hTASyncInfo != IMG_NULL) + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo; + psSyncInfo->psSyncData->ui32WriteOpsPending--; + } + + PVR_DPF((PVR_DBG_ERROR, "SGXSubmitTransferKM: PVRSyncPatchTransferKickSyncInfos failed.")); + PVR_TTRACE(PVRSRV_TRACE_GROUP_TRANSFER, PVRSRV_TRACE_CLASS_FUNCTION_EXIT, + TRANSFER_TOKEN_SUBMIT); + return eError; + } + + /* Find a free dst sync to slot in our extra sync */ + for (loop = 0; loop < psKick->ui32NumDstSync; loop++) + { + if (abDstSyncEnable[loop]) + break; + } + + /* We shouldn't be in this code path if ui32RealDstSyncNum + * didn't allow for at least two free synchronization slots. + */ + PVR_ASSERT(loop + ui32NumSrcSyncs <= SGX_MAX_TRANSFER_SYNC_OPS); + + /* Slot in the extra dst syncs */ + for (i = 0; i < ui32NumSrcSyncs; i++) + { + psKick->ahDstSyncInfo[loop + i] = ahSyncInfo[i]; + abDstSyncEnable[loop + i] = IMG_TRUE; + psKick->ui32NumDstSync++; + ui32RealDstSyncNum++; + } + } +#endif /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */ } + psSharedTransferCmd->ui32NumSrcSyncs = ui32RealSrcSyncNum; + psSharedTransferCmd->ui32NumDstSyncs = ui32RealDstSyncNum; + #if defined(PDUMP) - if ((PDumpIsCaptureFrameKM() - || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)) - && (bPersistentProcess == IMG_FALSE) ) + if (PDumpWillCapture(psKick->ui32PDumpFlags)) { PDUMPCOMMENT("Shared part of transfer command\r\n"); PDUMPMEM(psSharedTransferCmd, @@ -305,9 +379,15 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF { if (abSrcSyncEnable[loop]) { + IMG_UINT32 ui32PDumpReadOp2 = 0; psSyncInfo = psKick->ahSrcSyncInfo[loop]; PDUMPCOMMENT("Tweak src surface write op in transfer cmd\r\n"); +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_PERSISTENT, "TQ Src: PDump sync sample: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, psCCBMemInfo, psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asSrcSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32WriteOpsPendingVal)), @@ -322,6 +402,14 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), psKick->ui32PDumpFlags, MAKEUNIQUETAG(psCCBMemInfo)); + + PDUMPCOMMENT("Tweak srv surface read op2 in transfer cmd\r\n"); + PDUMPMEM(&ui32PDumpReadOp2, + psCCBMemInfo, + psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asSrcSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32ReadOps2PendingVal)), + sizeof(ui32PDumpReadOp2), + psKick->ui32PDumpFlags, + MAKEUNIQUETAG(psCCBMemInfo)); i++; } } @@ -335,6 +423,11 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF psSyncInfo = psKick->ahDstSyncInfo[loop]; PDUMPCOMMENT("Tweak dest surface write op in transfer cmd\r\n"); +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_PERSISTENT, "TQ Dst: PDump sync sample: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, psCCBMemInfo, psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asDstSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32WriteOpsPendingVal)), @@ -373,6 +466,12 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; psSyncInfo->psSyncData->ui32LastReadOpDumpVal++; +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_PERSISTENT, + "TQ Src: PDump sync update: uiAddr = 0x%08x, ui32LastReadOpDumpVal = 0x%08x\r\n", + psSyncInfo->sReadOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastReadOpDumpVal); +#endif } } @@ -380,8 +479,14 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF { if (abDstSyncEnable[loop]) { - psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[0]; + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; psSyncInfo->psSyncData->ui32LastOpDumpVal++; +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_PERSISTENT, + "TQ Dst: PDump sync update: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif } } } @@ -391,6 +496,11 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF psSyncInfo = psKick->hTASyncInfo; PDUMPCOMMENT("Tweak TA/TQ surface write op in transfer cmd\r\n"); +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENT("TQ TA/TQ: PDump sync sample: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, psCCBMemInfo, psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, ui32TASyncWriteOpsPendingVal)), @@ -398,6 +508,14 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF psKick->ui32PDumpFlags, MAKEUNIQUETAG(psCCBMemInfo)); + PDUMPCOMMENT("Tweak TA/TQ surface read op in transfer cmd\r\n"); + PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, + psCCBMemInfo, + psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, ui32TASyncReadOpsPendingVal)), + sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), + psKick->ui32PDumpFlags, + MAKEUNIQUETAG(psCCBMemInfo)); + psSyncInfo->psSyncData->ui32LastOpDumpVal++; } @@ -406,6 +524,11 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF psSyncInfo = psKick->h3DSyncInfo; PDUMPCOMMENT("Tweak 3D/TQ surface write op in transfer cmd\r\n"); +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENT("TQ 3D/TQ: PDump sync sample: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, psCCBMemInfo, psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, ui323DSyncWriteOpsPendingVal)), @@ -413,6 +536,14 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF psKick->ui32PDumpFlags, MAKEUNIQUETAG(psCCBMemInfo)); + PDUMPCOMMENT("Tweak 3D/TQ surface read op in transfer cmd\r\n"); + PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, + psCCBMemInfo, + psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, ui323DSyncReadOpsPendingVal)), + sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), + psKick->ui32PDumpFlags, + MAKEUNIQUETAG(psCCBMemInfo)); + psSyncInfo->psSyncData->ui32LastOpDumpVal++; } } @@ -435,7 +566,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF if (abSrcSyncEnable[loop]) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; - psSyncInfo->psSyncData->ui32ReadOpsPending--; + SyncRollBackReadOp(psSyncInfo, SYNC_OP_CLASS_TQ_3D); #if defined(PDUMP) if (PDumpIsCaptureFrameKM() || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)) @@ -450,7 +581,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF if (abDstSyncEnable[loop]) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; - psSyncInfo->psSyncData->ui32WriteOpsPending--; + SyncRollBackWriteOp(psSyncInfo, SYNC_OP_CLASS_TQ_3D); #if defined(PDUMP) if (PDumpIsCaptureFrameKM() || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)) @@ -466,14 +597,14 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF if (psKick->hTASyncInfo != IMG_NULL) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo; - psSyncInfo->psSyncData->ui32WriteOpsPending--; + SyncRollBackWriteOp(psSyncInfo, SYNC_OP_CLASS_TQ_3D); } /* Command needed to be synchronised with the 3D? */ if (psKick->h3DSyncInfo != IMG_NULL) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo; - psSyncInfo->psSyncData->ui32WriteOpsPending--; + SyncRollBackWriteOp(psSyncInfo, SYNC_OP_CLASS_TQ_3D); } } @@ -529,11 +660,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF } #if defined(SGX_FEATURE_2D_HARDWARE) -#if defined (SUPPORT_SID_INTERFACE) -IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK_KM *psKick) -#else IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK *psKick) -#endif { PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psKick->hCCBMemInfo; @@ -543,21 +670,6 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK PVRSRV_ERROR eError; IMG_UINT32 i; IMG_HANDLE hDevMemContext = IMG_NULL; -#if defined(PDUMP) - IMG_BOOL bPersistentProcess = IMG_FALSE; - /* - * For persistent processes, the HW kicks should not go into the - * extended init phase; only keep memory transactions from the - * window system which are necessary to run the client app. - */ - { - PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData(); - if(psPerProc != IMG_NULL) - { - bPersistentProcess = psPerProc->bPDumpPersistent; - } - } -#endif /* PDUMP */ #if defined(FIX_HW_BRN_31620) hDevMemContext = psKick->hDevMemContext; #endif @@ -571,31 +683,39 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK /* PRQA S 3305 1 */ ps2DCmd = CCB_DATA_FROM_OFFSET(SGXMKIF_2DCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset); - OSMemSet(ps2DCmd, 0, sizeof(*ps2DCmd)); - /* Command needs to be synchronised with the TA? */ if (psKick->hTASyncInfo != IMG_NULL) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo; - ps2DCmd->sTASyncData.ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++; + ps2DCmd->sTASyncData.ui32WriteOpsPendingVal = SyncTakeWriteOp(psSyncInfo, SYNC_OP_CLASS_TQ_2D); ps2DCmd->sTASyncData.ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; ps2DCmd->sTASyncData.sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; ps2DCmd->sTASyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; } + else + { + ps2DCmd->sTASyncData.sWriteOpsCompleteDevVAddr.uiAddr = 0; + ps2DCmd->sTASyncData.sReadOpsCompleteDevVAddr.uiAddr = 0; + } /* Command needs to be synchronised with the 3D? */ if (psKick->h3DSyncInfo != IMG_NULL) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo; - ps2DCmd->s3DSyncData.ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++; + ps2DCmd->s3DSyncData.ui32WriteOpsPendingVal = SyncTakeWriteOp(psSyncInfo, SYNC_OP_CLASS_TQ_2D); ps2DCmd->s3DSyncData.ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; ps2DCmd->s3DSyncData.sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; ps2DCmd->s3DSyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; } + else + { + ps2DCmd->s3DSyncData.sWriteOpsCompleteDevVAddr.uiAddr = 0; + ps2DCmd->s3DSyncData.sReadOpsCompleteDevVAddr.uiAddr = 0; + } /* * We allow the first source and destination sync objects to be the @@ -604,6 +724,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK * values from the objects. */ ps2DCmd->ui32NumSrcSync = psKick->ui32NumSrcSync; + for (i = 0; i < psKick->ui32NumSrcSync; i++) { psSyncInfo = psKick->ahSrcSyncInfo[i]; @@ -626,25 +747,26 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK ps2DCmd->sDstSyncData.sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; ps2DCmd->sDstSyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; ps2DCmd->sDstSyncData.sReadOps2CompleteDevVAddr = psSyncInfo->sReadOps2CompleteDevVAddr; + + /* We can do this immediately as we only have one */ + SyncTakeWriteOp(psSyncInfo, SYNC_OP_CLASS_TQ_2D); + } + else + { + ps2DCmd->sDstSyncData.sWriteOpsCompleteDevVAddr.uiAddr = 0; + ps2DCmd->sDstSyncData.sReadOpsCompleteDevVAddr.uiAddr = 0; + ps2DCmd->sDstSyncData.sReadOps2CompleteDevVAddr.uiAddr = 0; } /* Read/Write ops pending updates, delayed from above */ for (i = 0; i < psKick->ui32NumSrcSync; i++) { psSyncInfo = psKick->ahSrcSyncInfo[i]; - psSyncInfo->psSyncData->ui32ReadOpsPending++; - } - - if (psKick->hDstSyncInfo != IMG_NULL) - { - psSyncInfo = psKick->hDstSyncInfo; - psSyncInfo->psSyncData->ui32WriteOpsPending++; + SyncTakeReadOp(psSyncInfo, SYNC_OP_CLASS_TQ_2D); } #if defined(PDUMP) - if ((PDumpIsCaptureFrameKM() - || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)) - && (bPersistentProcess == IMG_FALSE) ) + if (PDumpWillCapture(psKick->ui32PDumpFlags)) { /* Pdump the command from the per context CCB */ PDUMPCOMMENT("Shared part of 2D command\r\n"); @@ -710,12 +832,24 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK { psSyncInfo = psKick->ahSrcSyncInfo[i]; psSyncInfo->psSyncData->ui32LastReadOpDumpVal++; +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_PERSISTENT, + "TQ2D Src: PDump sync update: uiAddr = 0x%08x, ui32LastReadOpDumpVal = 0x%08x\r\n", + psSyncInfo->sReadOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastReadOpDumpVal); +#endif } if (psKick->hDstSyncInfo != IMG_NULL) { psSyncInfo = psKick->hDstSyncInfo; psSyncInfo->psSyncData->ui32LastOpDumpVal++; +#if defined(SUPPORT_PDUMP_SYNC_DEBUG) + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_PERSISTENT, + "TQ2D Dst: PDump sync update: uiAddr = 0x%08x, ui32LastOpDumpVal = 0x%08x\r\n", + psSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr, + psSyncInfo->psSyncData->ui32LastOpDumpVal); +#endif } } #endif @@ -749,13 +883,13 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK for (i = 0; i < psKick->ui32NumSrcSync; i++) { psSyncInfo = psKick->ahSrcSyncInfo[i]; - psSyncInfo->psSyncData->ui32ReadOpsPending--; + SyncRollBackReadOp(psSyncInfo, SYNC_OP_CLASS_TQ_2D); } if (psKick->hDstSyncInfo != IMG_NULL) { psSyncInfo = psKick->hDstSyncInfo; - psSyncInfo->psSyncData->ui32WriteOpsPending--; + SyncRollBackWriteOp(psSyncInfo, SYNC_OP_CLASS_TQ_2D); } /* Command needed to be synchronised with the TA? */ @@ -763,7 +897,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo; - psSyncInfo->psSyncData->ui32WriteOpsPending--; + SyncRollBackWriteOp(psSyncInfo, SYNC_OP_CLASS_TQ_2D); } /* Command needed to be synchronised with the 3D? */ @@ -771,7 +905,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo; - psSyncInfo->psSyncData->ui32WriteOpsPending--; + SyncRollBackWriteOp(psSyncInfo, SYNC_OP_CLASS_TQ_2D); } } diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxutils.c b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxutils.c index 227675d1545..b1d2b1309e8 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxutils.c +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxutils.c @@ -57,6 +57,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "pvr_debug.h" #include "sgxutils.h" #include "ttrace.h" +#include "sgxmmu.h" #ifdef __linux__ #include <linux/kernel.h> // sprintf @@ -172,9 +173,11 @@ IMG_VOID SGXTestActivePowerEvent (PVRSRV_DEVICE_NODE *psDeviceNode, ((psSGXHostCtl->ui32InterruptFlags & PVRSRV_USSE_EDM_INTERRUPT_IDLE) != 0)) { psSGXHostCtl->ui32InterruptClearFlags |= PVRSRV_USSE_EDM_INTERRUPT_IDLE; - psDevInfo->bSGXIdle = IMG_TRUE; - - SysSGXIdleEntered(); + if (psDevInfo->bSGXIdle == IMG_FALSE) + { + psDevInfo->bSGXIdle = IMG_TRUE; + SysSGXIdleEntered(); + } } /* @@ -284,7 +287,11 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode, #if defined(PDUMP) IMG_VOID *pvDumpCommand; IMG_BOOL bPDumpIsSuspended = PDumpIsSuspended(); - IMG_BOOL bPersistentProcess = IMG_FALSE; +#if defined(SUPPORT_PDUMP_MULTI_PROCESS) + IMG_BOOL bPDumpActive = _PDumpIsProcessActive(); +#else + IMG_BOOL bPDumpActive = IMG_TRUE; +#endif #else PVR_UNREFERENCED_PARAMETER(ui32CallerID); PVR_UNREFERENCED_PARAMETER(ui32PDumpFlags); @@ -422,20 +429,6 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode, } } #endif -#if defined(PDUMP) - /* - * For persistent processes, the HW kicks should not go into the - * extended init phase; only keep memory transactions from the - * window system which are necessary to run the client app. - */ - { - PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData(); - if(psPerProc != IMG_NULL) - { - bPersistentProcess = psPerProc->bPDumpPersistent; - } - } -#endif /* PDUMP */ psKernelCCB = psDevInfo->psKernelCCBInfo; psSGXCommand = SGXAcquireKernelCCBSlot(psKernelCCB); @@ -496,7 +489,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode, #if defined(PDUMP) if ((ui32CallerID != ISR_ID) && (bPDumpIsSuspended == IMG_FALSE) && - (bPersistentProcess == IMG_FALSE) ) + (bPDumpActive == IMG_TRUE) ) { /* Poll for space in the CCB. */ PDUMPCOMMENTWITHFLAGS(ui32PDumpFlags, "Poll for space in the Kernel CCB\r\n"); @@ -559,7 +552,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode, #if defined(PDUMP) if ((ui32CallerID != ISR_ID) && (bPDumpIsSuspended == IMG_FALSE) && - (bPersistentProcess == IMG_FALSE) ) + (bPDumpActive == IMG_TRUE) ) { #if defined(FIX_HW_BRN_26620) && defined(SGX_FEATURE_SYSTEM_CACHE) && !defined(SGX_BYPASS_SYSTEM_CACHE) PDUMPCOMMENTWITHFLAGS(ui32PDumpFlags, "Poll for previous Kernel CCB CMD to be read\r\n"); @@ -709,9 +702,6 @@ PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode, /* Note that a power-up has been dumped in the init phase. */ PDUMPSUSPEND(); - SysSGXCommandPending(psDevInfo->bSGXIdle); - psDevInfo->bSGXIdle = IMG_FALSE; - /* Ensure that SGX is powered up before kicking the ukernel. */ eError = PVRSRVSetDevicePowerStateKM(psDeviceNode->sDevId.ui32DeviceIndex, PVRSRV_DEV_POWER_STATE_ON); @@ -724,11 +714,15 @@ PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode, } else { - PVR_DPF((PVR_DBG_ERROR,"SGXScheduleCCBCommandKM failed to acquire lock - " + PVR_DPF((PVR_DBG_ERROR,"SGXScheduleCCBCommandKM failed to power up device - " "ui32CallerID:%d eError:%u", ui32CallerID, eError)); + PVRSRVPowerUnlock(ui32CallerID); return eError; } + SysSGXCommandPending(psDevInfo->bSGXIdle); + psDevInfo->bSGXIdle = IMG_FALSE; + eError = SGXScheduleCCBCommand(psDeviceNode, eCmdType, psCommandData, ui32CallerID, ui32PDumpFlags, hDevMemContext, bLastInScene); PVRSRVPowerUnlock(ui32CallerID); @@ -750,10 +744,18 @@ PVRSRV_ERROR SGXScheduleProcessQueuesKM(PVRSRV_DEVICE_NODE *psDeviceNode) { PVRSRV_ERROR eError; PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; - SGXMKIF_HOST_CTL *psHostCtl = psDevInfo->psKernelSGXHostCtlMemInfo->pvLinAddrKM; + SGXMKIF_HOST_CTL *psHostCtl; IMG_UINT32 ui32PowerStatus; SGXMKIF_COMMAND sCommand = {0}; + if (psDevInfo->psKernelSGXHostCtlMemInfo == IMG_NULL) + { + /* Part2 hasn't run yet, we can't do anything */ + return PVRSRV_OK; + } + + psHostCtl = psDevInfo->psKernelSGXHostCtlMemInfo->pvLinAddrKM; + ui32PowerStatus = psHostCtl->ui32PowerStatus; if ((ui32PowerStatus & PVRSRV_USSE_EDM_POWMAN_NO_WORK) != 0) { @@ -809,11 +811,7 @@ IMG_BOOL SGXIsDevicePowered(PVRSRV_DEVICE_NODE *psDeviceNode) ******************************************************************************/ IMG_EXPORT PVRSRV_ERROR SGXGetInternalDevInfoKM(IMG_HANDLE hDevCookie, -#if defined (SUPPORT_SID_INTERFACE) - SGX_INTERNAL_DEVINFO_KM *psSGXInternalDevInfo) -#else SGX_INTERNAL_DEVINFO *psSGXInternalDevInfo) -#endif { PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)((PVRSRV_DEVICE_NODE *)hDevCookie)->pvDevice; @@ -1092,6 +1090,7 @@ IMG_HANDLE SGXRegisterHWRenderContextKM(IMG_HANDLE hDeviceNode, IMG_UINT8 *pSrc; IMG_UINT8 *pDst; PRESMAN_ITEM psResItem; + IMG_UINT32 ui32PDDevPAddrInDirListFormat; eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(SGX_HW_RENDER_CONTEXT_CLEANUP), @@ -1157,17 +1156,23 @@ IMG_HANDLE SGXRegisterHWRenderContextKM(IMG_HANDLE hDeviceNode, psMMUContext = BM_GetMMUContextFromMemContext(hDevMemContextInt); sPDDevPAddr = psDeviceNode->pfnMMUGetPDDevPAddr(psMMUContext); + /* + The PDDevPAddr needs to be shifted-down, as the uKernel expects it in the + format it will be inserted into the DirList registers in. + */ + ui32PDDevPAddrInDirListFormat = (IMG_UINT32)(sPDDevPAddr.uiAddr >> SGX_MMU_PTE_ADDR_ALIGNSHIFT); + /* patch-in the Page-Directory Device-Physical address. Note that this is copied-in one byte at a time, as we have no guarantee that the usermode- provided ui32OffsetToPDDevPAddr is a validly-aligned address for the current CPU architecture. */ - pSrc = (IMG_UINT8 *)&sPDDevPAddr; + pSrc = (IMG_UINT8 *)&ui32PDDevPAddrInDirListFormat; pDst = (IMG_UINT8 *)psCleanup->psHWRenderContextMemInfo->pvLinAddrKM; pDst += ui32OffsetToPDDevPAddr; - for (iPtrByte = 0; iPtrByte < sizeof(IMG_DEV_PHYADDR); iPtrByte++) + for (iPtrByte = 0; iPtrByte < sizeof(ui32PDDevPAddrInDirListFormat); iPtrByte++) { pDst[iPtrByte] = pSrc[iPtrByte]; } @@ -1272,6 +1277,7 @@ IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE hDeviceNode, IMG_UINT8 *pSrc; IMG_UINT8 *pDst; PRESMAN_ITEM psResItem; + IMG_UINT32 ui32PDDevPAddrInDirListFormat; eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(SGX_HW_TRANSFER_CONTEXT_CLEANUP), @@ -1288,6 +1294,7 @@ IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE hDeviceNode, psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo; psHeapInfo = &psDevMemoryInfo->psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID]; + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "Allocate HW Transfer context"); eError = PVRSRVAllocDeviceMemKM(hDeviceNode, psPerProc, psHeapInfo->hDevMemHeap, @@ -1337,17 +1344,23 @@ IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE hDeviceNode, psMMUContext = BM_GetMMUContextFromMemContext(hDevMemContextInt); sPDDevPAddr = psDeviceNode->pfnMMUGetPDDevPAddr(psMMUContext); + /* + The PDDevPAddr needs to be shifted-down, as the uKernel expects it in the + format it will be inserted into the DirList registers in. + */ + ui32PDDevPAddrInDirListFormat = (IMG_UINT32)(sPDDevPAddr.uiAddr >> SGX_MMU_PTE_ADDR_ALIGNSHIFT); + /* patch-in the Page-Directory Device-Physical address. Note that this is copied-in one byte at a time, as we have no guarantee that the usermode- provided ui32OffsetToPDDevPAddr is a validly-aligned address for the current CPU architecture. */ - pSrc = (IMG_UINT8 *)&sPDDevPAddr; + pSrc = (IMG_UINT8 *)&ui32PDDevPAddrInDirListFormat; pDst = (IMG_UINT8 *)psCleanup->psHWTransferContextMemInfo->pvLinAddrKM; pDst += ui32OffsetToPDDevPAddr; - for (iPtrByte = 0; iPtrByte < sizeof(IMG_DEV_PHYADDR); iPtrByte++) + for (iPtrByte = 0; iPtrByte < sizeof(ui32PDDevPAddrInDirListFormat); iPtrByte++) { pDst[iPtrByte] = pSrc[iPtrByte]; } @@ -1605,6 +1618,7 @@ IMG_HANDLE SGXRegisterHW2DContextKM(IMG_HANDLE hDeviceNode, IMG_UINT8 *pSrc; IMG_UINT8 *pDst; PRESMAN_ITEM psResItem; + IMG_UINT32 ui32PDDevPAddrInDirListFormat; eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(SGX_HW_2D_CONTEXT_CLEANUP), @@ -1669,17 +1683,23 @@ IMG_HANDLE SGXRegisterHW2DContextKM(IMG_HANDLE hDeviceNode, psMMUContext = BM_GetMMUContextFromMemContext(hDevMemContextInt); sPDDevPAddr = psDeviceNode->pfnMMUGetPDDevPAddr(psMMUContext); + /* + The PDDevPAddr needs to be shifted-down, as the uKernel expects it in the + format it will be inserted into the DirList registers in. + */ + ui32PDDevPAddrInDirListFormat = sPDDevPAddr.uiAddr >> SGX_MMU_PTE_ADDR_ALIGNSHIFT; + /* patch-in the Page-Directory Device-Physical address. Note that this is copied-in one byte at a time, as we have no guarantee that the usermode- provided ui32OffsetToPDDevPAddr is a validly-aligned address for the current CPU architecture. */ - pSrc = (IMG_UINT8 *)&sPDDevPAddr; + pSrc = (IMG_UINT8 *)&ui32PDDevPAddrInDirListFormat; pDst = (IMG_UINT8 *)psCleanup->psHW2DContextMemInfo->pvLinAddrKM; pDst += ui32OffsetToPDDevPAddr; - for (iPtrByte = 0; iPtrByte < sizeof(IMG_DEV_PHYADDR); iPtrByte++) + for (iPtrByte = 0; iPtrByte < sizeof(ui32PDDevPAddrInDirListFormat); iPtrByte++) { pDst[iPtrByte] = pSrc[iPtrByte]; } @@ -1848,8 +1868,8 @@ PVRSRV_ERROR SGX2DQueryBlitsCompleteKM(PVRSRV_SGXDEV_INFO *psDevInfo, { PVRSRV_SYNC_DATA *psSyncData = psSyncInfo->psSyncData; - PVR_TRACE(("SGX2DQueryBlitsCompleteKM: Syncinfo: 0x%x, Syncdata: 0x%x", - (IMG_UINTPTR_T)psSyncInfo, (IMG_UINTPTR_T)psSyncData)); + PVR_TRACE(("SGX2DQueryBlitsCompleteKM: Syncinfo: 0x%p, Syncdata: 0x%p", + psSyncInfo, psSyncData)); PVR_TRACE(("SGX2DQueryBlitsCompleteKM: Read ops complete: %d, Read ops pending: %d", psSyncData->ui32ReadOpsComplete, psSyncData->ui32ReadOpsPending)); PVR_TRACE(("SGX2DQueryBlitsCompleteKM: Write ops complete: %d, Write ops pending: %d", psSyncData->ui32WriteOpsComplete, psSyncData->ui32WriteOpsPending)); diff --git a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxutils.h b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxutils.h index fc2ef6f34c3..fc2ef6f34c3 100644..100755 --- a/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxutils.h +++ b/drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxutils.h |