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| author | Thomas Gleixner <tglx@linutronix.de> | 2011-05-20 20:06:24 +0200 | 
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2011-05-20 20:08:05 +0200 | 
| commit | 250f972d85effad5b6e10da4bbd877e6a4b503b6 (patch) | |
| tree | 007393a6fc6439af7e0121dd99a6f9f9fb8405bc /arch/x86/kernel/cpu/intel.c | |
| parent | 7372b0b122af0f6675f3ab65bfd91c8a438e0480 (diff) | |
| parent | bbe7b8bef48c567f5ff3f6041c1fb011292e8f12 (diff) | |
| download | olio-linux-3.10-250f972d85effad5b6e10da4bbd877e6a4b503b6.tar.xz olio-linux-3.10-250f972d85effad5b6e10da4bbd877e6a4b503b6.zip  | |
Merge branch 'timers/urgent' into timers/core
Reason: Get upstream fixes and kfree_rcu which is necessary for a
follow up patch.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 29 | 
1 files changed, 19 insertions, 10 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index df86bc8c859..1edf5ba4fb2 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -29,10 +29,10 @@  static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)  { +	u64 misc_enable; +  	/* Unmask CPUID levels if masked: */  	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { -		u64 misc_enable; -  		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);  		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) { @@ -118,8 +118,6 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)  	 * (model 2) with the same problem.  	 */  	if (c->x86 == 15) { -		u64 misc_enable; -  		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);  		if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) { @@ -130,6 +128,19 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)  		}  	}  #endif + +	/* +	 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, +	 * clear the fast string and enhanced fast string CPU capabilities. +	 */ +	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { +		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); +		if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { +			printk(KERN_INFO "Disabled fast string operations\n"); +			setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); +			setup_clear_cpu_cap(X86_FEATURE_ERMS); +		} +	}  }  #ifdef CONFIG_X86_32 @@ -400,12 +411,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)  		switch (c->x86_model) {  		case 5: -			if (c->x86_mask == 0) { -				if (l2 == 0) -					p = "Celeron (Covington)"; -				else if (l2 == 256) -					p = "Mobile Pentium II (Dixon)"; -			} +			if (l2 == 0) +				p = "Celeron (Covington)"; +			else if (l2 == 256) +				p = "Mobile Pentium II (Dixon)";  			break;  		case 6:  |