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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2013-04-30 11:10:09 +1000 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2013-04-30 11:10:09 +1000 |
| commit | bc23100a0d646aedb6e17fbcecdc35a24cd3bf2a (patch) | |
| tree | afbf44b177d17a8450d606b6d976e76e8e964273 /arch/powerpc/sysdev/fsl_pci.h | |
| parent | 28bf41a1fedad76e9b4de70c9573bb3f8afc3709 (diff) | |
| parent | 9e2ecdbba3b0745f9ed454ab86961e3ccf9dc224 (diff) | |
| download | olio-linux-3.10-bc23100a0d646aedb6e17fbcecdc35a24cd3bf2a.tar.xz olio-linux-3.10-bc23100a0d646aedb6e17fbcecdc35a24cd3bf2a.zip | |
Merge remote-tracking branch 'kumar/next' into next
From Kumar Gala:
<<
Add support for T4 and B4 SoC families from Freescale, e6500 altivec
support, some various board fixes and other minor cleanups.
>>
Diffstat (limited to 'arch/powerpc/sysdev/fsl_pci.h')
| -rw-r--r-- | arch/powerpc/sysdev/fsl_pci.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index c495c00c874..72b5625330e 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -14,9 +14,12 @@ #ifndef __POWERPC_FSL_PCI_H #define __POWERPC_FSL_PCI_H +struct platform_device; + #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ #define PCIE_LTSSM_L0 0x16 /* L0 state */ #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */ +#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */ #define PIWAR_EN 0x80000000 /* Enable */ #define PIWAR_PF 0x20000000 /* prefetch */ #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ @@ -89,6 +92,16 @@ struct ccsr_pci { __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ + u8 res_e38[200]; + __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */ + u8 res_f04[16]; + __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/ +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 +#define PEX_CSR0_LTSSM_L0 0x11 + __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/ + u8 res_f1c[228]; + }; extern int fsl_add_bridge(struct platform_device *pdev, int is_primary); |