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| author | Catalin Marinas <catalin.marinas@arm.com> | 2011-11-22 17:30:31 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2011-12-08 10:30:40 +0000 |
| commit | f7b8156d150f7383b42622a9219b230b36435b4a (patch) | |
| tree | c06e0ed558f7a9e106920a9f3acbb6bed15017bf /arch/arm/mm/fault.c | |
| parent | c9f27f1026f55b543df260ad8ab84a7bdab7792f (diff) | |
| download | olio-linux-3.10-f7b8156d150f7383b42622a9219b230b36435b4a.tar.xz olio-linux-3.10-f7b8156d150f7383b42622a9219b230b36435b4a.zip | |
ARM: LPAE: Add fault handling support
The DFSR and IFSR register format is different when LPAE is enabled. In
addition, DFSR and IFSR have similar definitions for the fault type.
This modifies the fault code to correctly handle the new format.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm/fault.c')
| -rw-r--r-- | arch/arm/mm/fault.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 2a027167772..eb5520fc755 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -110,8 +110,10 @@ void show_pte(struct mm_struct *mm, unsigned long addr) pte = pte_offset_map(pmd, addr); printk(", *pte=%08llx", (long long)pte_val(*pte)); +#ifndef CONFIG_ARM_LPAE printk(", *ppte=%08llx", (long long)pte_val(pte[PTE_HWTABLE_PTRS])); +#endif pte_unmap(pte); } while(0); @@ -428,6 +430,12 @@ do_translation_fault(unsigned long addr, unsigned int fsr, pmd = pmd_offset(pud, addr); pmd_k = pmd_offset(pud_k, addr); +#ifdef CONFIG_ARM_LPAE + /* + * Only one hardware entry per PMD with LPAE. + */ + index = 0; +#else /* * On ARM one Linux PGD entry contains two hardware entries (see page * tables layout in pgtable.h). We normally guarantee that we always @@ -437,6 +445,7 @@ do_translation_fault(unsigned long addr, unsigned int fsr, * for the first of pair. */ index = (addr >> SECTION_SHIFT) & 1; +#endif if (pmd_none(pmd_k[index])) goto bad_area; @@ -484,7 +493,11 @@ struct fsr_info { }; /* FSR definition */ +#ifdef CONFIG_ARM_LPAE +#include "fsr-3level.c" +#else #include "fsr-2level.c" +#endif void __init hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *), @@ -553,6 +566,7 @@ do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs) arm_notify_die("", regs, &info, ifsr, 0); } +#ifndef CONFIG_ARM_LPAE static int __init exceptions_init(void) { if (cpu_architecture() >= CPU_ARCH_ARMv6) { @@ -575,3 +589,4 @@ static int __init exceptions_init(void) } arch_initcall(exceptions_init); +#endif |