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| author | Catalin Marinas <catalin.marinas@arm.com> | 2008-11-06 13:23:07 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2008-11-06 13:23:07 +0000 |
| commit | c30c2f99e10b6a810dae9a25b35c6d48796d8ffb (patch) | |
| tree | ba62c6796e789fc5dfcb16ec8cddb2f1c89203b8 /arch/arm/mm/cache-v7.S | |
| parent | 2bedbdf4148ebbe48c7a89449ab52e475a788f42 (diff) | |
| download | olio-linux-3.10-c30c2f99e10b6a810dae9a25b35c6d48796d8ffb.tar.xz olio-linux-3.10-c30c2f99e10b6a810dae9a25b35c6d48796d8ffb.zip | |
ARMv7: Add extra barriers for flush_cache_all compressed/head.S
The flush_cache_all function on ARMv7 is implemented as a series of
cache operations by set/way. These are not guaranteed to be ordered with
previous memory accesses, requiring a DMB. This patch also adds barriers
for the TLB operations in compressed/head.S
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index d19c2bec2b1..be93ff02a98 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -26,6 +26,7 @@ * - mm - mm_struct describing address space */ ENTRY(v7_flush_dcache_all) + dmb @ ensure ordering with previous memory accesses mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr mov r3, r3, lsr #23 @ left align loc bit field @@ -64,6 +65,7 @@ skip: finished: mov r10, #0 @ swith back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + dsb isb mov pc, lr ENDPROC(v7_flush_dcache_all) |