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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-05-02 09:38:16 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-05-02 09:38:16 -0700 |
| commit | 99c6bcf46d2233d33e441834e958ed0bc22b190a (patch) | |
| tree | 25abf5e856bc0f08d75e623715eb5acc4d4de2b2 /arch/arm/mach-tegra/include | |
| parent | 97b1007a2924aaa9126398623f6755a8c3c6a616 (diff) | |
| parent | 2fdfe1c26fb9f24cfdf124384abb35396ca2cd3f (diff) | |
| download | olio-linux-3.10-99c6bcf46d2233d33e441834e958ed0bc22b190a.tar.xz olio-linux-3.10-99c6bcf46d2233d33e441834e958ed0bc22b190a.zip | |
Merge tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC multiplatform updates from Olof Johansson:
"More multiplatform enablement for ARM platforms. The ones converted
in this branch are:
- bcm2835
- cns3xxx
- sirf
- nomadik
- msx
- spear
- tegra
- ux500
We're getting close to having most of them converted!
One of the larger platforms remaining is Samsung Exynos, and there are
a bunch of supporting patches in this merge window for it. There was
a patch in this branch to a early version of multiplatform conversion,
but it ended up being reverted due to need of more bake time. The
revert commit is part of the branch since it would have required
rebasing multiple dependent branches and they were stable by then"
* tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
mmc: sdhci-s3c: Fix operation on non-single image Samsung platforms
clocksource: nomadik-mtu: fix up clocksource/timer
Revert "ARM: exynos: enable multiplatform support"
ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ"
ARM: exynos: enable multiplatform support
rtc: s3c: make header file local
mtd: onenand/samsung: make regs-onenand.h file local
thermal/exynos: remove unnecessary header inclusions
mmc: sdhci-s3c: remove platform dependencies
ARM: samsung: move mfc device definition to s5p-dev-mfc.c
ARM: exynos: move debug-macro.S to include/debug/
ARM: exynos: prepare for sparse IRQ
ARM: exynos: introduce EXYNOS_ATAGS symbol
ARM: tegra: build assembly files with -march=armv7-a
ARM: Push selects for TWD/SCU into machine entries
ARM: ux500: build hotplug.o for ARMv7-a
ARM: ux500: move to multiplatform
ARM: ux500: make remaining headers local
ARM: ux500: make irqs.h local to platform
ARM: ux500: get rid of <mach/[hardware|db8500-regs].h>
...
Diffstat (limited to 'arch/arm/mach-tegra/include')
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/powergate.h | 54 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/timex.h | 26 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/uncompress.h | 175 |
3 files changed, 0 insertions, 255 deletions
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h deleted file mode 100644 index 06763fe7529..00000000000 --- a/arch/arm/mach-tegra/include/mach/powergate.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * drivers/regulator/tegra-regulator.c - * - * Copyright (c) 2010 Google, Inc - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _MACH_TEGRA_POWERGATE_H_ -#define _MACH_TEGRA_POWERGATE_H_ - -struct clk; - -#define TEGRA_POWERGATE_CPU 0 -#define TEGRA_POWERGATE_3D 1 -#define TEGRA_POWERGATE_VENC 2 -#define TEGRA_POWERGATE_PCIE 3 -#define TEGRA_POWERGATE_VDEC 4 -#define TEGRA_POWERGATE_L2 5 -#define TEGRA_POWERGATE_MPE 6 -#define TEGRA_POWERGATE_HEG 7 -#define TEGRA_POWERGATE_SATA 8 -#define TEGRA_POWERGATE_CPU1 9 -#define TEGRA_POWERGATE_CPU2 10 -#define TEGRA_POWERGATE_CPU3 11 -#define TEGRA_POWERGATE_CELP 12 -#define TEGRA_POWERGATE_3D1 13 - -#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU -#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D - -int __init tegra_powergate_init(void); - -int tegra_cpu_powergate_id(int cpuid); -int tegra_powergate_is_powered(int id); -int tegra_powergate_power_on(int id); -int tegra_powergate_power_off(int id); -int tegra_powergate_remove_clamping(int id); - -/* Must be called with clk disabled, and returns with clk enabled */ -int tegra_powergate_sequence_power_up(int id, struct clk *clk); - -#endif /* _MACH_TEGRA_POWERGATE_H_ */ diff --git a/arch/arm/mach-tegra/include/mach/timex.h b/arch/arm/mach-tegra/include/mach/timex.h deleted file mode 100644 index a44ccbdb7db..00000000000 --- a/arch/arm/mach-tegra/include/mach/timex.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/timex.h - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross <ccross@google.com> - * Erik Gilling <konkers@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_TIMEX_H -#define __MACH_TEGRA_TIMEX_H - -#define CLOCK_TICK_RATE 1000000 - -#endif diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h deleted file mode 100644 index 08386418196..00000000000 --- a/arch/arm/mach-tegra/include/mach/uncompress.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/uncompress.h - * - * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2011 Google, Inc. - * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved. - * - * Author: - * Colin Cross <ccross@google.com> - * Erik Gilling <konkers@google.com> - * Doug Anderson <dianders@chromium.org> - * Stephen Warren <swarren@nvidia.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_UNCOMPRESS_H -#define __MACH_TEGRA_UNCOMPRESS_H - -#include <linux/types.h> -#include <linux/serial_reg.h> - -#include "../../iomap.h" - -#define BIT(x) (1 << (x)) -#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) - -#define DEBUG_UART_SHIFT 2 - -volatile u8 *uart; - -static void putc(int c) -{ - if (uart == NULL) - return; - - while (!(uart[UART_LSR << DEBUG_UART_SHIFT] & UART_LSR_THRE)) - barrier(); - uart[UART_TX << DEBUG_UART_SHIFT] = c; -} - -static inline void flush(void) -{ -} - -static const struct { - u32 base; - u32 reset_reg; - u32 clock_reg; - u32 bit; -} uarts[] = { - { - TEGRA_UARTA_BASE, - TEGRA_CLK_RESET_BASE + 0x04, - TEGRA_CLK_RESET_BASE + 0x10, - 6, - }, - { - TEGRA_UARTB_BASE, - TEGRA_CLK_RESET_BASE + 0x04, - TEGRA_CLK_RESET_BASE + 0x10, - 7, - }, - { - TEGRA_UARTC_BASE, - TEGRA_CLK_RESET_BASE + 0x08, - TEGRA_CLK_RESET_BASE + 0x14, - 23, - }, - { - TEGRA_UARTD_BASE, - TEGRA_CLK_RESET_BASE + 0x0c, - TEGRA_CLK_RESET_BASE + 0x18, - 1, - }, - { - TEGRA_UARTE_BASE, - TEGRA_CLK_RESET_BASE + 0x0c, - TEGRA_CLK_RESET_BASE + 0x18, - 2, - }, -}; - -static inline bool uart_clocked(int i) -{ - if (*(u8 *)uarts[i].reset_reg & BIT(uarts[i].bit)) - return false; - - if (!(*(u8 *)uarts[i].clock_reg & BIT(uarts[i].bit))) - return false; - - return true; -} - -#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA -int auto_odmdata(void) -{ - volatile u32 *pmc = (volatile u32 *)TEGRA_PMC_BASE; - u32 odmdata = pmc[0xa0 / 4]; - - /* - * Bits 19:18 are the console type: 0=default, 1=none, 2==DCC, 3==UART - * Some boards apparently swap the last two values, but we don't have - * any way of catering for that here, so we just accept either. If this - * doesn't make sense for your board, just don't enable this feature. - * - * Bits 17:15 indicate the UART to use, 0/1/2/3/4 are UART A/B/C/D/E. - */ - - switch ((odmdata >> 18) & 3) { - case 2: - case 3: - break; - default: - return -1; - } - - return (odmdata >> 15) & 7; -} -#endif - -/* - * Setup before decompression. This is where we do UART selection for - * earlyprintk and init the uart_base register. - */ -static inline void arch_decomp_setup(void) -{ - int uart_id; - volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE; - u32 chip, div; - -#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA) - uart_id = auto_odmdata(); -#elif defined(CONFIG_TEGRA_DEBUG_UARTA) - uart_id = 0; -#elif defined(CONFIG_TEGRA_DEBUG_UARTB) - uart_id = 1; -#elif defined(CONFIG_TEGRA_DEBUG_UARTC) - uart_id = 2; -#elif defined(CONFIG_TEGRA_DEBUG_UARTD) - uart_id = 3; -#elif defined(CONFIG_TEGRA_DEBUG_UARTE) - uart_id = 4; -#endif - - if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) || - !uart_clocked(uart_id)) - uart = NULL; - else - uart = (volatile u8 *)uarts[uart_id].base; - - if (uart == NULL) - return; - - chip = (apb_misc[0x804 / 4] >> 8) & 0xff; - if (chip == 0x20) - div = 0x0075; - else - div = 0x00dd; - - uart[UART_LCR << DEBUG_UART_SHIFT] |= UART_LCR_DLAB; - uart[UART_DLL << DEBUG_UART_SHIFT] = div & 0xff; - uart[UART_DLM << DEBUG_UART_SHIFT] = div >> 8; - uart[UART_LCR << DEBUG_UART_SHIFT] = 3; -} - -#endif |