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| author | Jean Pihet <j-pihet@ti.com> | 2012-10-04 18:47:10 +0200 |
|---|---|---|
| committer | Kevin Hilman <khilman@ti.com> | 2012-10-15 15:22:24 -0700 |
| commit | 1bef60cc7c284fb3164a2b05e8c121ff0ef56a24 (patch) | |
| tree | c0db1bb23931b46f77eb3b02d91f16c133ae2d65 /arch/arm/mach-omap2/clock3xxx_data.c | |
| parent | ddffeb8c4d0331609ef2581d84de4d763607bd37 (diff) | |
| download | olio-linux-3.10-1bef60cc7c284fb3164a2b05e8c121ff0ef56a24.tar.xz olio-linux-3.10-1bef60cc7c284fb3164a2b05e8c121ff0ef56a24.zip | |
ARM: OMAP: hwmod: align the SmartReflex fck names
Rename the smartreflex fck names for consistency and better readability;
rename the clock aliases so that they match the hwmod main_clk names.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock3xxx_data.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 1f42c9d5ecf..d1786fca691 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3050,8 +3050,8 @@ static struct clk traceclk_fck = { /* SR clocks */ /* SmartReflex fclk (VDD1) */ -static struct clk sr1_fck = { - .name = "sr1_fck", +static struct clk smartreflex_mpu_iva_fck = { + .name = "smartreflex_mpu_iva_fck", .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), @@ -3061,8 +3061,8 @@ static struct clk sr1_fck = { }; /* SmartReflex fclk (VDD2) */ -static struct clk sr2_fck = { - .name = "sr2_fck", +static struct clk smartreflex_core_fck = { + .name = "smartreflex_core_fck", .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), @@ -3478,8 +3478,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), - CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX), - CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX), + CLK(NULL, "smartreflex_mpu_iva_fck", &smartreflex_mpu_iva_fck, CK_34XX | CK_36XX), + CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_34XX | CK_36XX), CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX), CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), |