diff options
| author | Tony Lindgren <tony@atomide.com> | 2012-11-30 08:40:31 -0800 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2012-11-30 08:40:31 -0800 |
| commit | 2589d056122f6dcb405d411eae872aac8cf9da1b (patch) | |
| tree | 8b2fb3a9f8205c110842c59ed42987a6f2b17e1a /arch/arm/mach-omap2/clkt34xx_dpll3m2.c | |
| parent | 42a1cc9c0ec2a00b53b4f02849dc4377b09b3b05 (diff) | |
| parent | 8b9c1ac2e11a9fb3a5a8860fb7570ff7633aa7f7 (diff) | |
| download | olio-linux-3.10-2589d056122f6dcb405d411eae872aac8cf9da1b.tar.xz olio-linux-3.10-2589d056122f6dcb405d411eae872aac8cf9da1b.zip | |
Merge tag 'tags/omap-for-v3.8/devel-prcm-signed' into omap-for-v3.8/cleanup-headers-prepare-multiplatform-v3
omap prcm changes via Paul Walmsley <paul@pwsan.com>:
Some miscellaneous OMAP hwmod changes for 3.8, along with a PRM
change needed for one of the hwmod patches to function.
Basic test logs for this branch on top of Tony's
omap-for-v3.8/clock branch at commit
558a0780b0a04862a678f7823215424b4e5501f9 are here:
http://www.pwsan.com/omap/testlogs/hwmod_devel_a_3.8/20121121161522/
However, omap-for-v3.8/clock at 558a0780 does not include some fixes
that are needed for a successful test. With several reverts,
fixes, and workarounds applied, the following test logs were
obtained:
http://www.pwsan.com/omap/testlogs/TEST_hwmod_devel_a_3.8/20121121162719/
which indicate that the series tests cleanly.
Conflicts:
arch/arm/mach-omap2/cm33xx.c
arch/arm/mach-omap2/io.c
arch/arm/mach-omap2/prm_common.c
Diffstat (limited to 'arch/arm/mach-omap2/clkt34xx_dpll3m2.c')
| -rw-r--r-- | arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index 6cf298e262f..eb69acf2101 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -44,8 +44,10 @@ * Program the DPLL M2 divider with the rounded target rate. Returns * -EINVAL upon error, or 0 upon success. */ -int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) +int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); u32 new_div = 0; u32 unlock_dll = 0; u32 c; @@ -63,7 +65,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; sdrcrate = __clk_get_rate(sdrc_ick_p); - clkrate = __clk_get_rate(clk); + clkrate = __clk_get_rate(hw->clk); if (rate > clkrate) sdrcrate <<= ((rate / clkrate) >> 1); else @@ -112,8 +114,6 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); - clk->rate = rate; - return 0; } |