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| author | Tony Lindgren <tony@atomide.com> | 2012-11-30 08:40:31 -0800 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2012-11-30 08:40:31 -0800 |
| commit | 2589d056122f6dcb405d411eae872aac8cf9da1b (patch) | |
| tree | 8b2fb3a9f8205c110842c59ed42987a6f2b17e1a /arch/arm/mach-omap2/clkt2xxx_dpll.c | |
| parent | 42a1cc9c0ec2a00b53b4f02849dc4377b09b3b05 (diff) | |
| parent | 8b9c1ac2e11a9fb3a5a8860fb7570ff7633aa7f7 (diff) | |
| download | olio-linux-3.10-2589d056122f6dcb405d411eae872aac8cf9da1b.tar.xz olio-linux-3.10-2589d056122f6dcb405d411eae872aac8cf9da1b.zip | |
Merge tag 'tags/omap-for-v3.8/devel-prcm-signed' into omap-for-v3.8/cleanup-headers-prepare-multiplatform-v3
omap prcm changes via Paul Walmsley <paul@pwsan.com>:
Some miscellaneous OMAP hwmod changes for 3.8, along with a PRM
change needed for one of the hwmod patches to function.
Basic test logs for this branch on top of Tony's
omap-for-v3.8/clock branch at commit
558a0780b0a04862a678f7823215424b4e5501f9 are here:
http://www.pwsan.com/omap/testlogs/hwmod_devel_a_3.8/20121121161522/
However, omap-for-v3.8/clock at 558a0780 does not include some fixes
that are needed for a successful test. With several reverts,
fixes, and workarounds applied, the following test logs were
obtained:
http://www.pwsan.com/omap/testlogs/TEST_hwmod_devel_a_3.8/20121121162719/
which indicate that the series tests cleanly.
Conflicts:
arch/arm/mach-omap2/cm33xx.c
arch/arm/mach-omap2/io.c
arch/arm/mach-omap2/prm_common.c
Diffstat (limited to 'arch/arm/mach-omap2/clkt2xxx_dpll.c')
| -rw-r--r-- | arch/arm/mach-omap2/clkt2xxx_dpll.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c index 0890ba94a28..82572e277b9 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpll.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c @@ -15,7 +15,7 @@ #include <linux/io.h> #include "clock.h" -#include "cm2xxx_3xxx.h" +#include "cm2xxx.h" #include "cm-regbits-24xx.h" /* Private functions */ @@ -29,7 +29,7 @@ * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1 * instead. Add some mechanism to optionally enter this mode. */ -static void _allow_idle(struct clk *clk) +static void _allow_idle(struct clk_hw_omap *clk) { if (!clk || !clk->dpll_data) return; @@ -43,7 +43,7 @@ static void _allow_idle(struct clk *clk) * * Disable DPLL automatic idle control. No return value. */ -static void _deny_idle(struct clk *clk) +static void _deny_idle(struct clk_hw_omap *clk) { if (!clk || !clk->dpll_data) return; @@ -53,9 +53,7 @@ static void _deny_idle(struct clk *clk) /* Public data */ - -const struct clkops clkops_omap2xxx_dpll_ops = { +const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = { .allow_idle = _allow_idle, .deny_idle = _deny_idle, }; - |