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| author | Jiri Kosina <jkosina@suse.cz> | 2011-09-15 15:08:05 +0200 | 
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2011-09-15 15:08:18 +0200 | 
| commit | e060c38434b2caa78efe7cedaff4191040b65a15 (patch) | |
| tree | 407361230bf6733f63d8e788e4b5e6566ee04818 /arch/arm/mach-mx5/pm-imx5.c | |
| parent | 10e4ac572eeffe5317019bd7330b6058a400dfc2 (diff) | |
| parent | cc39c6a9bbdebfcf1a7dee64d83bf302bc38d941 (diff) | |
| download | olio-linux-3.10-e060c38434b2caa78efe7cedaff4191040b65a15.tar.xz olio-linux-3.10-e060c38434b2caa78efe7cedaff4191040b65a15.zip  | |
Merge branch 'master' into for-next
Fast-forward merge with Linus to be able to merge patches
based on more recent version of the tree.
Diffstat (limited to 'arch/arm/mach-mx5/pm-imx5.c')
| -rw-r--r-- | arch/arm/mach-mx5/pm-imx5.c | 73 | 
1 files changed, 73 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c new file mode 100644 index 00000000000..e4529af0da7 --- /dev/null +++ b/arch/arm/mach-mx5/pm-imx5.c @@ -0,0 +1,73 @@ +/* + *  Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/suspend.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/err.h> +#include <asm/cacheflush.h> +#include <asm/tlbflush.h> +#include <mach/system.h> +#include "crm_regs.h" + +static struct clk *gpc_dvfs_clk; + +static int mx5_suspend_enter(suspend_state_t state) +{ +	clk_enable(gpc_dvfs_clk); +	switch (state) { +	case PM_SUSPEND_MEM: +		mx5_cpu_lp_set(STOP_POWER_OFF); +		break; +	case PM_SUSPEND_STANDBY: +		mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); +		break; +	default: +		return -EINVAL; +	} + +	if (state == PM_SUSPEND_MEM) { +		local_flush_tlb_all(); +		flush_cache_all(); + +		/*clear the EMPGC0/1 bits */ +		__raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); +		__raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); +	} +	cpu_do_idle(); +	clk_disable(gpc_dvfs_clk); + +	return 0; +} + +static int mx5_pm_valid(suspend_state_t state) +{ +	return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); +} + +static const struct platform_suspend_ops mx5_suspend_ops = { +	.valid = mx5_pm_valid, +	.enter = mx5_suspend_enter, +}; + +static int __init mx5_pm_init(void) +{ +	if (gpc_dvfs_clk == NULL) +		gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); + +	if (!IS_ERR(gpc_dvfs_clk)) { +		if (cpu_is_mx51()) +			suspend_set_ops(&mx5_suspend_ops); +	} else +		return -EPERM; + +	return 0; +} +device_initcall(mx5_pm_init);  |