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| author | Ralf Baechle <ralf@linux-mips.org> | 2005-07-13 18:20:33 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:31:48 +0100 |
| commit | 569f75bd02d20043c4baf9fc38d937f37e7572b0 (patch) | |
| tree | d04f221d275ad6e7d8b7e2fda73f032015eb8242 | |
| parent | 97fb5de194a244df3a257bbddaaad911641af381 (diff) | |
| download | olio-linux-3.10-569f75bd02d20043c4baf9fc38d937f37e7572b0.tar.xz olio-linux-3.10-569f75bd02d20043c4baf9fc38d937f37e7572b0.zip | |
Use an irq_enable_hazard hazard barrier in unmask_mips_irq. This
hasn't been an actual bug, so it's more a change to be 100% compliant
with the requirements of the architecture spec. Similar fix to
mask_mips_irq where there was a slightly less theoretical chance of
getting hit.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/kernel/irq_cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 905ff843a68..060722e42c5 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -40,11 +40,13 @@ static int mips_cpu_irq_base; static inline void unmask_mips_irq(unsigned int irq) { set_c0_status(0x100 << (irq - mips_cpu_irq_base)); + irq_enable_hazard(); } static inline void mask_mips_irq(unsigned int irq) { clear_c0_status(0x100 << (irq - mips_cpu_irq_base)); + irq_disable_hazard(); } static inline void mips_cpu_irq_enable(unsigned int irq) |