diff options
| author | Damien Lespiau <damien.lespiau@intel.com> | 2012-10-29 15:24:49 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-11-11 23:51:04 +0100 |
| commit | 14f86147a90cb47db7ccfd90bf14f830fb34fba9 (patch) | |
| tree | 902659c1d8ca95956f1de0a35f79b7366647d718 | |
| parent | 4358a3748c39de3e66b6dc260af7a5ef785e120b (diff) | |
| download | olio-linux-3.10-14f86147a90cb47db7ccfd90bf14f830fb34fba9.tar.xz olio-linux-3.10-14f86147a90cb47db7ccfd90bf14f830fb34fba9.zip | |
drm/i915: Flush using only the correct base address register
We were writing DSP_ADDR and DSP_SURF unconditionally. This did not
trigger an unclaimed write before HSW as the address of DSP_ADDR has
been repurposed as DSP_LINOFF.
On HSW, though, DSP_LINOFF has been removed and then writting to it
triggers an unclaimed write.
This patch writes to DSP_ADDR or DSP_SURF to flush the display plane
configuration depending on the gen we're running on.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1096066cd2e..fe2bb77c221 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1836,8 +1836,10 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv, void intel_flush_display_plane(struct drm_i915_private *dev_priv, enum plane plane) { - I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); - I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); + if (dev_priv->info->gen >= 4) + I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); + else + I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); } /** |