/*
 * (C) Copyright 2008
 * Dirk Behme <dirk.behme@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef _H1_H_
#define _H1_H_

#include <asm/arch/dss.h>

const omap3_sysinfo sysinfo = {
	DDR_STACKED,
	"OMAP3 Beagle board",
	"NAND",
};

/*
 * IEN  - Input Enable
 * IDIS - Input Disable
 * PTD  - Pull type Down
 * PTU  - Pull type Up
 * DIS  - Pull type selection is inactive
 * EN   - Pull type selection is active
 * M0   - Mode 0
 * The commented string gives the final mux configuration for that pin
 */

#include "pinmux.h"
/*
 * Display Configuration
 */

#define DVI_BEAGLE_ORANGE_COL		0x00FF8000
#define VENC_HEIGHT			0x00ef
#define VENC_WIDTH			0x027f

/*
 * Configure VENC in DSS for Beagle to generate Color Bar
 *
 * Kindly refer to OMAP TRM for definition of these values.
 */
static const struct venc_regs venc_config_std_tv = {
	.status					= 0x0000001B,
	.f_control				= 0x00000040,
	.vidout_ctrl				= 0x00000000,
	.sync_ctrl				= 0x00008000,
	.llen					= 0x00008359,
	.flens					= 0x0000020C,
	.hfltr_ctrl				= 0x00000000,
	.cc_carr_wss_carr			= 0x043F2631,
	.c_phase				= 0x00000024,
	.gain_u					= 0x00000130,
	.gain_v					= 0x00000198,
	.gain_y					= 0x000001C0,
	.black_level				= 0x0000006A,
	.blank_level				= 0x0000005C,
	.x_color				= 0x00000000,
	.m_control				= 0x00000001,
	.bstamp_wss_data			= 0x0000003F,
	.s_carr					= 0x21F07C1F,
	.line21					= 0x00000000,
	.ln_sel					= 0x00000015,
	.l21__wc_ctl				= 0x00001400,
	.htrigger_vtrigger			= 0x00000000,
	.savid__eavid				= 0x069300F4,
	.flen__fal				= 0x0016020C,
	.lal__phase_reset			= 0x00060107,
	.hs_int_start_stop_x			= 0x008D034E,
	.hs_ext_start_stop_x			= 0x000F0359,
	.vs_int_start_x				= 0x01A00000,
	.vs_int_stop_x__vs_int_start_y		= 0x020501A0,
	.vs_int_stop_y__vs_ext_start_x		= 0x01AC0024,
	.vs_ext_stop_x__vs_ext_start_y		= 0x020D01AC,
	.vs_ext_stop_y				= 0x00000006,
	.avid_start_stop_x			= 0x03480079,
	.avid_start_stop_y			= 0x02040024,
	.fid_int_start_x__fid_int_start_y	= 0x0001008A,
	.fid_int_offset_y__fid_ext_start_x	= 0x01AC0106,
	.fid_ext_start_y__fid_ext_offset_y	= 0x01060006,
	.tvdetgp_int_start_stop_x		= 0x00140001,
	.tvdetgp_int_start_stop_y		= 0x00010001,
	.gen_ctrl				= 0x00FF0000,
	.output_control				= 0x0000000D,
	.dac_b__dac_c				= 0x00000000
};

/*
 * Configure Timings for DVI D
 */
static const struct panel_config dvid_cfg = {
	.timing_h	= 0x0ff03f31, /* Horizontal timing */
	.timing_v	= 0x01400504, /* Vertical timing */
	.pol_freq	= 0x00007028, /* Pol Freq */
	.divisor	= 0x00010006, /* 72Mhz Pixel Clock */
	.lcd_size	= 0x02ff03ff, /* 1024x768 */
	.panel_type	= 0x01, /* TFT */
	.data_lines	= 0x03, /* 24 Bit RGB */
	.load_mode	= 0x02, /* Frame Mode */
	.panel_color	= DVI_BEAGLE_ORANGE_COL, /* ORANGE */
	.gfx_format	= GFXFORMAT_RGB24_UNPACKED,
};

static const struct panel_config dvid_cfg_xm = {
	.timing_h	= 0x1a4024c9, /* Horizontal timing */
	.timing_v	= 0x02c00509, /* Vertical timing */
	.pol_freq	= 0x00007028, /* Pol Freq */
	.divisor	= 0x00010001, /* 96MHz Pixel Clock */
	.lcd_size	= 0x02ff03ff, /* 1024x768 */
	.panel_type	= 0x01, /* TFT */
	.data_lines	= 0x03, /* 24 Bit RGB */
	.load_mode	= 0x02, /* Frame Mode */
	.panel_color	= DVI_BEAGLE_ORANGE_COL, /* ORANGE */
	.gfx_format	= GFXFORMAT_RGB24_UNPACKED,
};
#endif