/* * (C) Copyright 2004-2011 * Texas Instruments, * * Author : * Sunil Kumar * Shashi Ranjan * * Derived from Beagle Board and 3430 SDP code by * Richard Woodruff * Syed Mohammed Khasim * * * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include #include #include #include #include #include #include "h1.h" #include #include DECLARE_GLOBAL_DATA_PTR; /* * Routine: board_init * Description: Early hardware init. */ int board_init(void) { gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ /* board id for Linux */ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_H1; /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); return 0; } #ifdef CONFIG_SPL_BUILD /* * Routine: get_board_mem_timings * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ void get_board_mem_timings(struct board_sdrc_timings *timings) { int pop_mfr, pop_id; /* * We need to identify what PoP memory is on the board so that * we know what timings to use. If we can't identify it then * we know it's an xM. To map the ID values please see nand_ids.c */ identify_nand_chip(&pop_mfr, &pop_id); timings->mr = MICRON_V_MR_165; /* 128MB DDR */ timings->mcfg = MICRON_V_MCFG_200(256 << 20); timings->ctrla = MICRON_V_ACTIMA_200; timings->ctrlb = MICRON_V_ACTIMB_200; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } #endif /* * Routine: misc_init_r * Description: Configure board specific parts */ int misc_init_r(void) { struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE; //MUX_BEAGLE_XM(); dieid_num_r(); return 0; } /* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the * hardware. Many pins need to be moved from protect to primary * mode. */ void set_muxconf_regs(void) { MUX_EVM(); }