From 302e52e0b1d4c7f994991709d0cb6c3ea612cdb5 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 5 Sep 2008 14:40:29 -0500 Subject: Fix compiler warning in mpc8xxx ddr code ctrl_regs.c: In function 'compute_fsl_memctl_config_regs': ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function ctrl_regs.c:523: note: 'caslat' was declared here Add a warning in DDR1 case if cas_latency isn't a value we know about. Signed-off-by: Kumar Gala Acked-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/mpc8xxx/ddr/ctrl_regs.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'cpu/mpc8xxx/ddr/ctrl_regs.c') diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index ca675512a..e6c2a5ce7 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -520,7 +520,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, unsigned int wr; /* Write Recovery */ unsigned int dll_res; /* DLL Reset */ unsigned int mode; /* Normal=0 or Test=1 */ - unsigned int caslat; /* CAS# latency */ + unsigned int caslat = 0;/* CAS# latency */ /* BT: Burst Type (0=Sequential, 1=Interleaved) */ unsigned int bt; unsigned int bl; /* BL: Burst Length */ @@ -572,7 +572,9 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, 0x6, /* 2.5 clocks */ 0x3 /* 3.0 clocks */ }; - caslat = mode_caslat_table[cas_latency - 1]; + caslat = mode_caslat_table[cas_latency - 1]; + } else { + printf("Warning: unknown cas_latency %d\n", cas_latency); } #elif defined(CONFIG_FSL_DDR2) caslat = cas_latency; -- cgit v1.2.3-70-g09d2 From dbbbb3abeff325855cae76e33d69d5665631443f Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 3 Oct 2008 12:36:39 -0400 Subject: Make DDR interleaving mode work correctly Fix some bugs: 1. Correctly set intlv_ctl in cs_config. 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled. 3. Set base_address and total memory for each ddr controller in memory controller interleaving mode. Signed-off-by: Haiying Wang --- cpu/mpc8xxx/ddr/ctrl_regs.c | 61 +++++++++++++++++++++++++++++++++-------- cpu/mpc8xxx/ddr/main.c | 5 ++++ include/asm-ppc/fsl_ddr_sdram.h | 12 ++++++++ 3 files changed, 66 insertions(+), 12 deletions(-) (limited to 'cpu/mpc8xxx/ddr/ctrl_regs.c') diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index e6c2a5ce7..629714116 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -95,16 +95,10 @@ static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr, col_bits_cs_n = dimm_params[i/2].n_col_addr - 8; } - /* FIXME: intlv_en, intlv_ctl only on CS0_CONFIG */ - if (i != 0) { - intlv_en = 0; - intlv_ctl = 0; - } - ddr->cs[i].config = (0 | ((cs_n_en & 0x1) << 31) | ((intlv_en & 0x3) << 29) - | ((intlv_en & 0xf) << 24) + | ((intlv_ctl & 0xf) << 24) | ((ap_n_en & 0x1) << 23) /* XXX: some implementation only have 1 bit starting at left */ @@ -874,8 +868,13 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { phys_size_t sa = 0; phys_size_t ea = 0; - if (popts->ba_intlv_ctl && i > 0) { - /* Don't set up boundaries if bank interleaving */ + + if (popts->ba_intlv_ctl && (i > 0) && + ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) { + /* Don't set up boundaries for other CS + * other than CS0, if bank interleaving + * is enabled and not CS2+CS3 interleaved. + */ break; } @@ -894,7 +893,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, * on each controller is twice the amount present on * each controller. */ - ea = (2 * common_dimm->total_mem >> dbw_cap_adj) - 1; + unsigned long long rank_density + = dimm_params[0].capacity; + ea = (2 * (rank_density >> dbw_cap_adj)) - 1; } else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) { /* @@ -906,8 +907,44 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, * controller needs to be programmed into its * respective CS0_BNDS. */ - sa = common_dimm->base_address; - ea = sa + (common_dimm->total_mem >> dbw_cap_adj) - 1; + unsigned long long rank_density + = dimm_params[i/2].rank_density; + switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS + * needs to be set. + */ + sa = common_dimm->base_address; + ea = sa + (4 * (rank_density >> dbw_cap_adj))-1; + break; + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS + * and CS2_CNDS need to be set. + */ + if (!(i&1)) { + sa = dimm_params[i/2].base_address; + ea = sa + (i * (rank_density >> + dbw_cap_adj)) - 1; + } + break; + case FSL_DDR_CS0_CS1: + /* CS0+CS1 interleaving, CS0_CNDS needs + * to be set + */ + sa = common_dimm->base_address; + ea = sa + (2 * (rank_density >> dbw_cap_adj))-1; + break; + case FSL_DDR_CS2_CS3: + /* CS2+CS3 interleaving*/ + if (i == 2) { + sa = dimm_params[i/2].base_address; + ea = sa + (2 * (rank_density >> + dbw_cap_adj)) - 1; + } + break; + default: /* No bank(chip-select) interleaving */ + break; + } } else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) { /* diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c index c340d569f..d26c5c5c2 100644 --- a/cpu/mpc8xxx/ddr/main.c +++ b/cpu/mpc8xxx/ddr/main.c @@ -179,6 +179,7 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, if (*memctl_interleaving) { phys_addr_t addr; + phys_size_t total_mem_per_ctlr = 0; /* * If interleaving between memory controllers, @@ -197,14 +198,18 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { addr = 0; + pinfo->common_timing_params[i].base_address = + (phys_addr_t)addr; for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { unsigned long long cap = pinfo->dimm_params[i][j].capacity; pinfo->dimm_params[i][j].base_address = addr; addr += (phys_addr_t)(cap >> dbw_cap_adj[i]); + total_mem_per_ctlr += cap >> dbw_cap_adj[i]; } } + pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr; } else { /* * Simple linear assignment if memory diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 8adde3424..c1ea7cd6b 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -36,6 +36,18 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #endif +/* define bank(chip select) interleaving mode */ +#define FSL_DDR_CS0_CS1 0x40 +#define FSL_DDR_CS2_CS3 0x20 +#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) +#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) + +/* define memory controller interleaving mode */ +#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 +#define FSL_DDR_PAGE_INTERLEAVING 0x1 +#define FSL_DDR_BANK_INTERLEAVING 0x2 +#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 + /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { struct { -- cgit v1.2.3-70-g09d2 From 1f293b417ac6ab8e317ca2b770377ca93edf2370 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 3 Oct 2008 12:37:26 -0400 Subject: Add debug information for DDR controller registers Signed-off-by: Haiying Wang --- cpu/mpc8xxx/ddr/ctrl_regs.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'cpu/mpc8xxx/ddr/ctrl_regs.c') diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 629714116..1783e927a 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -111,6 +111,7 @@ static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr, | ((row_bits_cs_n & 0x7) << 8) | ((col_bits_cs_n & 0x7) << 0) ); + debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); } /* Chip Select Configuration 2 (CSn_CONFIG_2) */ @@ -120,6 +121,7 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) unsigned int pasr_cfg = 0; /* Partial array self refresh config */ ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); + debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); } /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ @@ -190,6 +192,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, | ((ext_caslat & 0x1) << 12) | ((cntl_adj & 0x7) << 0) ); + debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); } /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ @@ -257,6 +260,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, | ((acttoact_mclk & 0x07) << 4) | ((wrtord_mclk & 0x07) << 0) ); + debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); } /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ @@ -313,6 +317,7 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((cke_pls & 0x7) << 6) | ((four_act & 0x1f) << 0) ); + debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); } /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ @@ -379,6 +384,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, | ((mem_halt & 0x1) << 1) | ((bi & 0x1) << 0) ); + debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); } /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ @@ -443,6 +449,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((rcw_en & 0x1) << 2) | ((md_en & 0x1) << 0) ); + debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); } /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ @@ -455,6 +462,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr) | ((esdmode2 & 0xFFFF) << 16) | ((esdmode3 & 0xFFFF) << 0) ); + debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); } /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ @@ -474,6 +482,7 @@ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, | ((refint & 0xFFFF) << 16) | ((bstopre & 0x3FFF) << 0) ); + debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); } /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ @@ -607,6 +616,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, | ((esdmode & 0xFFFF) << 16) | ((sdmode & 0xFFFF) << 0) ); + debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); } @@ -669,6 +679,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr) | ((wwt & 0xf) << 16) | (dll_lock & 0x3) ); + debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); } /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ @@ -685,6 +696,7 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) | ((wodt_on & 0xf) << 12) | ((wodt_off & 0xf) << 8) ); + debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); } /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ @@ -992,6 +1004,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, | ((ea & 0xFFF) << 0) /* ending address MSB */ ); + debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); set_csn_config(i, ddr, popts, dimm_params); set_csn_config_2(i, ddr); } -- cgit v1.2.3-70-g09d2