From e1be0d25ecf494ae81245ca438738ba839d6329b Mon Sep 17 00:00:00 2001 From: Poonam_Aggrwal-b10812 Date: Sun, 4 Jan 2009 08:46:38 +0530 Subject: 32bit BUg fix for DDR2 on 8572 This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 --- cpu/mpc85xx/ddr-gen3.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'cpu/mpc85xx/ddr-gen3.c') diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index a2b45c571..8dc2b3ac5 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -19,6 +19,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, { unsigned int i; volatile ccsr_ddr_t *ddr; + u32 temp_sdram_cfg; switch (ctrl_num) { case 0: @@ -78,6 +79,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + /* Do not enable the memory */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg); + temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg); /* * For 8572 DDR1 erratum - DDR controller may enter illegal state * when operatiing in 32-bit bus mode with 4-beat bursts, @@ -99,7 +104,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, udelay(200); asm volatile("sync;isync"); - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); + /* Let the controller go */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ while (in_be32(&ddr->sdram_cfg_2) & 0x10) { -- cgit v1.2.3-70-g09d2