From 82fd1f8da9add2d74532cf78d224485f0042d00d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:53:01 -0500 Subject: 85xx: Add support for e500mc cache stashing The e500mc core supports the ability to stash into the L1 or L2 cache, however we need to uniquely identify the caches with an id. We use the following equation to set the various stash-ids: 32 + coreID*2 + 0(L1) or 1(L2) The 0 (for L1) or 1 (for L2) matches the CT field used be various cache control instructions. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'cpu/mpc85xx/cpu_init.c') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 0041a60df..16ce82c99 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -357,6 +357,11 @@ int cpu_init_r(void) while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) ; +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L2 (1) */ + mtspr(SPRN_L2CSR1, (32 + 1)); +#endif + /* enable the cache */ mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); -- cgit v1.2.3-70-g09d2