From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/mcf5445x/cpu_init.c | 56 ++++++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 28 deletions(-) (limited to 'cpu/mcf5445x/cpu_init.c') diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index 51a9e9037..50b4561f3 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -62,42 +62,42 @@ void cpu_init_f(void) GPIO_PAR_FBCTL_TS_TS; #if !defined(CONFIG_CF_SBF) -#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) - fbcs->csar0 = CFG_CS0_BASE; - fbcs->cscr0 = CFG_CS0_CTRL; - fbcs->csmr0 = CFG_CS0_MASK; +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; #endif #endif -#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) /* Latch chipselect */ - fbcs->csar1 = CFG_CS1_BASE; - fbcs->cscr1 = CFG_CS1_CTRL; - fbcs->csmr1 = CFG_CS1_MASK; + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; #endif -#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) - fbcs->csar2 = CFG_CS2_BASE; - fbcs->cscr2 = CFG_CS2_CTRL; - fbcs->csmr2 = CFG_CS2_MASK; +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; #endif -#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) - fbcs->csar3 = CFG_CS3_BASE; - fbcs->cscr3 = CFG_CS3_CTRL; - fbcs->csmr3 = CFG_CS3_MASK; +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; #endif -#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) - fbcs->csar4 = CFG_CS4_BASE; - fbcs->cscr4 = CFG_CS4_CTRL; - fbcs->csmr4 = CFG_CS4_MASK; +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; #endif -#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) - fbcs->csar5 = CFG_CS5_BASE; - fbcs->cscr5 = CFG_CS5_CTRL; - fbcs->csmr5 = CFG_CS5_MASK; +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; #endif #ifdef CONFIG_FSL_I2C @@ -113,11 +113,11 @@ void cpu_init_f(void) int cpu_init_r(void) { #ifdef CONFIG_MCFRTC - volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE); + volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; - rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF; - rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF; + rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; + rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; #endif return (0); @@ -128,7 +128,7 @@ void uart_port_conf(void) volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CFG_UART_PORT) { + switch (CONFIG_SYS_UART_PORT) { case 0: gpio->par_uart = (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); -- cgit v1.2.3-70-g09d2 From f3962d3f574e5a1cffacd4e9bc48713060a2a314 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Tue, 21 Oct 2008 13:47:54 +0000 Subject: ColdFire: Relocate FEC's GPIO and mii functions protocols Place FEC pin assignments in cpu_init.c from platform's mii.c Signed-off-by: TsiChung Liew --- cpu/mcf523x/cpu_init.c | 24 ++++++++++++- cpu/mcf52x2/cpu_init.c | 78 +++++++++++++++++++++++++++++++++++++++++ cpu/mcf532x/cpu_init.c | 25 ++++++++++++- cpu/mcf5445x/cpu_init.c | 34 +++++++++++++++++- cpu/mcf547x_8x/cpu_init.c | 27 ++++++++++++++ include/asm-m68k/fec.h | 12 +++++++ include/asm-m68k/fsl_mcdmafec.h | 9 ----- 7 files changed, 197 insertions(+), 12 deletions(-) (limited to 'cpu/mcf5445x/cpu_init.c') diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c index 652094485..3c04fd413 100644 --- a/cpu/mcf523x/cpu_init.c +++ b/cpu/mcf523x/cpu_init.c @@ -27,9 +27,14 @@ #include #include - #include +#if defined(CONFIG_CMD_NET) +#include +#include +#include +#endif + /* * Breath some life into the CPU... * @@ -143,3 +148,20 @@ void uart_port_conf(void) break; } } + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO); + } else { + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); + } + + return 0; +} +#endif diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 32ad6cd1a..18308c8a7 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -36,6 +36,12 @@ #include #include +#if defined(CONFIG_CMD_NET) +#include +#include +#include +#endif + #ifndef CONFIG_M5272 /* Only 5272 Flexbus chipselect is different from the rest */ void init_fbcs(void) @@ -207,6 +213,19 @@ void uart_port_conf(void) break; } } + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C); + } else { + } + + return 0; +} +#endif /* CONFIG_CMD_NET */ #endif #if defined(CONFIG_M5272) @@ -309,6 +328,22 @@ void uart_port_conf(void) break; } } + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | + GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | + GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | + GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; + } else { + } + return 0; +} +#endif /* CONFIG_CMD_NET */ #endif /* #if defined(CONFIG_M5272) */ #if defined(CONFIG_M5275) @@ -372,6 +407,35 @@ void uart_port_conf(void) break; } } + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + struct fec_info_s *info = (struct fec_info_s *) dev->priv; + volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO; + + if (setclear) { + /* Enable Ethernet pins */ + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + gpio->par_feci2c |= 0x0F00; + gpio->par_fec0hl |= 0xC0; + } else { + gpio->par_feci2c |= 0x00A0; + gpio->par_fec1hl |= 0xC0; + } + } else { + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + gpio->par_feci2c &= ~0x0F00; + gpio->par_fec0hl &= ~0xC0; + } else { + gpio->par_feci2c &= ~0x00A0; + gpio->par_fec1hl &= ~0xC0; + } + } + + return 0; +} +#endif /* CONFIG_CMD_NET */ #endif /* #if defined(CONFIG_M5275) */ #if defined(CONFIG_M5282) @@ -469,6 +533,20 @@ void uart_port_conf(void) break; } } + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + MCFGPIO_PASPAR |= 0x0F00; + MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; + } else { + MCFGPIO_PASPAR &= 0xF0FF; + MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR; + } + return 0; +} +#endif /* CONFIG_CMD_NET */ #endif #if defined(CONFIG_M5249) diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c index d348e29a1..39be11f09 100644 --- a/cpu/mcf532x/cpu_init.c +++ b/cpu/mcf532x/cpu_init.c @@ -27,9 +27,14 @@ #include #include - #include +#if defined(CONFIG_CMD_NET) +#include +#include +#include +#endif + /* * Breath some life into the CPU... * @@ -139,3 +144,21 @@ void uart_port_conf(void) break; } } + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; + } else { + gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); + } + return 0; +} +#endif diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index 50b4561f3..7e04e32c7 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -27,10 +27,15 @@ #include #include - #include #include +#if defined(CONFIG_CMD_NET) +#include +#include +#include +#endif + /* * Breath some life into the CPU... * @@ -139,3 +144,30 @@ void uart_port_conf(void) break; } } + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + struct fec_info_s *info = (struct fec_info_s *)dev->priv; + + if (setclear) { + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) + gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; + else + gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; + } else { + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) + gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; + else + gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; + } + return 0; +} +#endif diff --git a/cpu/mcf547x_8x/cpu_init.c b/cpu/mcf547x_8x/cpu_init.c index 9a0e04083..1ba57835e 100644 --- a/cpu/mcf547x_8x/cpu_init.c +++ b/cpu/mcf547x_8x/cpu_init.c @@ -29,6 +29,12 @@ #include #include +#if defined(CONFIG_CMD_NET) +#include +#include +#include +#endif + /* * Breath some life into the CPU... * @@ -130,3 +136,24 @@ void uart_port_conf(void) *pscsicr &= 0xF8; } + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + struct fec_info_dma *info = (struct fec_info_dma *)dev->priv; + + if (setclear) { + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) + gpio->par_feci2cirq |= 0xF000; + else + gpio->par_feci2cirq |= 0x0FC0; + } else { + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) + gpio->par_feci2cirq &= 0x0FFF; + else + gpio->par_feci2cirq &= 0xF03F; + } + return 0; +} +#endif diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h index e63959902..49311e596 100644 --- a/include/asm-m68k/fec.h +++ b/include/asm-m68k/fec.h @@ -351,4 +351,16 @@ typedef struct fec { #define FEC_RESET_DELAY 100 #define FEC_RX_TOUT 100 +int fecpin_setclear(struct eth_device *dev, int setclear); + +#ifdef CONFIG_SYS_DISCOVER_PHY +void __mii_init(void); +uint mii_send(uint mii_cmd); +int mii_discover_phy(struct eth_device *dev); +int mcffec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +int mcffec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +#endif + #endif /* fec_h */ diff --git a/include/asm-m68k/fsl_mcdmafec.h b/include/asm-m68k/fsl_mcdmafec.h index 82da5931e..7e540567a 100644 --- a/include/asm-m68k/fsl_mcdmafec.h +++ b/include/asm-m68k/fsl_mcdmafec.h @@ -164,13 +164,4 @@ struct fec_info_dma { #define FIFO_CTRL_UFMASK (0x00100000) #define FIFO_CTRL_OFMASK (0x00080000) -int fecpin_setclear(struct eth_device *dev, int setclear); -void mii_init(void); -uint mii_send(uint mii_cmd); -int mii_discover_phy(struct eth_device *dev); -int mcffec_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int mcffec_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - #endif /* fsl_mcdmafec_h */ -- cgit v1.2.3-70-g09d2