From c9b2feafaaf0a7998347589f9a29f7169873af6e Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 28 Feb 2012 23:28:07 +0000 Subject: powerpc/p2041rdb: add NAND and NAND boot support New P2041RDB board will add a NAND chip, so add support for NAND and NAND boot. Signed-off-by: Shaohui Xie Signed-off-by: Andy Fleming --- boards.cfg | 1 + 1 file changed, 1 insertion(+) (limited to 'boards.cfg') diff --git a/boards.cfg b/boards.cfg index 3cf75c315..1986da9cd 100644 --- a/boards.cfg +++ b/boards.cfg @@ -742,6 +742,7 @@ P2020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freesca P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH P2041RDB powerpc mpc85xx p2041rdb freescale +P2041RDB_NAND powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SECURE_BOOT P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -- cgit v1.2.3-70-g09d2 From 5ffa88eca78b7260788b898b69b7d17d9508268f Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Thu, 8 Mar 2012 00:33:17 +0000 Subject: powerpc/corenet_ds: Master module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang Signed-off-by: Shaohui Xie --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 ++-- arch/powerpc/cpu/mpc8xxx/srio.c | 51 +++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_srio.h | 61 +++++++++++++++++++++++++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 3 ++ boards.cfg | 3 ++ include/configs/corenet_ds.h | 18 +++++++++++ 6 files changed, 140 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/include/asm/fsl_srio.h (limited to 'boards.cfg') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2e4a06c35..97a7fe1b9 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include "mp.h" #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -48,8 +49,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern void srio_init(void); - #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -443,6 +442,9 @@ skip_l2: #ifdef CONFIG_SYS_SRIO srio_init(); +#ifdef CONFIG_SRIOBOOT_MASTER + srio_boot_master(); +#endif #endif #if defined(CONFIG_MP) diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index e46d32806..77fa32f69 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -21,6 +21,10 @@ #include #include #include +#include + +#define SRIO_PORT_ACCEPT_ALL 0x10000001 +#define SRIO_IB_ATMU_AR 0x80f55000 #if defined(CONFIG_FSL_CORENET) #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 @@ -84,3 +88,50 @@ void srio_init(void) setbits_be32(&gur->devdisr, _DEVDISR_RMU); } } + +#ifdef CONFIG_SRIOBOOT_MASTER +void srio_boot_master(void) +{ + struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + + /* set port accept-all */ + out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr, + SRIO_PORT_ACCEPT_ALL); + + debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", + CONFIG_SRIOBOOT_MASTER_PORT); + /* configure inbound window5 for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window 5 for slave's image; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + + /* configure inbound window4 for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window 4 for slave's image; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); +} +#endif diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h new file mode 100644 index 000000000..e4cd9b654 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -0,0 +1,61 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FSL_SRIO_H_ +#define _FSL_SRIO_H_ + +enum atmu_size { + ATMU_SIZE_4K = 0xb, + ATMU_SIZE_8K, + ATMU_SIZE_16K, + ATMU_SIZE_32K, + ATMU_SIZE_64K, + ATMU_SIZE_128K, + ATMU_SIZE_256K, + ATMU_SIZE_512K, + ATMU_SIZE_1M, + ATMU_SIZE_2M, + ATMU_SIZE_4M, + ATMU_SIZE_8M, + ATMU_SIZE_16M, + ATMU_SIZE_32M, + ATMU_SIZE_64M, + ATMU_SIZE_128M, + ATMU_SIZE_256M, + ATMU_SIZE_512M, + ATMU_SIZE_1G, + ATMU_SIZE_2G, + ATMU_SIZE_4G, + ATMU_SIZE_8G, + ATMU_SIZE_16G, + ATMU_SIZE_32G, + ATMU_SIZE_64G, +}; + +#define atmu_size_mask(sz) (__ilog2_u64(sz) - 1) +#define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1)) + +extern void srio_init(void); +#ifdef CONFIG_SRIOBOOT_MASTER +extern void srio_boot_master(void); +#endif +#endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index c4d241b7e..632e3c166 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2507,6 +2507,7 @@ struct ccsr_rman { #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 +#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) @@ -2580,6 +2581,8 @@ struct ccsr_rman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) #define CONFIG_SYS_FSL_FM2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) +#define CONFIG_SYS_FSL_SRIO_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) #define CONFIG_SYS_PCI1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) diff --git a/boards.cfg b/boards.cfg index 1986da9cd..4821dfb27 100644 --- a/boards.cfg +++ b/boards.cfg @@ -751,6 +751,7 @@ P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER P3060QDS powerpc mpc85xx p3060qds freescale P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT @@ -758,11 +759,13 @@ P4080DS powerpc mpc85xx corenet_ds freesca P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER P5020DS powerpc mpc85xx corenet_ds freescale P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index fd8291e85..a31ccc294 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -374,6 +374,24 @@ #endif #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +/* + * SRIOBOOT - MASTER + */ +#ifdef CONFIG_SRIOBOOT_MASTER +/* master port for srioboot*/ +#define CONFIG_SRIOBOOT_MASTER_PORT 0 +/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */ +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull +#endif + /* * eSPI - Enhanced SPI */ -- cgit v1.2.3-70-g09d2 From 292dc6c50107a5bef1084c53c36598dde177a116 Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Thu, 8 Mar 2012 00:33:18 +0000 Subject: powerpc/corenet_ds: Slave module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. 5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode locally. For the slave module, need to finish these processes: 1. Set the boot location to SRIO1 or SRIO2 by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot. 4. Slave's u-boot image should be generated specifically by make xxxx_SRIOBOOT_SLAVE_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. Signed-off-by: Liu Gang Signed-off-by: Shaohui Xie --- README | 6 ++++++ board/freescale/common/p_corenet/law.c | 9 +++++++++ board/freescale/common/p_corenet/tlb.c | 9 +++++++++ boards.cfg | 3 +++ drivers/net/fm/fm.c | 2 ++ include/configs/corenet_ds.h | 28 ++++++++++++++++++++++++++++ 6 files changed, 57 insertions(+) (limited to 'boards.cfg') diff --git a/README b/README index 43074cf65..da1510561 100644 --- a/README +++ b/README @@ -3462,6 +3462,12 @@ within that device. Specifies that QE/FMAN firmware is located on the primary SPI device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device. +- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE + Specifies that QE/FMAN firmware is located in the remote (master) + memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which + can be mapped from slave TLB->slave LAW->slave SRIO outbound window + ->master inbound window->master LAW->the ucode address in master's + NOR flash. Building the Software: ====================== diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 09ef5615d..1fbab4d96 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -48,6 +48,15 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif +#ifdef CONFIG_SRIOBOOT_SLAVE +#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0) + SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), +#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1) + SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), +#endif +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 6a0026a2c..a8c8b3c3a 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIOBOOT_SLAVE) + /* + * SRIOBOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR, + CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), #else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/boards.cfg b/boards.cfg index 4821dfb27..7194e0896 100644 --- a/boards.cfg +++ b/boards.cfg @@ -752,6 +752,7 @@ P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER +P3041DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P3060QDS powerpc mpc85xx p3060qds freescale P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT @@ -760,12 +761,14 @@ P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER +P4080DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P5020DS powerpc mpc85xx corenet_ds freescale P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER +P5020DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 0b8c33fb7..49c74c278 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -408,6 +408,8 @@ int fm_init_common(int index, struct ccsr_fman *reg) /* flush cache after read */ flush_cache((ulong)addr, cnt * 512); } +#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) + void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; #endif /* Upload the Fman microcode if it's present */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index a31ccc294..8ff1408c6 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -33,6 +33,15 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif +#ifdef CONFIG_SRIOBOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -392,6 +401,15 @@ #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull #endif +/* + * SRIOBOOT - SLAVE + */ +#ifdef CONFIG_SRIOBOOT_SLAVE +/* slave port for srioboot */ +#define CONFIG_SRIOBOOT_SLAVE_PORT0 +/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */ +#endif + /* * eSPI - Enhanced SPI */ @@ -512,6 +530,16 @@ #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIOBOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO outbound window->master inbound window->master LAW-> + * the ucode address in master's NOR flash. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_QE_FMAN_FW_ADDR NULL #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 -- cgit v1.2.3-70-g09d2