From 2ad6b513b31070bd0c003792ed1c3e7f5d740357 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 31 Oct 2006 18:44:42 -0600 Subject: mpc83xx: Add support for the MPC8349E-mITX PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi --- board/mpc8349itx/Makefile | 48 +++++ board/mpc8349itx/config.mk | 33 +++ board/mpc8349itx/mpc8349itx.c | 461 ++++++++++++++++++++++++++++++++++++++++++ board/mpc8349itx/pci.c | 337 ++++++++++++++++++++++++++++++ board/mpc8349itx/u-boot.lds | 120 +++++++++++ 5 files changed, 999 insertions(+) create mode 100644 board/mpc8349itx/Makefile create mode 100644 board/mpc8349itx/config.mk create mode 100644 board/mpc8349itx/mpc8349itx.c create mode 100644 board/mpc8349itx/pci.c create mode 100644 board/mpc8349itx/u-boot.lds (limited to 'board/mpc8349itx') diff --git a/board/mpc8349itx/Makefile b/board/mpc8349itx/Makefile new file mode 100644 index 000000000..31bcdb864 --- /dev/null +++ b/board/mpc8349itx/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mpc8349itx/config.mk b/board/mpc8349itx/config.mk new file mode 100644 index 000000000..2e113118b --- /dev/null +++ b/board/mpc8349itx/config.mk @@ -0,0 +1,33 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC8349ITX +# + +TEXT_BASE = 0xFEF00000 + +ifneq ($(OBJTREE),$(SRCTREE)) +# We are building u-boot in a separate directory, use generated +# .lds script from OBJTREE directory. +LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds +endif diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c new file mode 100644 index 000000000..9a5cbec85 --- /dev/null +++ b/board/mpc8349itx/mpc8349itx.c @@ -0,0 +1,461 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_PCI +#include +#include +#endif + +#ifdef CONFIG_SPD_EEPROM +#include +#else +#include +#endif + +#ifndef CONFIG_SPD_EEPROM +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + u32 ddr_size; /* The size of RAM, in bytes */ + u32 ddr_size_log2 = 0; + + for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { + if (ddr_size & 1) { + return -1; + } + ddr_size_log2++; + } + + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff; + + /* Only one CS0 for DDR */ + im->ddr.csbnds[0].csbnds = 0x0000000f; + im->ddr.cs_config[0] = CFG_DDR_CONFIG; + + debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); + debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); + + debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); + debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); + + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ + im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR; + im->ddr.sdram_mode = + (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); + im->ddr.sdram_interval = + (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << + SDRAM_INTERVAL_BSTOPRE_SHIFT); + im->ddr.sdram_clk_cntl = + DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; + + udelay(200); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); + debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); + debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); + debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); + debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); + + return CFG_DDR_SIZE; +} +#endif + +#ifdef CONFIG_PCI +/* + * Initialize PCI Devices, report devices found + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc83xxmitx_config_table[] = { + { + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + 0x0f, + PCI_ANY_ID, + pci_cfgfunc_config_device, + { + PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} + }, + {} +} +#endif + +volatile static struct pci_controller hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxmitx_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxmitx_config_table, +#endif + } +}; +#endif /* CONFIG_PCI */ + +/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. +*/ + +void sdram_init(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile lbus83xx_t *lbc = &immap->lbus; + +#if defined(CFG_BR2_PRELIM) \ + && defined(CFG_OR2_PRELIM) \ + && defined(CFG_LBLAWBAR2_PRELIM) \ + && defined(CFG_LBLAWAR2_PRELIM) \ + && !defined(CONFIG_COMPACT_FLASH) + + uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; + + puts("\n SDRAM on Local Bus: "); + print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers, already done in cpu_init.c + */ + + /*setup mtrpt, lsrt and lbcr for LB bus */ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + + /* + * Configure the SDRAM controller Machine Mode register. + */ + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + + lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733; precharge all the banks */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2; /*0x48636733; auto refresh */ + asm("sync"); + *sdram_addr = 0xff; /*1 time*/ + udelay(100); + *sdram_addr = 0xff; /*2 times*/ + udelay(100); + *sdram_addr = 0xff; /*3 times*/ + udelay(100); + *sdram_addr = 0xff; /*4 times*/ + udelay(100); + *sdram_addr = 0xff; /*5 times*/ + udelay(100); + *sdram_addr = 0xff; /*6 times*/ + udelay(100); + *sdram_addr = 0xff; /*7 times*/ + udelay(100); + *sdram_addr = 0xff; /*8 times*/ + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + +#else + puts("SDRAM on Local Bus is NOT available!\n"); + +#ifdef CFG_BR2_PRELIM + lbc->bank[2].br = CFG_BR2_PRELIM; + lbc->bank[2].or = CFG_OR2_PRELIM; +#endif + +#ifdef CFG_BR3_PRELIM + lbc->bank[3].br = CFG_BR3_PRELIM; + lbc->bank[3].or = CFG_OR3_PRELIM; +#endif +#endif +} + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + u32 msize = 0; +#ifdef CONFIG_DDR_ECC + volatile ddr83xx_t *ddr = &im->ddr; +#endif + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; +#ifdef CONFIG_SPD_EEPROM + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + +#ifdef CONFIG_DDR_ECC + if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) + /* Unlike every other board, on the 83xx spd_sdram() returns + megabytes instead of just bytes. That's why we need to + multiple by 1MB when calling ddr_enable_ecc(). */ + ddr_enable_ecc(msize * 1048576); +#endif + + /* + * Initialize SDRAM if it is on local bus. + */ + sdram_init(); + puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ +#ifdef CONFIG_HARD_I2C + u8 i2c_data; +#endif + + puts("Board: Freescale MPC8349E-mITX"); + +#ifdef CONFIG_HARD_I2C + i2c_set_bus_num(I2C_BUS_2); + if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == + 0) + printf(" %u.%u (PCF8475A)", (i2c_data & 0x02) >> 1, + i2c_data & 0x01); + else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) + == 0) + printf(" %u.%u (PCF8475)", (i2c_data & 0x02) >> 1, + i2c_data & 0x01); + else + printf(" ?.?"); +#endif + + puts("\n"); + + return 0; +} + +/** + * Implement a work-around for a hardware problem with compact + * flash. + * + * Program the UPM if compact flash is enabled. + */ +int misc_init_f(void) +{ + volatile u32 *vsc7385_cpuctrl; + + /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up + default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That + means it is 0 when the IRQ is not active. This makes the wire-AND + logic always assert IRQ7 to CPU even if there is no request from the + switch. Since the compact flash and the switch share the same IRQ, + the Linux kernel will think that the compact flash is requesting irq + and get stuck when it tries to clear the IRQ. Thus we need to set + the L2_IRQ0 and L2_IRQ1 to active low. + + The following code sets the L1_IRQ and L2_IRQ polarity to active low. + Without this code, compact flash will not work in Linux because + unlike U-Boot, Linux uses the IRQ, so this code is necessary if we + don't enable compact flash for U-Boot. + */ + + vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); + *vsc7385_cpuctrl |= 0x0c; + +#ifdef CONFIG_COMPACT_FLASH + /* UPM Table Configuration Code */ + static uint UPMATable[] = { + 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, + 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, + 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 + }; + volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile lbus83xx_t *lbus = &immap->lbus; + + lbus->bank[3].br = CFG_BR3_PRELIM; + lbus->bank[3].or = CFG_OR3_PRELIM; + + /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, + GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 + */ + lbus->mamr = 0x08404440; + + upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); + + puts("UPMA: Configured for compact flash\n"); +#endif + + return 0; +} + +/** + * Make sure the EEPROM has the HRCW correctly programmed. + * Make sure the RTC is correctly programmed. + * + * The MPC8349E-mITX can be configured to load the HRCW from + * EEPROM instead of flash. This is controlled via jumpers + * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all + * jumpered), but if they're set to 001 or 010, then the HRCW is + * read from the "I2C EEPROM". + * + * This function makes sure that the I2C EEPROM is programmed + * correctly. + */ +int misc_init_r(void) +{ + int rc = 0; + +#ifdef CONFIG_HARD_I2C + + uchar orig_bus = i2c_get_bus_num();; + +#ifdef CFG_I2C_RTC_ADDR + char ds1339_data[17]; +#endif + +#ifdef CFG_I2C_EEPROM_ADDR + static u8 eeprom_data[] = /* HRCW data */ + { + 0xaa, 0x55, 0xaa, + 0x7c, 0x02, 0x40, 0x05, 0x04, 0x00, 0x00, + 0x7c, 0x02, 0x41, 0xb4, 0x60, 0xa0, 0x00, + }; + + u8 data[sizeof(eeprom_data)]; + + i2c_set_bus_num(I2C_BUS_1); + + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { + if (memcmp(data, eeprom_data, sizeof(data)) != 0) { + if (i2c_write + (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data, + sizeof(eeprom_data)) != 0) { + puts("Failure writing the HRCW to EEPROM via I2C.\n"); + rc = 1; + } + } + } else { + puts("Failure reading the HRCW from EEPROM via I2C.\n"); + rc = 1; + } +#endif + +#ifdef CFG_I2C_RTC_ADDR + i2c_set_bus_num(I2C_BUS_2); + + if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) + == 0) { + + /* Work-around for MPC8349E-mITX bug #13601. + If the RTC does not contain valid register values, the DS1339 + Linux driver will not work. + */ + + /* Make sure status register bits 6-2 are zero */ + ds1339_data[0x0f] &= ~0x7c; + + /* Check for a valid day register value */ + ds1339_data[0x03] &= ~0xf8; + if (ds1339_data[0x03] == 0) { + ds1339_data[0x03] = 1; + } + + /* Check for a valid date register value */ + ds1339_data[0x04] &= ~0xc0; + if ((ds1339_data[0x04] == 0) || + ((ds1339_data[0x04] & 0x0f) > 9) || + (ds1339_data[0x04] >= 0x32)) { + ds1339_data[0x04] = 1; + } + + /* Check for a valid month register value */ + ds1339_data[0x05] &= ~0x60; + + if ((ds1339_data[0x05] == 0) || + ((ds1339_data[0x05] & 0x0f) > 9) || + ((ds1339_data[0x05] >= 0x13) + && (ds1339_data[0x05] <= 0x19))) { + ds1339_data[0x05] = 1; + } + + /* Enable Oscillator and rate select */ + ds1339_data[0x0e] = 0x1c; + + /* Work-around for MPC8349E-mITX bug #13330. + Ensure that the RTC control register contains the value 0x1c. + This affects SATA performance. + */ + + if (i2c_write + (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, + sizeof(ds1339_data))) { + puts("Failure writing to the RTC via I2C.\n"); + rc = 1; + } + } else { + puts("Failure reading from the RTC via I2C.\n"); + rc = 1; + } +#endif + + i2c_set_bus_num(orig_bus); +#endif + + return rc; +} diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c new file mode 100644 index 000000000..247b3a6ec --- /dev/null +++ b/board/mpc8349itx/pci.c @@ -0,0 +1,337 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc8349itx_config_table[] = { + { + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_IDSEL_NUMBER, + PCI_ANY_ID, + pci_cfgfunc_config_device, + { + PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} + }, + {} +}; +#endif + +static struct pci_controller pci_hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349itx_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349itx_config_table, +#endif + } +}; + +/************************************************************************** + * pci_init_board() + * + * NOTICE: PCI2 is not currently supported + * + */ +void pci_init_board(void) +{ + volatile immap_t *immr; + volatile clk83xx_t *clk; + volatile law83xx_t *pci_law; + volatile pot83xx_t *pci_pot; + volatile pcictrl83xx_t *pci_ctrl; + volatile pciconf83xx_t *pci_conf; + u8 reg8; + u16 reg16; + u32 reg32; + u32 dev; + struct pci_controller *hose; + + immr = (immap_t *) CFG_IMMRBAR; + clk = (clk83xx_t *) & immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + + hose = &pci_hose[0]; + + /* + * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode + */ + + reg32 = clk->occr; + udelay(2000); + +#ifdef CONFIG_HARD_I2C + i2c_set_bus_num(I2C_BUS_2); + /* Read the PCI_M66EN jumper setting */ + if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || + (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { + if (reg8 & I2C_8574_PCI66) + clk->occr = 0xff000000; /* 66 MHz PCI */ + else + clk->occr = 0xff600001; /* 33 MHz PCI */ + } else { + clk->occr = 0xff600001; /* 33 MHz PCI */ + } +#else + clk->occr = 0xff000000; /* 66 MHz PCI */ +#endif + + udelay(2000); + + /* + * Release PCI RST Output signal + */ + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + +#ifdef CONFIG_MPC83XX_PCI2 + pci_ctrl[1].gcr = 0; + udelay(2000); + pci_ctrl[1].gcr = 1; +#endif + + /* We need to wait at least a 1sec based on PCI specs */ + { + int i; + + for (i = 0; i < 1000; i++) + udelay(1000); + } + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI1 mem space - prefetch */ + pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = + POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI1 IO space */ + pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* PCI1 mmio - non-prefetch mem space */ + pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MMIO_BASE, + CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); + +#ifdef CONFIG_MPC83XX_PCI2 + hose = &pci_hose[1]; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI2 mem space - prefetch */ + pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[3].pocmr = + POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & + POCMR_CM_MASK); + + /* PCI2 IO space */ + pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[4].pocmr = + POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* PCI2 mmio - non-prefetch mem space */ + pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[5].pocmr = + POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[1].pitar1 = 0x0; + pci_ctrl[1].pibar1 = 0x0; + pci_ctrl[1].piebar1 = 0x0; + pci_ctrl[1].piwar1 = + PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | + (__ilog2(gd->ram_size) - 1); + + hose->first_busno = pci_hose[0].last_busno + 1; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MMIO_BASE, + CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMRBAR + 0x8380), (CFG_IMMRBAR + 0x8384)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +#endif +} + +#endif /* CONFIG_PCI */ diff --git a/board/mpc8349itx/u-boot.lds b/board/mpc8349itx/u-boot.lds new file mode 100644 index 000000000..f044c0f00 --- /dev/null +++ b/board/mpc8349itx/u-boot.lds @@ -0,0 +1,120 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) -- cgit v1.2.3-70-g09d2 From 988833324a7fda482c8ac3ca23eb539f8232e404 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 31 Oct 2006 19:14:41 -0600 Subject: mpc83xx: Fix PCI, USB, bootargs for MPC8349E-mITX PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006092142000015 "Add support for the MPC8349E-mITX 1/2" 2) DNX#2006092142000024 "Add support for the MPC8349E-mITX 2/2" CHANGELOG: * For the 8349E-mITX, fix some size values in pci_init_board(), enable the clock for the 2nd USB board (Linux kernel will hang otherwise), and fix the CONFIG_BOOTARGS macro. Signed-off-by: Timur Tabi --- board/mpc8349itx/pci.c | 19 +++++++------------ include/configs/MPC8349ITX.h | 19 +++++++++++-------- 2 files changed, 18 insertions(+), 20 deletions(-) (limited to 'board/mpc8349itx') diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c index 247b3a6ec..acac185d5 100644 --- a/board/mpc8349itx/pci.c +++ b/board/mpc8349itx/pci.c @@ -150,7 +150,7 @@ void pci_init_board(void) pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; /* * Configure PCI Outbound Translation Windows @@ -159,18 +159,17 @@ void pci_init_board(void) /* PCI1 mem space - prefetch */ pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = - POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); + pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M; /* PCI1 IO space */ pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; /* PCI1 mmio - non-prefetch mem space */ pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); + pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; /* * Configure PCI Inbound Translation Windows @@ -250,21 +249,17 @@ void pci_init_board(void) /* PCI2 mem space - prefetch */ pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[3].pocmr = - POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & - POCMR_CM_MASK); + pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M; /* PCI2 IO space */ pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[4].pocmr = - POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M; /* PCI2 mmio - non-prefetch mem space */ pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[5].pocmr = - POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); + pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M; /* * Configure PCI Inbound Translation Windows diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index aed350fe0..20f3c6d39 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -604,7 +604,7 @@ /* System IO Config */ #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ -#define CFG_SICRL SICRL_LDP_A +#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) #define CFG_HID0_INIT 0x000000000 @@ -701,7 +701,7 @@ #define CONFIG_SERVERIP 10.82.48.106 #define CONFIG_GATEWAYIP 10.82.19.254 #define CONFIG_NETMASK 255.255.252.0 - +#define CONFIG_NETDEV eth0 #define CONFIG_HOSTNAME mpc8349emitx #define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs @@ -722,16 +722,19 @@ #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ #endif -#define CONFIG_BOOTARGS \ - "root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=ttyS0,$baudrate $othbootargs" - #define XMK_STR(x) #x #define MK_STR(x) XMK_STR(x) +#define CONFIG_BOOTARGS \ + "root=/dev/nfs rw" \ + " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ + " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ + MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ + MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ + " console=ttyS0," MK_STR(CONFIG_BAUDRATE) + #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \ -- cgit v1.2.3-70-g09d2 From 9ca880a250870a7d55754291b5591d2b5fe89b54 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 31 Oct 2006 21:23:16 -0600 Subject: mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and MPC8360EMDS This patch also adds an improved I2C set_speed(), which handles all clock frequencies. Signed-off-by: Timur Tabi --- board/mpc8349emds/pci.c | 8 +- board/mpc8349itx/mpc8349itx.c | 6 +- board/mpc8349itx/pci.c | 2 +- board/mpc8360emds/pci.c | 11 ++- cpu/mpc83xx/i2c.c | 214 +++++++++++++++++++++++++----------------- include/asm-ppc/i2c.h | 10 +- include/configs/MPC8349ITX.h | 2 +- include/configs/TQM834x.h | 2 +- include/i2c.h | 8 +- 9 files changed, 154 insertions(+), 109 deletions(-) (limited to 'board/mpc8349itx') diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c index a916245ae..93827f11d 100644 --- a/board/mpc8349emds/pci.c +++ b/board/mpc8349emds/pci.c @@ -75,10 +75,8 @@ pib_init(void) /* Switch temporarily to I2C bus #2 */ orig_i2c_bus = i2c_get_bus_num(); - if(orig_i2c_bus != I2C_BUS_2) - i2c_set_bus_num(I2C_BUS_2); - - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + if(orig_i2c_bus != 2) + i2c_set_bus_num(2); val8 = 0; i2c_write(0x23, 0x6, 1, &val8, 1); @@ -124,7 +122,7 @@ pib_init(void) printf("PCI2: 32-bit on PMC3\n"); #endif /* Reset to original I2C bus */ - if(orig_i2c_bus != I2C_BUS_2) + if(orig_i2c_bus != 2) i2c_set_bus_num(orig_i2c_bus); } diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 9a5cbec85..466264588 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -259,7 +259,7 @@ int checkboard(void) puts("Board: Freescale MPC8349E-mITX"); #ifdef CONFIG_HARD_I2C - i2c_set_bus_num(I2C_BUS_2); + i2c_set_bus_num(2); if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) printf(" %u.%u (PCF8475A)", (i2c_data & 0x02) >> 1, @@ -379,7 +379,7 @@ int misc_init_r(void) u8 data[sizeof(eeprom_data)]; - i2c_set_bus_num(I2C_BUS_1); + i2c_set_bus_num(1); if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { if (memcmp(data, eeprom_data, sizeof(data)) != 0) { @@ -397,7 +397,7 @@ int misc_init_r(void) #endif #ifdef CFG_I2C_RTC_ADDR - i2c_set_bus_num(I2C_BUS_2); + i2c_set_bus_num(2); if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) == 0) { diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c index acac185d5..cf07020b6 100644 --- a/board/mpc8349itx/pci.c +++ b/board/mpc8349itx/pci.c @@ -105,7 +105,7 @@ void pci_init_board(void) udelay(2000); #ifdef CONFIG_HARD_I2C - i2c_set_bus_num(I2C_BUS_2); + i2c_set_bus_num(2); /* Read the PCI_M66EN jumper setting */ if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index 880b2ecc3..64ea50979 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -198,8 +198,11 @@ void pci_init_board(void) * Assign PIB PMC slot to desired PCI bus */ - mpc83xx_i2c = (i2c_t *) (CFG_IMMRBAR + CFG_I2C2_OFFSET); - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + /* Switch temporarily to I2C bus #2 */ + orig_i2c_bus = i2c_get_bus_num(); + + if(orig_i2c_bus != 2) + i2c_set_bus_num(2); val8 = 0; i2c_write(0x23, 0x6, 1, &val8, 1); @@ -227,6 +230,10 @@ void pci_init_board(void) i2c_write(0x27, 0x3, 1, &val8, 1); asm("eieio"); + /* Reset to original I2C bus */ + if(orig_i2c_bus != 2) + i2c_set_bus_num(orig_i2c_bus); + /* * Release PCI RST Output signal */ diff --git a/cpu/mpc83xx/i2c.c b/cpu/mpc83xx/i2c.c index fc89fb1e2..ce7849161 100644 --- a/cpu/mpc83xx/i2c.c +++ b/cpu/mpc83xx/i2c.c @@ -47,75 +47,121 @@ DECLARE_GLOBAL_DATA_PTR; -/* Three I2C bus speeds are supported here (50kHz, 100kHz - * and 400kHz). It should be easy to add more. Note that - * the maximum bus speed for I2C bus 1 is CSB/3, while I2C - * bus 2 can go as high as CSB. - * Typical values for CSB are 266MHz and 200MHz. */ - - /* 50kH 100kHz 400kHz */ -static const uchar speed_map_266[][3] = - {{0x2e, 0x2a, 0x20}, /* base 88MHz */ - {0x34, 0x30, 0x28}}; /* base 266 MHz */ - -static const uchar speed_map_200[][3] = - {{0x2c, 0x28, 0x20}, /* base 66 MHz */ - {0x33, 0x2f, 0x26}}; /* base 200 MHz */ - /* Initialize the bus pointer to whatever one the SPD EEPROM is on. * Default is bus 1. This is necessary because the DDR initialization * runs from ROM, and we can't switch buses because we can't modify * the i2c_dev variable. Everything gets straightened out once i2c_init * is called from RAM. */ -#if defined CFG_SPD_BUS_NUM -static i2c_t *i2c_dev = CFG_SPD_BUS_NUM; +#ifndef CFG_SPD_BUS_NUM +#define CFG_SPD_BUS_NUM 1 +#endif + +static unsigned int i2c_bus_num = CFG_SPD_BUS_NUM; + +#if CFG_SPD_BUS_NUM == 1 +static volatile i2c_t *i2c_dev = I2C_1; #else -static i2c_t *i2c_dev = I2C_1; +static volatile i2c_t *i2c_dev = I2C_2; #endif -static uchar busNum = I2C_BUS_1 ; -static int bus_speed[2] = {0, 0}; +static int i2c_bus_speed[2] = {0, 0}; -static int set_speed(int speed) +/* + * Map the frequency divider to the FDR. This data is taken from table 17-5 + * of the MPC8349EA reference manual, with duplicates removed. + */ +static struct { + unsigned int divider; + u8 fdr; +} i2c_speed_map[] = { - uchar value; - const uchar *spdPtr; - - /* Global data contains maximum I2C bus 1 speed, which is CSB/3 */ - if(gd->i2c_clk == 88000000) - { - spdPtr = speed_map_266[busNum]; - } - else if(gd->i2c_clk == 66000000) - { - spdPtr = speed_map_200[busNum]; - } - else - { - printf("Max I2C bus speed %d not supported\n", gd->i2c_clk); - return -1; - } - - switch(speed) - { - case 50000: - value = *(spdPtr + 0); - break; - case 100000: - value = *(spdPtr + 1); - break; - case 400000: - value = *(spdPtr + 2); - break; - default: - printf("I2C bus speed %d not supported\n", speed); - return -2; - } - /* set clock */ - writeb(value, &i2c_dev->fdr); - bus_speed[busNum] = speed; - return 0; + {0, 0x20}, + {256, 0x20}, + {288, 0x21}, + {320, 0x22}, + {352, 0x23}, + {384, 0x24}, + {416, 0x01}, + {448, 0x25}, + {480, 0x02}, + {512, 0x26}, + {576, 0x27}, + {640, 0x28}, + {704, 0x05}, + {768, 0x29}, + {832, 0x06}, + {896, 0x2A}, + {1024, 0x2B}, + {1152, 0x08}, + {1280, 0x2C}, + {1536, 0x2D}, + {1792, 0x2E}, + {1920, 0x0B}, + {2048, 0x2F}, + {2304, 0x0C}, + {2560, 0x30}, + {3072, 0x31}, + {3584, 0x32}, + {3840, 0x0F}, + {4096, 0x33}, + {4608, 0x10}, + {5120, 0x34}, + {6144, 0x35}, + {7168, 0x36}, + {7680, 0x13}, + {8192, 0x37}, + {9216, 0x14}, + {10240, 0x38}, + {12288, 0x39}, + {14336, 0x3A}, + {15360, 0x17}, + {16384, 0x3B}, + {18432, 0x18}, + {20480, 0x3C}, + {24576, 0x3D}, + {28672, 0x3E}, + {30720, 0x1B}, + {32768, 0x3F}, + {36864, 0x1C}, + {40960, 0x1D}, + {49152, 0x1E}, + {61440, 0x1F}, + {-1, 0x1F} +}; + +#define NUM_I2C_SPEEDS (sizeof(i2c_speed_map) / sizeof(i2c_speed_map[0])) + +static int set_speed(unsigned int speed) +{ + unsigned long i2c_clk; + unsigned int divider, i; + u8 fdr = 0x3F; + + i2c_clk = (i2c_bus_num == 2) ? gd->i2c2_clk : gd->i2c1_clk; + + divider = i2c_clk / speed; + + /* Scan i2c_speed_map[] for the closest matching divider.*/ + + for (i = 0; i < NUM_I2C_SPEEDS-1; i++) { + /* Locate our divider in between two entries in i2c_speed_map[] */ + if ((divider >= i2c_speed_map[i].divider) && + (divider <= i2c_speed_map[i+1].divider)) { + /* Which one is closer? */ + if ((divider - i2c_speed_map[i].divider) < (i2c_speed_map[i+1].divider - divider)) { + fdr = i2c_speed_map[i].fdr; + } else { + fdr = i2c_speed_map[i+1].fdr; + } + break; + } + } + + writeb(fdr, &i2c_dev->fdr); + i2c_bus_speed[i2c_bus_num - 1] = speed; + + return 0; } @@ -125,16 +171,16 @@ static void _i2c_init(int speed, int slaveadd) writeb(0x00 , &i2c_dev->cr); /* set clock */ - writeb(speed, &i2c_dev->fdr); + set_speed(speed); /* set default filter */ - writeb(0x10,&i2c_dev->dfsrr); + writeb(IC2_FDR,&i2c_dev->dfsrr); /* write slave address */ writeb(slaveadd, &i2c_dev->adr); /* clear status register */ - writeb(0x00, &i2c_dev->sr); + writeb(I2C_CR_MTX, &i2c_dev->sr); /* start I2C controller */ writeb(I2C_CR_MEN, &i2c_dev->cr); @@ -142,19 +188,19 @@ static void _i2c_init(int speed, int slaveadd) void i2c_init(int speed, int slaveadd) { - /* Set both interfaces to the same speed and slave address */ - /* Note: This function gets called twice - before and after - * relocation to RAM. The first time it's called, we are unable - * to change buses, so whichever one 'i2c_dev' was initialized to - * gets set twice. When run from RAM both buses get set properly */ - - i2c_set_bus_num(I2C_BUS_1); - _i2c_init(speed, slaveadd); -#ifdef CFG_I2C2_OFFSET - i2c_set_bus_num(I2C_BUS_2); - _i2c_init(speed, slaveadd); - i2c_set_bus_num(I2C_BUS_1); -#endif /* CFG_I2C2_OFFSET */ + /* Set both interfaces to the same speed and slave address */ + /* Note: This function gets called twice - before and after + * relocation to RAM. The first time it's called, we are unable + * to change buses, so whichever one 'i2c_dev' was initialized to + * gets set twice. When run from RAM both buses get set properly */ + + i2c_set_bus_num(1); + _i2c_init(speed, slaveadd); +#ifdef CFG_I2C2_OFFSET + i2c_set_bus_num(2); + _i2c_init(speed, slaveadd); + i2c_set_bus_num(1); +#endif /* CFG_I2C2_OFFSET */ } static __inline__ int @@ -340,38 +386,38 @@ void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) i2c_write (i2c_addr, reg, 1, &val, 1); } -int i2c_set_bus_num(uchar bus) +int i2c_set_bus_num(unsigned int bus) { - if(bus == I2C_BUS_1) + if(bus == 1) { i2c_dev = I2C_1; } #ifdef CFG_I2C2_OFFSET - else if(bus == I2C_BUS_2) + else if(bus == 2) { i2c_dev = I2C_2; } -#endif /* CFG_I2C2_OFFSET */ +#endif else { return -1; } - busNum = bus; + i2c_bus_num = bus; return 0; } -int i2c_set_bus_speed(int speed) +int i2c_set_bus_speed(unsigned int speed) { return set_speed(speed); } -uchar i2c_get_bus_num(void) +unsigned int i2c_get_bus_num(void) { - return busNum; + return i2c_bus_num; } -int i2c_get_bus_speed(void) +unsigned int i2c_get_bus_speed(void) { - return bus_speed[busNum]; + return i2c_bus_speed[i2c_bus_num - 1]; } #endif /* CONFIG_HARD_I2C */ diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h index baf9d9a26..8afdda2ce 100644 --- a/include/asm-ppc/i2c.h +++ b/include/asm-ppc/i2c.h @@ -79,12 +79,6 @@ typedef struct i2c #endif #define I2C_TIMEOUT (CFG_HZ/4) -enum I2C_BUS_NUM -{ - I2C_BUS_1 = 0, - I2C_BUS_2, -}; - #ifndef CFG_IMMRBAR #error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h #endif @@ -96,9 +90,9 @@ enum I2C_BUS_NUM #define I2C_1 ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET)) /* Optional support for second I2C bus */ -#ifdef CFG_I2C2_OFFSET +#ifdef CFG_I2C2_OFFSET #define I2C_2 ((i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET)) -#endif /* CFG_I2C2_OFFSET */ +#endif /* CFG_I2C2_OFFSET */ #define I2C_READ 1 #define I2C_WRITE 0 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 20f3c6d39..2fbc73618 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -81,7 +81,7 @@ #define CONFIG_I2C_CMD_TREE #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 -#define CFG_SPD_BUS_NUM I2C_2 +#define CFG_SPD_BUS_NUM 2 #define CFG_I2C_8574_ADDR1 0x20 /* I2C2, PCF8574 */ #define CFG_I2C_8574_ADDR2 0x21 /* I2C2, PCF8574 */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index f0e49007d..727094b20 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -36,8 +36,8 @@ */ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC834X 1 /* MPC834X specific */ +#define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_TQM834X 1 /* TQM834X board specific */ /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ diff --git a/include/i2c.h b/include/i2c.h index 97e006163..a8f729afe 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -97,7 +97,7 @@ void i2c_reg_write(uchar chip, uchar reg, uchar val); * Returns: 0 on success, not 0 on failure * */ -int i2c_set_bus_num(uchar bus); +int i2c_set_bus_num(unsigned int bus); /* * i2c_get_bus_num: @@ -105,7 +105,7 @@ int i2c_set_bus_num(uchar bus); * Returns index of currently active I2C bus. Zero-based. */ -uchar i2c_get_bus_num(void); +unsigned int i2c_get_bus_num(void); /* * i2c_set_bus_speed: @@ -117,7 +117,7 @@ uchar i2c_get_bus_num(void); * Returns: 0 on success, not 0 on failure * */ -int i2c_set_bus_speed(int); +int i2c_set_bus_speed(unsigned int); /* * i2c_get_bus_speed: @@ -125,6 +125,6 @@ int i2c_set_bus_speed(int); * Returns speed of currently active I2C bus in Hz */ -int i2c_get_bus_speed(void); +unsigned int i2c_get_bus_speed(void); #endif /* _I2C_H_ */ -- cgit v1.2.3-70-g09d2 From bf0b542d6773a5a1cbce77691f009b06d9aeb57d Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 1 Nov 2006 00:10:40 -0600 Subject: mpc83xx: add OF_FLAT_TREE bits to 83xx boards add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and STDOUT_PATH configuration bits to mpc8349emds, mpc8349itx, and mpc8360emds board code. redo environment to use bootm with the fdtaddr for booting ARCH=powerpc kernels by default, and provide default fdtaddr values. --- board/mpc8349emds/mpc8349emds.c | 24 +++++++++++++++++++ board/mpc8349emds/pci.c | 22 ++++++++++++++++++ board/mpc8349itx/mpc8349itx.c | 23 +++++++++++++++++++ board/mpc8349itx/pci.c | 22 ++++++++++++++++++ board/mpc8360emds/mpc8360emds.c | 23 +++++++++++++++++++ board/mpc8360emds/pci.c | 19 +++++++++++++++ include/configs/MPC8349EMDS.h | 51 +++++++++++++++++++++++++++++++++++++---- include/configs/MPC8349ITX.h | 45 ++++++++++++++++++++++++++++++------ include/configs/MPC8360EMDS.h | 36 ++++++++++++++++++++++------- 9 files changed, 245 insertions(+), 20 deletions(-) (limited to 'board/mpc8349itx') diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index 6b3dedcbd..ed7b71d08 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -33,6 +33,10 @@ #if defined(CONFIG_SPD_EEPROM) #include #endif +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif + int fixed_sdram(void); void sdram_init(void); @@ -564,3 +568,23 @@ U_BOOT_CMD( " - re-inits memory" ); #endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c index 93827f11d..908be5754 100644 --- a/board/mpc8349emds/pci.c +++ b/board/mpc8349emds/pci.c @@ -385,4 +385,26 @@ pci_init_board(void) } +#ifdef CONFIG_OF_FLAT_TREE +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[0].first_busno; + p[1] = pci_hose[0].last_busno; + } + +#ifdef CONFIG_MPC83XX_PCI2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[1].first_busno; + p[1] = pci_hose[1].last_busno; + } +#endif +} +#endif /* CONFIG_OF_FLAT_TREE */ #endif /* CONFIG_PCI */ diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 466264588..9fce973df 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -37,6 +37,9 @@ #else #include #endif +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif #ifndef CONFIG_SPD_EEPROM /************************************************************************* @@ -459,3 +462,23 @@ int misc_init_r(void) return rc; } + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c index cf07020b6..b4637bc8c 100644 --- a/board/mpc8349itx/pci.c +++ b/board/mpc8349itx/pci.c @@ -330,3 +330,25 @@ void pci_init_board(void) } #endif /* CONFIG_PCI */ +#ifdef CONFIG_OF_FLAT_TREE +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[0].first_busno; + p[1] = pci_hose[0].last_busno; + } + +#ifdef CONFIG_MPC83XX_PCI2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[1].first_busno; + p[1] = pci_hose[1].last_busno; + } +#endif +} +#endif /* CONFIG_OF_FLAT_TREE */ diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index 5eadcd39e..5bbaa5cf2 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -28,6 +28,9 @@ #else #include #endif +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif const qe_iop_conf_t qe_iop_conf_tab[] = { /* GETH1 */ @@ -628,3 +631,23 @@ U_BOOT_CMD(ecc, 4, 0, do_ecc, " - writes pattern with word access, generates error\n" " - disables injects\n" " - re-inits memory"); #endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index 64ea50979..c81e7a64e 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -234,6 +234,10 @@ void pci_init_board(void) if(orig_i2c_bus != 2) i2c_set_bus_num(orig_i2c_bus); + /* Reset to original I2C bus */ + if(orig_i2c_bus != 2) + i2c_set_bus_num(orig_i2c_bus); + /* * Release PCI RST Output signal */ @@ -298,4 +302,19 @@ void pci_init_board(void) hose->last_busno = pci_hose_scan(hose); } #endif /* CONFIG_PCISLAVE */ + +#ifdef CONFIG_OF_FLAT_TREE +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p != NULL) { + p[0] = hose[0].first_busno; + p[1] = hose[0].last_busno; + } +} +#endif /* CONFIG_OF_FLAT_TREE */ #endif /* CONFIG_PCI */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 4d5ad5719..e68c41acc 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -35,6 +35,7 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ #define CONFIG_MPC834X 1 /* MPC834X family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ @@ -59,6 +60,17 @@ #endif #endif +#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) +#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ +#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ +#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ +#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ +#define CFG_SCCR_VAL ( CFG_SCCR_INIT \ + | CFG_SCCR_TSEC1CM \ + | CFG_SCCR_TSEC2CM \ + | CFG_SCCR_ENCCM \ + | CFG_SCCR_USBCM ) + #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ #define CFG_IMMRBAR 0xE0000000 @@ -308,6 +320,18 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8349@0" +#define OF_SOC "soc8349@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ @@ -668,11 +692,11 @@ #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 #endif -#define CONFIG_IPADDR 192.168.205.5 +#define CONFIG_IPADDR 192.168.1.253 #define CONFIG_HOSTNAME mpc8349emds -#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx -#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage +#define CONFIG_ROOTPATH /nfsroot/rootfs +#define CONFIG_BOOTFILE uImage #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 @@ -705,14 +729,31 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/mpc8349emds/uImage\0" \ "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ "update=protect off fe000000 fe03ffff; " \ "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ "upd=run load;run update\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc8349emds.dtb\0" \ "" +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + #define CONFIG_BOOTCOMMAND "run flash_self" #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 2fbc73618..aaf4d101d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -383,6 +383,17 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8349@0" +#define OF_SOC "soc8349@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" #ifdef CONFIG_PCI @@ -697,17 +708,17 @@ #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #endif -#define CONFIG_IPADDR 10.82.19.159 -#define CONFIG_SERVERIP 10.82.48.106 -#define CONFIG_GATEWAYIP 10.82.19.254 +#define CONFIG_IPADDR 192.168.1.253 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.252.0 #define CONFIG_NETDEV eth0 #define CONFIG_HOSTNAME mpc8349emitx -#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs -#define CONFIG_BOOTFILE timur/uImage +#define CONFIG_ROOTPATH /nfsroot/rootfs +#define CONFIG_BOOTFILE uImage -#define CONFIG_UBOOTPATH timur/u-boot.bin +#define CONFIG_UBOOTPATH u-boot.bin #define CONFIG_UBOOTSTART fe700000 #define CONFIG_UBOOTEND fe77ffff @@ -747,7 +758,27 @@ "cmp.b $loadaddr FEF00000 $filesize\0" \ "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" + "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc8349emitx.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #undef MK_STR diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 330c3073d..feb9cf22f 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -101,6 +101,8 @@ #define CFG_SDRAM_BASE CFG_DDR_BASE #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_83XX_DDR_USES_CS0 + #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ @@ -313,6 +315,18 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8360@0" +#define OF_SOC "soc8360@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ @@ -591,23 +605,29 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ + "ramdiskaddr=1000000\0" \ "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc8349emds.dtb\0" \ + "" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ + "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND -- cgit v1.2.3-70-g09d2 From d239d74b1c937984bc519083a8e7de373a390f06 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 3 Nov 2006 12:00:28 -0600 Subject: mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx tree matches the other 8xxx trees. Signed-off-by: Timur Tabi --- board/mpc8349emds/mpc8349emds.c | 10 +++++----- board/mpc8349emds/pci.c | 10 +++++----- board/mpc8349itx/mpc8349itx.c | 8 ++++---- board/mpc8349itx/pci.c | 6 +++--- board/mpc8360emds/mpc8360emds.c | 10 +++++----- board/mpc8360emds/pci.c | 8 ++++---- board/tqm834x/pci.c | 6 +++--- board/tqm834x/tqm834x.c | 4 ++-- cpu/mpc83xx/cpu.c | 14 +++++++------- cpu/mpc83xx/cpu_init.c | 2 +- cpu/mpc83xx/interrupts.c | 2 +- cpu/mpc83xx/qe_io.c | 2 +- cpu/mpc83xx/spd_sdram.c | 4 ++-- cpu/mpc83xx/speed.c | 2 +- cpu/mpc83xx/start.S | 16 ++++++++-------- drivers/tsec.h | 2 +- include/asm-ppc/i2c.h | 8 ++++---- include/configs/MPC8349EMDS.h | 14 +++++++------- include/configs/MPC8349ITX.h | 10 +++++----- include/configs/MPC8360EMDS.h | 10 +++++----- include/configs/TQM834x.h | 14 +++++++------- lib_ppc/board.c | 2 +- 22 files changed, 82 insertions(+), 82 deletions(-) (limited to 'board/mpc8349itx') diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index ed7b71d08..873bdd01c 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -63,7 +63,7 @@ int board_early_init_f (void) long int initdram (int board_type) { - volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + volatile immap_t *im = (immap_t *)CFG_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) @@ -100,7 +100,7 @@ long int initdram (int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + volatile immap_t *im = (immap_t *)CFG_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; @@ -171,7 +171,7 @@ int checkboard (void) void sdram_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile lbus83xx_t *lbc= &immap->lbus; uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; @@ -249,7 +249,7 @@ void sdram_init(void) */ void ecc_print_status(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); @@ -324,7 +324,7 @@ void ecc_print_status(void) int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; volatile u32 val; u64 *addr, count, val64; diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c index 908be5754..da49a5d80 100644 --- a/board/mpc8349emds/pci.c +++ b/board/mpc8349emds/pci.c @@ -146,7 +146,7 @@ pci_init_board(void) u32 dev; struct pci_controller * hose; - immr = (immap_t *)CFG_IMMRBAR; + immr = (immap_t *)CFG_IMMR; clk = (clk83xx_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -260,8 +260,8 @@ pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMRBAR+0x8300), - (CFG_IMMRBAR+0x8304)); + (CFG_IMMR+0x8300), + (CFG_IMMR+0x8304)); pci_register_hose(hose); @@ -356,8 +356,8 @@ pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMRBAR+0x8380), - (CFG_IMMRBAR+0x8384)); + (CFG_IMMR+0x8380), + (CFG_IMMR+0x8384)); pci_register_hose(hose); diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 9fce973df..c0e72c93e 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -47,7 +47,7 @@ ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + volatile immap_t *im = (immap_t *) CFG_IMMR; u32 ddr_size; /* The size of RAM, in bytes */ u32 ddr_size_log2 = 0; @@ -139,7 +139,7 @@ volatile static struct pci_controller hose[] = { void sdram_init(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile lbus83xx_t *lbc = &immap->lbus; #if defined(CFG_BR2_PRELIM) \ @@ -219,7 +219,7 @@ void sdram_init(void) long int initdram(int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + volatile immap_t *im = (immap_t *) CFG_IMMR; u32 msize = 0; #ifdef CONFIG_DDR_ECC volatile ddr83xx_t *ddr = &im->ddr; @@ -328,7 +328,7 @@ int misc_init_f(void) 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 }; - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile lbus83xx_t *lbus = &immap->lbus; lbus->bank[3].br = CFG_BR3_PRELIM; diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c index b4637bc8c..535cc34af 100644 --- a/board/mpc8349itx/pci.c +++ b/board/mpc8349itx/pci.c @@ -88,7 +88,7 @@ void pci_init_board(void) u32 dev; struct pci_controller *hose; - immr = (immap_t *) CFG_IMMRBAR; + immr = (immap_t *) CFG_IMMR; clk = (clk83xx_t *) & immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -211,7 +211,7 @@ void pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304)); + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); pci_register_hose(hose); @@ -302,7 +302,7 @@ void pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMRBAR + 0x8380), (CFG_IMMRBAR + 0x8384)); + (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384)); pci_register_hose(hose); diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index a9b1d9eb3..ddc1047c6 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -106,7 +106,7 @@ void sdram_init(void); long int initdram(int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + volatile immap_t *im = (immap_t *) CFG_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) @@ -141,7 +141,7 @@ long int initdram(int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + volatile immap_t *im = (immap_t *) CFG_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; @@ -196,7 +196,7 @@ int checkboard(void) void sdram_init(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile lbus83xx_t *lbc = &immap->lbus; uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; @@ -267,7 +267,7 @@ void sdram_init(void) */ void ecc_print_status(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; printf("\nECC mode: %s\n\n", @@ -347,7 +347,7 @@ void ecc_print_status(void) int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; volatile u32 val; u64 *addr; diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index c81e7a64e..a013ba3d4 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -63,7 +63,7 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - immr = (immap_t *) CFG_IMMRBAR; + immr = (immap_t *) CFG_IMMR; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; pci_ctrl = immr->pci_ctrl; @@ -89,7 +89,7 @@ void pci_init_board(void) hose[0].first_busno = 0; hose[0].last_busno = 0xff; pci_setup_indirect(&hose[0], - (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304)); + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); reg16 = 0xff; pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), @@ -131,7 +131,7 @@ void pci_init_board(void) u32 val32; u32 dev; - immr = (immap_t *) CFG_IMMRBAR; + immr = (immap_t *) CFG_IMMR; clk = (clk83xx_t *) & immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -274,7 +274,7 @@ void pci_init_board(void) hose[0].region_count = 4; pci_setup_indirect(&hose[0], - (CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304)); + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); pci_register_hose(hose); diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c index d01277f80..d896f17aa 100644 --- a/board/tqm834x/pci.c +++ b/board/tqm834x/pci.c @@ -78,7 +78,7 @@ pci_init_board(void) u32 reg32; struct pci_controller * hose; - immr = (immap_t *)CFG_IMMRBAR; + immr = (immap_t *)CFG_IMMR; clk = (clk83xx_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -186,8 +186,8 @@ pci_init_board(void) hose->region_count = 3; pci_setup_indirect(hose, - (CFG_IMMRBAR+0x8300), - (CFG_IMMRBAR+0x8304)); + (CFG_IMMR+0x8300), + (CFG_IMMR+0x8304)); pci_register_hose(hose); diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index 41b34cc6f..36d901f09 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -69,7 +69,7 @@ static void set_cs_config(short cs, long config); static void set_ddr_config(void); /* Local variable */ -static volatile immap_t *im = (immap_t *)CFG_IMMRBAR; +static volatile immap_t *im = (immap_t *)CFG_IMMR; /************************************************************************** * Board initialzation after relocation to RAM. Used to detect the number @@ -147,7 +147,7 @@ int checkboard (void) volatile immap_t * immr; u32 w, f; - immr = (immap_t *)CFG_IMMRBAR; + immr = (immap_t *)CFG_IMMR; if (!(immr->reset.rcwh & RCWH_PCIHOST)) { printf("PCI: NOT in host mode..?!\n"); return 0; diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 3d8ca772c..0bd05330d 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -49,7 +49,7 @@ int checkcpu(void) u32 spridr; char buf[32]; - immr = (immap_t *)CFG_IMMRBAR; + immr = (immap_t *)CFG_IMMR; if ((pvr & 0xFFFF0000) != PVR_83xx) { puts("Not MPC83xx Family!!!\n"); @@ -141,7 +141,7 @@ int checkcpu(void) void upmconfig (uint upm, uint *table, uint size) { #if defined(CONFIG_MPC834X) - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile lbus83xx_t *lbus = &immap->lbus; volatile uchar *dummy = NULL; const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */ @@ -188,7 +188,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ulong addr; #endif - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; #ifdef MPC83xx_RESET /* Interrupts and MMU off */ @@ -259,7 +259,7 @@ void watchdog_reset (void) int re_enable = disable_interrupts(); /* Reset the 83xx watchdog */ - volatile immap_t *immr = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immr = (immap_t *) CFG_IMMR; immr->wdt.swsrr = 0x556c; immr->wdt.swsrr = 0xaa39; @@ -311,7 +311,7 @@ ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_DDR_ECC) void dma_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile dma83xx_t *dma = &immap->dma; volatile u32 status = swab32(dma->dmasr0); volatile u32 dmamr0 = swab32(dma->dmamr0); @@ -342,7 +342,7 @@ void dma_init(void) uint dma_check(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile dma83xx_t *dma = &immap->dma; volatile u32 status = swab32(dma->dmasr0); volatile u32 byte_count = swab32(dma->dmabcr0); @@ -361,7 +361,7 @@ uint dma_check(void) int dma_xfer(void *dest, u32 count, void *src) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile dma83xx_t *dma = &immap->dma; volatile u32 dmamr0; diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index eb8f8c042..4f80f4a09 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -219,7 +219,7 @@ void cpu_init_f (volatile immap_t * im) int cpu_init_r (void) { #ifdef CONFIG_QE - uint qe_base = CFG_IMMRBAR + 0x00100000; /* QE immr base */ + uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */ qe_init(qe_base); qe_reset(); #endif diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c index 5a0babfcb..98fccff22 100644 --- a/cpu/mpc83xx/interrupts.c +++ b/cpu/mpc83xx/interrupts.c @@ -45,7 +45,7 @@ struct irq_action { int interrupt_init_cpu (unsigned *decrementer_count) { - volatile immap_t *immr = (immap_t *) CFG_IMMRBAR; + volatile immap_t *immr = (immap_t *) CFG_IMMR; *decrementer_count = (gd->bus_clk / 4) / CFG_HZ; diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c index 11cf3722b..ebe348711 100644 --- a/cpu/mpc83xx/qe_io.c +++ b/cpu/mpc83xx/qe_io.c @@ -34,7 +34,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile immap_t *im = (volatile immap_t *)CFG_IMMRBAR; + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; volatile gpio83xx_t *par_io =(volatile gpio83xx_t *)&im->gpio; /* Caculate pin location and 2bit mask and dir */ diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index b91c6130e..dc8f6790a 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -112,7 +112,7 @@ static void spd_debug(spd_eeprom_t *spd) long int spd_sdram() { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; spd_eeprom_t spd; @@ -562,7 +562,7 @@ static __inline__ unsigned long get_tbms (void) /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */ void ddr_enable_ecc(unsigned int dram_size) { - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ddr83xx_t *ddr= &immap->ddr; unsigned long t_start, t_end; register u64 *p; diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 1e082a786..213e7180a 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -94,7 +94,7 @@ corecnf_t corecnf_tab[] = { */ int get_clocks(void) { - volatile immap_t *im = (immap_t *) CFG_IMMRBAR; + volatile immap_t *im = (immap_t *) CFG_IMMR; u32 pci_sync_in; u8 spmf; u8 clkin_div; diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index c43835c8d..0f27bb61f 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -104,9 +104,9 @@ version_string: #ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined #endif /* CFG_DEFAULT_IMMR */ -#ifndef CFG_IMMRBAR -#define CFG_IMMRBAR CONFIG_DEFAULT_IMMR -#endif /* CFG_IMMRBAR */ +#ifndef CFG_IMMR +#define CFG_IMMR CONFIG_DEFAULT_IMMR +#endif /* CFG_IMMR */ /* * After configuration, a system reset exception is executed using the @@ -152,8 +152,8 @@ boot_cold: /* time t 3 */ nop boot_warm: /* time t 5 */ mfmsr r5 /* save msr contents */ - lis r3, CFG_IMMRBAR@h - ori r3, r3, CFG_IMMRBAR@l + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l stw r3, IMMRBAR(r4) /* Initialise the E300 processor core */ @@ -226,7 +226,7 @@ in_flash: GET_GOT /* initialize GOT access */ /* r3: IMMR */ - lis r3, CFG_IMMRBAR@h + lis r3, CFG_IMMR@h /* run low-level CPU init code (in Flash)*/ bl cpu_init_f @@ -446,7 +446,7 @@ init_e300_core: /* time t 10 */ mtspr SRR1, r3 /* Make SRR1 match MSR */ - lis r3, CFG_IMMRBAR@h + lis r3, CFG_IMMR@h #if defined(CONFIG_WATCHDOG) /* Initialise the Wathcdog values and reset it (if req) */ /*------------------------------------------------------*/ @@ -1201,7 +1201,7 @@ map_flash_by_law1: /* When booting from ROM (Flash or EPROM), clear the */ /* Address Mask in OR0 so ROM appears everywhere */ /*----------------------------------------------------*/ - lis r3, (CFG_IMMRBAR)@h /* r3 <= CFG_IMMRBAR */ + lis r3, (CFG_IMMR)@h /* r3 <= CFG_IMMR */ lwz r4, OR0@l(r3) li r5, 0x7fff /* r5 <= 0x00007FFFF */ and r4, r4, r5 diff --git a/drivers/tsec.h b/drivers/tsec.h index 4aa331c45..cee30037d 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -30,7 +30,7 @@ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) #elif defined(CONFIG_MPC83XX) - #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET) + #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) #endif diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h index 8afdda2ce..37847666d 100644 --- a/include/asm-ppc/i2c.h +++ b/include/asm-ppc/i2c.h @@ -79,19 +79,19 @@ typedef struct i2c #endif #define I2C_TIMEOUT (CFG_HZ/4) -#ifndef CFG_IMMRBAR -#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h +#ifndef CFG_IMMR +#error CFG_IMMR is not defined in /include/configs/${BOARD}.h #endif #ifndef CFG_I2C_OFFSET #error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h #endif -#define I2C_1 ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET)) +#define I2C_1 ((i2c_t*)(CFG_IMMR + CFG_I2C_OFFSET)) /* Optional support for second I2C bus */ #ifdef CFG_I2C2_OFFSET -#define I2C_2 ((i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET)) +#define I2C_2 ((i2c_t*)(CFG_IMMR + CFG_I2C2_OFFSET)) #endif /* CFG_I2C2_OFFSET */ #define I2C_READ 1 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index e68c41acc..4a5b4bc4a 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -73,7 +73,7 @@ #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ -#define CFG_IMMRBAR 0xE0000000 +#define CFG_IMMR 0xE0000000 #undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00000000 /* memtest region */ @@ -311,8 +311,8 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER @@ -345,9 +345,9 @@ /* TSEC */ #define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) #define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) /* USB */ #define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ @@ -641,8 +641,8 @@ #endif /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index aaf4d101d..c74e63a4d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -128,7 +128,7 @@ #endif #endif -#define CFG_IMMRBAR 0xE0000000 /* The IMMR is relocated to here */ +#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ #undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00003000 /* memtest region */ @@ -374,8 +374,8 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) +#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER @@ -653,8 +653,8 @@ #endif /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index feb9cf22f..a8f2df911 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -92,7 +92,7 @@ /* * IMMR new address */ -#define CFG_IMMRBAR 0xE0000000 +#define CFG_IMMR 0xE0000000 /* * DDR Setup @@ -306,8 +306,8 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER @@ -515,9 +515,9 @@ #define CFG_DBAT0U CFG_IBAT0U /* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CFG_IBAT1L (CFG_IMMRBAR | BATL_PP_10 | \ +#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT1U (CFG_IMMRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) #define CFG_DBAT1L CFG_IBAT1L #define CFG_DBAT1U CFG_IBAT1U diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 727094b20..b0b0673cf 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -41,7 +41,7 @@ #define CONFIG_TQM834X 1 /* TQM834X board specific */ /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ -#define CFG_IMMRBAR 0xff400000 +#define CFG_IMMR 0xff400000 /* System clock. Primary input clock when in PCI host mode */ #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ @@ -210,8 +210,8 @@ extern int tqm834x_num_flash_banks; #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) +#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) /* * I2C @@ -248,9 +248,9 @@ extern int tqm834x_num_flash_banks; #define CONFIG_MII #define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET) +#define CFG_TSEC1 (CFG_IMMR + CFG_TSEC1_OFFSET) #define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET) +#define CFG_TSEC2 (CFG_IMMR + CFG_TSEC2_OFFSET) #if defined(CONFIG_TSEC_ENET) @@ -473,8 +473,8 @@ extern int tqm834x_num_flash_banks; #endif /* IMMRBAR */ -#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) +#define CFG_IBAT6L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT6U (CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP) /* FLASH */ #define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 844bbc900..1866dc5cf 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -511,7 +511,7 @@ void board_init_f (ulong bootflag) bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ #endif #if defined(CONFIG_MPC83XX) - bd->bi_immrbar = CFG_IMMRBAR; + bd->bi_immrbar = CFG_IMMR; #endif #if defined(CONFIG_MPC8220) bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ -- cgit v1.2.3-70-g09d2 From be5e61815d5a1fac290ce9c0ef09cb6a8e4288fa Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 3 Nov 2006 19:15:00 -0600 Subject: mpc83xx: Update 83xx to use fsl_i2c.c Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. Added multiple I2C bus support to fsl_i2c.c. Signed-off-by: Timur Tabi --- README | 11 ++ board/mpc8349emds/pci.c | 7 +- board/mpc8349itx/mpc8349itx.c | 47 ++--- board/mpc8349itx/pci.c | 5 +- board/mpc8360emds/pci.c | 13 +- cpu/mpc83xx/Makefile | 2 +- cpu/mpc83xx/cpu.c | 4 +- cpu/mpc83xx/i2c.c | 423 ------------------------------------------ drivers/fsl_i2c.c | 113 +++++++---- include/asm-ppc/i2c.h | 100 ---------- include/asm-ppc/immap_83xx.h | 4 +- include/configs/MPC8349EMDS.h | 1 + include/configs/MPC8349ITX.h | 49 +++-- include/configs/MPC8360EMDS.h | 3 +- include/configs/TQM834x.h | 1 + 15 files changed, 163 insertions(+), 620 deletions(-) delete mode 100644 cpu/mpc83xx/i2c.c delete mode 100644 include/asm-ppc/i2c.h (limited to 'board/mpc8349itx') diff --git a/README b/README index 5c907c8f0..d03862b3e 100644 --- a/README +++ b/README @@ -1342,6 +1342,17 @@ The following options need to be configured: will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 + CFG_SPD_BUS_NUM + + If defined, then this indicates the I2C bus number for DDR SPD. + If not defined, then U-Boot assumes that SPD is on I2C bus 0. + + CONFIG_FSL_I2C + + Define this option if you want to use Freescale's I2C driver in + drivers/fsl_i2c.c. + + - SPI Support: CONFIG_SPI Enables SPI driver (so far only tested with diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c index da49a5d80..bb60e730b 100644 --- a/board/mpc8349emds/pci.c +++ b/board/mpc8349emds/pci.c @@ -74,9 +74,7 @@ pib_init(void) */ /* Switch temporarily to I2C bus #2 */ orig_i2c_bus = i2c_get_bus_num(); - - if(orig_i2c_bus != 2) - i2c_set_bus_num(2); + i2c_set_bus_num(1); val8 = 0; i2c_write(0x23, 0x6, 1, &val8, 1); @@ -122,8 +120,7 @@ pib_init(void) printf("PCI2: 32-bit on PMC3\n"); #endif /* Reset to original I2C bus */ - if(orig_i2c_bus != 2) - i2c_set_bus_num(orig_i2c_bus); + i2c_set_bus_num(orig_i2c_bus); } /************************************************************************** diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index c0e72c93e..097bb370e 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -134,8 +134,7 @@ volatile static struct pci_controller hose[] = { }; #endif /* CONFIG_PCI */ -/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. -*/ +/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. */ void sdram_init(void) { @@ -255,32 +254,12 @@ long int initdram(int board_type) int checkboard(void) { -#ifdef CONFIG_HARD_I2C - u8 i2c_data; -#endif - - puts("Board: Freescale MPC8349E-mITX"); - -#ifdef CONFIG_HARD_I2C - i2c_set_bus_num(2); - if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == - 0) - printf(" %u.%u (PCF8475A)", (i2c_data & 0x02) >> 1, - i2c_data & 0x01); - else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) - == 0) - printf(" %u.%u (PCF8475)", (i2c_data & 0x02) >> 1, - i2c_data & 0x01); - else - printf(" ?.?"); -#endif - - puts("\n"); + puts("Board: Freescale MPC8349E-mITX\n"); return 0; } -/** +/* * Implement a work-around for a hardware problem with compact * flash. * @@ -347,7 +326,7 @@ int misc_init_f(void) return 0; } -/** +/* * Make sure the EEPROM has the HRCW correctly programmed. * Make sure the RTC is correctly programmed. * @@ -366,7 +345,8 @@ int misc_init_r(void) #ifdef CONFIG_HARD_I2C - uchar orig_bus = i2c_get_bus_num();; + unsigned int orig_bus = i2c_get_bus_num();; + u8 i2c_data; #ifdef CFG_I2C_RTC_ADDR char ds1339_data[17]; @@ -381,8 +361,21 @@ int misc_init_r(void) }; u8 data[sizeof(eeprom_data)]; +#endif + printf("Board revision: "); i2c_set_bus_num(1); + if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) + printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); + else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) + printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); + else { + printf("Unknown\n"); + rc = 1; + } + +#ifdef CFG_I2C_EEPROM_ADDR + i2c_set_bus_num(0); if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { if (memcmp(data, eeprom_data, sizeof(data)) != 0) { @@ -400,7 +393,7 @@ int misc_init_r(void) #endif #ifdef CFG_I2C_RTC_ADDR - i2c_set_bus_num(2); + i2c_set_bus_num(1); if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) == 0) { diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c index 535cc34af..e81ad2735 100644 --- a/board/mpc8349itx/pci.c +++ b/board/mpc8349itx/pci.c @@ -29,6 +29,9 @@ #include #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -105,7 +108,7 @@ void pci_init_board(void) udelay(2000); #ifdef CONFIG_HARD_I2C - i2c_set_bus_num(2); + i2c_set_bus_num(1); /* Read the PCI_M66EN jumper setting */ if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index a013ba3d4..15a48dcf4 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -19,7 +19,7 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -200,9 +200,7 @@ void pci_init_board(void) /* Switch temporarily to I2C bus #2 */ orig_i2c_bus = i2c_get_bus_num(); - - if(orig_i2c_bus != 2) - i2c_set_bus_num(2); + i2c_set_bus_num(1); val8 = 0; i2c_write(0x23, 0x6, 1, &val8, 1); @@ -231,12 +229,7 @@ void pci_init_board(void) asm("eieio"); /* Reset to original I2C bus */ - if(orig_i2c_bus != 2) - i2c_set_bus_num(orig_i2c_bus); - - /* Reset to original I2C bus */ - if(orig_i2c_bus != 2) - i2c_set_bus_num(orig_i2c_bus); + i2c_set_bus_num(orig_i2c_bus); /* * Release PCI RST Output signal diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index e254ef98f..4b9dcc818 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -29,7 +29,7 @@ LIB = $(obj)lib$(CPU).a START = start.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - i2c.o spd_sdram.o qe_io.o + spd_sdram.o qe_io.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 0bd05330d..1d169bab2 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -111,7 +111,7 @@ int checkcpu(void) } -/** +/* * Program a UPM with the code supplied in the table. * * The 'dummy' variable is used to increment the MAD. 'dummy' is @@ -137,7 +137,7 @@ int checkcpu(void) * upm: 0=UPMA, 1=UPMB, 2=UPMC * table: Pointer to an array of values to program * size: Number of elements in the array. Must be 64 or less. -*/ + */ void upmconfig (uint upm, uint *table, uint size) { #if defined(CONFIG_MPC834X) diff --git a/cpu/mpc83xx/i2c.c b/cpu/mpc83xx/i2c.c deleted file mode 100644 index ce7849161..000000000 --- a/cpu/mpc83xx/i2c.c +++ /dev/null @@ -1,423 +0,0 @@ -/* - * (C) Copyright 2006 Freescale Semiconductor, Inc. - * - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao - * Adapted for Motorola 85xx chip. - * - * (C) Copyright 2003 - * Gleb Natapov - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk - * - * Hardware I2C driver for MPC107 PCI bridge. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Change log: - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - * 20060601: Dave Liu (daveliu@freescale.com) - * Unified variable names for mpc83xx - */ - -#include -#include -#include - -#ifdef CONFIG_HARD_I2C -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* Initialize the bus pointer to whatever one the SPD EEPROM is on. - * Default is bus 1. This is necessary because the DDR initialization - * runs from ROM, and we can't switch buses because we can't modify - * the i2c_dev variable. Everything gets straightened out once i2c_init - * is called from RAM. */ - -#ifndef CFG_SPD_BUS_NUM -#define CFG_SPD_BUS_NUM 1 -#endif - -static unsigned int i2c_bus_num = CFG_SPD_BUS_NUM; - -#if CFG_SPD_BUS_NUM == 1 -static volatile i2c_t *i2c_dev = I2C_1; -#else -static volatile i2c_t *i2c_dev = I2C_2; -#endif - -static int i2c_bus_speed[2] = {0, 0}; - -/* - * Map the frequency divider to the FDR. This data is taken from table 17-5 - * of the MPC8349EA reference manual, with duplicates removed. - */ -static struct { - unsigned int divider; - u8 fdr; -} i2c_speed_map[] = -{ - {0, 0x20}, - {256, 0x20}, - {288, 0x21}, - {320, 0x22}, - {352, 0x23}, - {384, 0x24}, - {416, 0x01}, - {448, 0x25}, - {480, 0x02}, - {512, 0x26}, - {576, 0x27}, - {640, 0x28}, - {704, 0x05}, - {768, 0x29}, - {832, 0x06}, - {896, 0x2A}, - {1024, 0x2B}, - {1152, 0x08}, - {1280, 0x2C}, - {1536, 0x2D}, - {1792, 0x2E}, - {1920, 0x0B}, - {2048, 0x2F}, - {2304, 0x0C}, - {2560, 0x30}, - {3072, 0x31}, - {3584, 0x32}, - {3840, 0x0F}, - {4096, 0x33}, - {4608, 0x10}, - {5120, 0x34}, - {6144, 0x35}, - {7168, 0x36}, - {7680, 0x13}, - {8192, 0x37}, - {9216, 0x14}, - {10240, 0x38}, - {12288, 0x39}, - {14336, 0x3A}, - {15360, 0x17}, - {16384, 0x3B}, - {18432, 0x18}, - {20480, 0x3C}, - {24576, 0x3D}, - {28672, 0x3E}, - {30720, 0x1B}, - {32768, 0x3F}, - {36864, 0x1C}, - {40960, 0x1D}, - {49152, 0x1E}, - {61440, 0x1F}, - {-1, 0x1F} -}; - -#define NUM_I2C_SPEEDS (sizeof(i2c_speed_map) / sizeof(i2c_speed_map[0])) - -static int set_speed(unsigned int speed) -{ - unsigned long i2c_clk; - unsigned int divider, i; - u8 fdr = 0x3F; - - i2c_clk = (i2c_bus_num == 2) ? gd->i2c2_clk : gd->i2c1_clk; - - divider = i2c_clk / speed; - - /* Scan i2c_speed_map[] for the closest matching divider.*/ - - for (i = 0; i < NUM_I2C_SPEEDS-1; i++) { - /* Locate our divider in between two entries in i2c_speed_map[] */ - if ((divider >= i2c_speed_map[i].divider) && - (divider <= i2c_speed_map[i+1].divider)) { - /* Which one is closer? */ - if ((divider - i2c_speed_map[i].divider) < (i2c_speed_map[i+1].divider - divider)) { - fdr = i2c_speed_map[i].fdr; - } else { - fdr = i2c_speed_map[i+1].fdr; - } - break; - } - } - - writeb(fdr, &i2c_dev->fdr); - i2c_bus_speed[i2c_bus_num - 1] = speed; - - return 0; -} - - -static void _i2c_init(int speed, int slaveadd) -{ - /* stop I2C controller */ - writeb(0x00 , &i2c_dev->cr); - - /* set clock */ - set_speed(speed); - - /* set default filter */ - writeb(IC2_FDR,&i2c_dev->dfsrr); - - /* write slave address */ - writeb(slaveadd, &i2c_dev->adr); - - /* clear status register */ - writeb(I2C_CR_MTX, &i2c_dev->sr); - - /* start I2C controller */ - writeb(I2C_CR_MEN, &i2c_dev->cr); -} - -void i2c_init(int speed, int slaveadd) -{ - /* Set both interfaces to the same speed and slave address */ - /* Note: This function gets called twice - before and after - * relocation to RAM. The first time it's called, we are unable - * to change buses, so whichever one 'i2c_dev' was initialized to - * gets set twice. When run from RAM both buses get set properly */ - - i2c_set_bus_num(1); - _i2c_init(speed, slaveadd); -#ifdef CFG_I2C2_OFFSET - i2c_set_bus_num(2); - _i2c_init(speed, slaveadd); - i2c_set_bus_num(1); -#endif /* CFG_I2C2_OFFSET */ -} - -static __inline__ int -i2c_wait4bus (void) -{ - ulong timeval = get_timer (0); - while (readb(&i2c_dev->sr) & I2C_SR_MBB) { - if (get_timer (timeval) > I2C_TIMEOUT) { - return -1; - } - } - return 0; -} - -static __inline__ int -i2c_wait (int write) -{ - u32 csr; - ulong timeval = get_timer(0); - do { - csr = readb(&i2c_dev->sr); - - if (!(csr & I2C_SR_MIF)) - continue; - - writeb(0x0, &i2c_dev->sr); - - if (csr & I2C_SR_MAL) { - debug("i2c_wait: MAL\n"); - return -1; - } - - if (!(csr & I2C_SR_MCF)) { - debug("i2c_wait: unfinished\n"); - return -1; - } - - if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { - debug("i2c_wait: No RXACK\n"); - return -1; - } - - return 0; - } while (get_timer (timeval) < I2C_TIMEOUT); - - debug("i2c_wait: timed out\n"); - return -1; -} - -static __inline__ int -i2c_write_addr (u8 dev, u8 dir, int rsta) -{ - writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | - (rsta?I2C_CR_RSTA:0), - &i2c_dev->cr); - - writeb((dev << 1) | dir, &i2c_dev->dr); - - if (i2c_wait (I2C_WRITE) < 0) - return 0; - return 1; -} - -static __inline__ int -__i2c_write (u8 *data, int length) -{ - int i; - - writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, - &i2c_dev->cr); - - for (i=0; i < length; i++) { - writeb(data[i], &i2c_dev->dr); - - if (i2c_wait (I2C_WRITE) < 0) - break; - } - return i; -} - -static __inline__ int -__i2c_read (u8 *data, int length) -{ - int i; - - writeb(I2C_CR_MEN | I2C_CR_MSTA | - ((length == 1) ? I2C_CR_TXAK : 0), - &i2c_dev->cr); - - /* dummy read */ - readb(&i2c_dev->dr); - - for (i=0; i < length; i++) { - if (i2c_wait (I2C_READ) < 0) - break; - - /* Generate ack on last next to last byte */ - if (i == length - 2) - writeb(I2C_CR_MEN | I2C_CR_MSTA | - I2C_CR_TXAK, - &i2c_dev->cr); - - /* Generate stop on last byte */ - if (i == length - 1) - writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev->cr); - - data[i] = readb(&i2c_dev->dr); - } - return i; -} - -int -i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8*)&addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - if (i2c_write_addr (dev, I2C_READ, 1) == 0) - goto exit; - - i = __i2c_read (data, length); - - exit: - writeb(I2C_CR_MEN, &i2c_dev->cr); - return !(i == length); -} - -int -i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8*)&addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - i = __i2c_write (data, length); - - exit: - writeb(I2C_CR_MEN, &i2c_dev->cr); - return !(i == length); -} - -int i2c_probe (uchar chip) -{ - int tmp; - - /* - * Try to read the first location of the chip. The underlying - * driver doesn't appear to support sending just the chip address - * and looking for an back. - */ - udelay(10000); - return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); -} - -uchar i2c_reg_read (uchar i2c_addr, uchar reg) -{ - uchar buf[1]; - - i2c_read (i2c_addr, reg, 1, buf, 1); - - return (buf[0]); -} - -void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write (i2c_addr, reg, 1, &val, 1); -} - -int i2c_set_bus_num(unsigned int bus) -{ - if(bus == 1) - { - i2c_dev = I2C_1; - } -#ifdef CFG_I2C2_OFFSET - else if(bus == 2) - { - i2c_dev = I2C_2; - } -#endif - else - { - return -1; - } - i2c_bus_num = bus; - return 0; -} - -int i2c_set_bus_speed(unsigned int speed) -{ - return set_speed(speed); -} - -unsigned int i2c_get_bus_num(void) -{ - return i2c_bus_num; -} - -unsigned int i2c_get_bus_speed(void) -{ - return i2c_bus_speed[i2c_bus_num - 1]; -} -#endif /* CONFIG_HARD_I2C */ diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c index 65c27439e..0e3921348 100644 --- a/drivers/fsl_i2c.c +++ b/drivers/fsl_i2c.c @@ -28,29 +28,49 @@ #include /* HW definitions */ #define I2C_TIMEOUT (CFG_HZ / 4) -#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) +/* Initialize the bus pointer to whatever one the SPD EEPROM is on. + * Default is bus 0. This is necessary because the DDR initialization + * runs from ROM, and we can't switch buses because we can't modify + * the global variables. + */ +#ifdef CFG_SPD_BUS_NUM +static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM; +#else +static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; +#endif + +static volatile struct fsl_i2c *i2c_dev[2] = { + (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET), +#ifdef CFG_I2C2_OFFSET + (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET) +#endif +}; void i2c_init(int speed, int slaveadd) { - /* stop I2C controller */ - writeb(0x0, &I2C->cr); - - /* set clock */ - writeb(0x3f, &I2C->fdr); - - /* set default filter */ - writeb(0x10, &I2C->dfsrr); - - /* write slave address */ - writeb(slaveadd, &I2C->adr); - - /* clear status register */ - writeb(0x0, &I2C->sr); - - /* start I2C controller */ - writeb(I2C_CR_MEN, &I2C->cr); + volatile struct fsl_i2c *dev; + + dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET); + + writeb(0, &dev->cr); /* stop I2C controller */ + writeb(0x3F, &dev->fdr); /* set bus speed */ + writeb(0x3F, &dev->dfsrr); /* set default filter */ + writeb(slaveadd, &dev->adr); /* write slave address */ + writeb(0x0, &dev->sr); /* clear status register */ + writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ + +#ifdef CFG_I2C2_OFFSET + dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET); + + writeb(0, &dev->cr); /* stop I2C controller */ + writeb(0x3F, &dev->fdr); /* set bus speed */ + writeb(0x3F, &dev->dfsrr); /* set default filter */ + writeb(slaveadd, &dev->adr); /* write slave address */ + writeb(0x0, &dev->sr); /* clear status register */ + writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ +#endif /* CFG_I2C2_OFFSET */ } static __inline__ int @@ -58,7 +78,7 @@ i2c_wait4bus(void) { ulong timeval = get_timer(0); - while (readb(&I2C->sr) & I2C_SR_MBB) { + while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { if (get_timer(timeval) > I2C_TIMEOUT) { return -1; } @@ -74,11 +94,11 @@ i2c_wait(int write) ulong timeval = get_timer(0); do { - csr = readb(&I2C->sr); + csr = readb(&i2c_dev[i2c_bus_num]->sr); if (!(csr & I2C_SR_MIF)) continue; - writeb(0x0, &I2C->sr); + writeb(0x0, &i2c_dev[i2c_bus_num]->sr); if (csr & I2C_SR_MAL) { debug("i2c_wait: MAL\n"); @@ -107,9 +127,9 @@ i2c_write_addr (u8 dev, u8 dir, int rsta) { writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | (rsta ? I2C_CR_RSTA : 0), - &I2C->cr); + &i2c_dev[i2c_bus_num]->cr); - writeb((dev << 1) | dir, &I2C->dr); + writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); if (i2c_wait(I2C_WRITE) < 0) return 0; @@ -123,10 +143,10 @@ __i2c_write(u8 *data, int length) int i; writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, - &I2C->cr); + &i2c_dev[i2c_bus_num]->cr); for (i = 0; i < length; i++) { - writeb(data[i], &I2C->dr); + writeb(data[i], &i2c_dev[i2c_bus_num]->dr); if (i2c_wait(I2C_WRITE) < 0) break; @@ -141,10 +161,10 @@ __i2c_read(u8 *data, int length) int i; writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), - &I2C->cr); + &i2c_dev[i2c_bus_num]->cr); /* dummy read */ - readb(&I2C->dr); + readb(&i2c_dev[i2c_bus_num]->dr); for (i = 0; i < length; i++) { if (i2c_wait(I2C_READ) < 0) @@ -153,13 +173,13 @@ __i2c_read(u8 *data, int length) /* Generate ack on last next to last byte */ if (i == length - 2) writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, - &I2C->cr); + &i2c_dev[i2c_bus_num]->cr); /* Generate stop on last byte */ if (i == length - 1) - writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr); + writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); - data[i] = readb(&I2C->dr); + data[i] = readb(&i2c_dev[i2c_bus_num]->dr); } return i; @@ -178,7 +198,7 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) i = __i2c_read(data, length); } - writeb(I2C_CR_MEN, &I2C->cr); + writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); if (i == length) return 0; @@ -198,7 +218,7 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) i = __i2c_write(data, length); } - writeb(I2C_CR_MEN, &I2C->cr); + writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); if (i == length) return 0; @@ -237,5 +257,34 @@ i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) i2c_write(i2c_addr, reg, 1, &val, 1); } +int i2c_set_bus_num(unsigned int bus) +{ +#ifdef CFG_I2C2_OFFSET + if (bus > 1) { +#else + if (bus > 0) { +#endif + return -1; + } + + i2c_bus_num = bus; + + return 0; +} + +int i2c_set_bus_speed(unsigned int speed) +{ + return -1; +} + +unsigned int i2c_get_bus_num(void) +{ + return i2c_bus_num; +} + +unsigned int i2c_get_bus_speed(void) +{ + return 0; +} #endif /* CONFIG_HARD_I2C */ #endif /* CONFIG_FSL_I2C */ diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h deleted file mode 100644 index 37847666d..000000000 --- a/include/asm-ppc/i2c.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Freescale I2C Controller - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2003, Motorola, Inc. - * author: Eran Liberty (liberty@freescale.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_I2C_H_ -#define _ASM_I2C_H_ - -#include - -typedef struct i2c -{ - u8 adr; /**< I2C slave address */ -#define I2C_ADR 0xFE -#define I2C_ADR_SHIFT 1 -#define I2C_ADR_RES ~(I2C_ADR) - u8 res0[3]; - u8 fdr; /**< I2C frequency divider register */ -#define IC2_FDR 0x3F -#define IC2_FDR_SHIFT 0 -#define IC2_FDR_RES ~(IC2_FDR) - u8 res1[3]; - u8 cr; /**< I2C control redister */ -#define I2C_CR_MEN 0x80 -#define I2C_CR_MIEN 0x40 -#define I2C_CR_MSTA 0x20 -#define I2C_CR_MTX 0x10 -#define I2C_CR_TXAK 0x08 -#define I2C_CR_RSTA 0x04 -#define I2C_CR_BCST 0x01 - u8 res2[3]; - u8 sr; /**< I2C status register */ -#define I2C_SR_MCF 0x80 -#define I2C_SR_MAAS 0x40 -#define I2C_SR_MBB 0x20 -#define I2C_SR_MAL 0x10 -#define I2C_SR_BCSTM 0x08 -#define I2C_SR_SRW 0x04 -#define I2C_SR_MIF 0x02 -#define I2C_SR_RXAK 0x01 - u8 res3[3]; - u8 dr; /**< I2C data register */ -#define I2C_DR 0xFF -#define I2C_DR_SHIFT 0 -#define I2C_DR_RES ~(I2C_DR) - u8 res4[3]; - u8 dfsrr; /**< I2C digital filter sampling rate register */ -#define I2C_DFSRR 0x3F -#define I2C_DFSRR_SHIFT 0 -#define I2C_DFSRR_RES ~(I2C_DR) - u8 res5[3]; - u8 res6[0xE8]; -} i2c_t; - -#ifndef CFG_HZ -#error CFG_HZ is not defined in /include/configs/${BOARD}.h -#endif -#define I2C_TIMEOUT (CFG_HZ/4) - -#ifndef CFG_IMMR -#error CFG_IMMR is not defined in /include/configs/${BOARD}.h -#endif - -#ifndef CFG_I2C_OFFSET -#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h -#endif - -#define I2C_1 ((i2c_t*)(CFG_IMMR + CFG_I2C_OFFSET)) - -/* Optional support for second I2C bus */ -#ifdef CFG_I2C2_OFFSET -#define I2C_2 ((i2c_t*)(CFG_IMMR + CFG_I2C2_OFFSET)) -#endif /* CFG_I2C2_OFFSET */ - -#define I2C_READ 1 -#define I2C_WRITE 0 - -#endif /* _ASM_I2C_H_ */ diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 09e08ba0a..2a76a05c6 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -39,7 +39,7 @@ #include #include -#include +#include /* * Local Access Window. @@ -2007,7 +2007,7 @@ typedef struct immap { qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ #endif ddr83xx_t ddr; /* DDR Memory Controller Memory */ - i2c_t i2c[2]; /* I2C1 Controller */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ u8 res2[0x1300]; duart83xx_t duart[2]; /* DUART */ #if defined (CONFIG_MPC8349) diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 4a5b4bc4a..5bed2d0a2 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -335,6 +335,7 @@ /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index c74e63a4d..8dc96352a 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -41,14 +41,14 @@ Align. Board Bus Addr Part No. Description Length Location ---------------------------------------------------------------- - I2C1 0x50 M24256-BWMN6P Board EEPROM 2 U64 + I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 - I2C2 0x20 PCF8574 I2C Expander 0 U8 - I2C2 0x21 PCF8574 I2C Expander 0 U10 - I2C2 0x38 PCF8574A I2C Expander 0 U8 - I2C2 0x39 PCF8574A I2C Expander 0 U10 - I2C2 0x51 (DDR) DDR EEPROM 1 U1 - I2C2 0x68 DS1339 RTC 1 U68 + I2C1 0x20 PCF8574 I2C Expander 0 U8 + I2C1 0x21 PCF8574 I2C Expander 0 U10 + I2C1 0x38 PCF8574A I2C Expander 0 U8 + I2C1 0x39 PCF8574A I2C Expander 0 U10 + I2C1 0x51 (DDR) DDR EEPROM 1 U1 + I2C1 0x68 DS1339 RTC 1 U68 Note that a given board has *either* a pair of 8574s or a pair of 8574As. */ @@ -77,19 +77,20 @@ #define CONFIG_MISC_INIT_F #define CONFIG_MISC_INIT_R +#define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 -#define CFG_SPD_BUS_NUM 2 +#define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ -#define CFG_I2C_8574_ADDR1 0x20 /* I2C2, PCF8574 */ -#define CFG_I2C_8574_ADDR2 0x21 /* I2C2, PCF8574 */ -#define CFG_I2C_8574A_ADDR1 0x38 /* I2C2, PCF8574A */ -#define CFG_I2C_8574A_ADDR2 0x39 /* I2C2, PCF8574A */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C1, Board EEPROM */ -#define CFG_I2C_RTC_ADDR 0x68 /* I2C2, DS1339 RTC*/ -#define SPD_EEPROM_ADDRESS 0x51 /* I2C2, DDR */ +#define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ +#define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ +#define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ +#define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ +#define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ +#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -175,6 +176,7 @@ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ +#define CFG_FLASH_EMPTY_INFO #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ @@ -610,7 +612,7 @@ #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C1 clock mode (0-3) */ +#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ /* System IO Config */ @@ -708,6 +710,19 @@ #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #endif +#if 1 +#define CONFIG_IPADDR 10.82.19.159 +#define CONFIG_SERVERIP 10.82.48.106 +#define CONFIG_GATEWAYIP 10.82.19.254 +#define CONFIG_NETMASK 255.255.252.0 +#define CONFIG_NETDEV eth0 + +#define CONFIG_HOSTNAME mpc8349emitx +#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs +#define CONFIG_BOOTFILE timur/uImage + +#define CONFIG_UBOOTPATH timur/u-boot.bin +#else #define CONFIG_IPADDR 192.168.1.253 #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 @@ -719,6 +734,8 @@ #define CONFIG_BOOTFILE uImage #define CONFIG_UBOOTPATH u-boot.bin +#endif + #define CONFIG_UBOOTSTART fe700000 #define CONFIG_UBOOTEND fe77ffff diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index a8f2df911..2ff5f4898 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -330,7 +330,8 @@ /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 0x3F /* I2C speed and slave address */ +#define CONFIG_FSL_I2C +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index b0b0673cf..728083b30 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -218,6 +218,7 @@ extern int tqm834x_num_flash_banks; */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C #define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ #define CFG_I2C_SLAVE 0x7F /* slave address */ #define CFG_I2C_OFFSET 0x3000 -- cgit v1.2.3-70-g09d2 From e857a5bdb3954b896c0920cb9d8d2b1b9c107ce5 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 28 Nov 2006 12:09:35 -0600 Subject: mpc83xx: Miscellaneous code style fixes Implement various code style fixes and similar changes. Signed-off-by: Timur Tabi --- board/mpc8349itx/mpc8349itx.c | 2 +- common/cmd_i2c.c | 205 ++++++++++++++++-------------------------- cpu/mpc83xx/cpu.c | 5 -- cpu/mpc83xx/cpu_init.c | 5 -- cpu/mpc83xx/interrupts.c | 7 -- cpu/mpc83xx/spd_sdram.c | 74 ++++++--------- cpu/mpc83xx/speed.c | 10 --- cpu/mpc83xx/traps.c | 18 +--- 8 files changed, 108 insertions(+), 218 deletions(-) (limited to 'board/mpc8349itx') diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 097bb370e..4838e707f 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -349,7 +349,7 @@ int misc_init_r(void) u8 i2c_data; #ifdef CFG_I2C_RTC_ADDR - char ds1339_data[17]; + u8 ds1339_data[17]; #endif #ifdef CFG_I2C_EEPROM_ADDR diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 62378af8a..45cfde2eb 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -174,7 +174,7 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = 1; - for(j = 0; j < 8; j++) { + for (j = 0; j < 8; j++) { if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; if (alen > 4) { @@ -182,9 +182,8 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } break; - } else if (argv[2][j] == '\0') { + } else if (argv[2][j] == '\0') break; - } } /* @@ -208,9 +207,9 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; - if(i2c_read(chip, addr, alen, linebuf, linebytes) != 0) { + if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0) puts ("Error reading the chip.\n"); - } else { + else { printf("%04x:", addr); cp = linebuf; for (j=0; j 4) { + if (alen > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } break; - } else if (argv[2][j] == '\0') { + } else if (argv[2][j] == '\0') break; - } } /* @@ -300,16 +298,14 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Optional count */ - if(argc == 5) { + if (argc == 5) count = simple_strtoul(argv[4], NULL, 16); - } else { + else count = 1; - } while (count-- > 0) { - if(i2c_write(chip, addr++, alen, &byte, 1) != 0) { + if (i2c_write(chip, addr++, alen, &byte, 1) != 0) puts ("Error writing the chip.\n"); - } /* * Wait for the write to complete. The write can take * up to 10mSec (we allow a little more time). @@ -326,9 +322,9 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif #if 0 - for(timeout = 0; timeout < 10; timeout++) { + for (timeout = 0; timeout < 10; timeout++) { udelay(2000); - if(i2c_probe(chip) == 0) + if (i2c_probe(chip) == 0) break; } #endif @@ -369,17 +365,16 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = 1; - for(j = 0; j < 8; j++) { + for (j = 0; j < 8; j++) { if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; - if(alen > 4) { + if (alen > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } break; - } else if (argv[2][j] == '\0') { + } else if (argv[2][j] == '\0') break; - } } /* @@ -394,19 +389,16 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ crc = 0; err = 0; - while(count-- > 0) { - if(i2c_read(chip, addr, alen, &byte, 1) != 0) { + while (count-- > 0) { + if (i2c_read(chip, addr, alen, &byte, 1) != 0) err++; - } crc = crc32 (crc, &byte, 1); addr++; } - if(err > 0) - { + if (err > 0) puts ("Error reading the chip,\n"); - } else { + else printf ("%08lx\n", crc); - } return 0; } @@ -464,17 +456,16 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = 1; - for(j = 0; j < 8; j++) { + for (j = 0; j < 8; j++) { if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; - if(alen > 4) { + if (alen > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } break; - } else if (argv[2][j] == '\0') { + } else if (argv[2][j] == '\0') break; - } } } @@ -484,17 +475,16 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) */ do { printf("%08lx:", addr); - if(i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) { + if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) puts ("\nError reading the chip,\n"); - } else { + else { data = cpu_to_be32(data); - if(size == 1) { + if (size == 1) printf(" %02lx", (data >> 24) & 0x000000FF); - } else if(size == 2) { + else if (size == 2) printf(" %04lx", (data >> 16) & 0x0000FFFF); - } else { + else printf(" %08lx", data); - } } nbytes = readline (" ? "); @@ -511,19 +501,17 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) #endif } #ifdef CONFIG_BOOT_RETRY_TIME - else if (nbytes == -2) { + else if (nbytes == -2) break; /* timed out, exit the command */ - } #endif else { char *endp; data = simple_strtoul(console_buffer, &endp, 16); - if(size == 1) { + if (size == 1) data = data << 24; - } else if(size == 2) { + else if (size == 2) data = data << 16; - } data = be32_to_cpu(data); nbytes = endp - console_buffer; if (nbytes) { @@ -533,9 +521,8 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) */ reset_cmd_timeout(); #endif - if(i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) { + if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) puts ("Error writing the chip.\n"); - } #ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); #endif @@ -565,13 +552,11 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif /* NOPROBES */ puts ("Valid chip addresses:"); - for(j = 0; j < 128; j++) { + for (j = 0; j < 128; j++) { #if defined(CFG_I2C_NOPROBES) skip = 0; - for(k=0; k < NUM_ELEMENTS_NOPROBE; k++) - { - if(COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) - { + for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { + if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) { skip = 1; break; } @@ -579,17 +564,15 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (skip) continue; #endif - if(i2c_probe(j) == 0) { + if (i2c_probe(j) == 0) printf(" %02X", j); - } } putc ('\n'); #if defined(CFG_I2C_NOPROBES) puts ("Excluded chip addresses:"); - for(k=0; k < NUM_ELEMENTS_NOPROBE; k++) - { - if(COMPARE_BUS(bus,k)) + for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { + if (COMPARE_BUS(bus,k)) printf(" %02X", NO_PROBE_ADDR(k)); } putc ('\n'); @@ -630,7 +613,7 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = 1; - for(j = 0; j < 8; j++) { + for (j = 0; j < 8; j++) { if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; if (alen > 4) { @@ -638,9 +621,8 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } break; - } else if (argv[2][j] == '\0') { + } else if (argv[2][j] == '\0') break; - } } /* @@ -648,24 +630,21 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ length = 1; length = simple_strtoul(argv[3], NULL, 16); - if(length > sizeof(bytes)) { + if (length > sizeof(bytes)) length = sizeof(bytes); - } /* * The delay time (uSec) is optional. */ delay = 1000; - if (argc > 3) { + if (argc > 3) delay = simple_strtoul(argv[4], NULL, 10); - } /* * Run the loop... */ - while(1) { - if(i2c_read(chip, addr, alen, bytes, length) != 0) { + while (1) { + if (i2c_read(chip, addr, alen, bytes, length) != 0) puts ("Error reading the chip.\n"); - } udelay(delay); } @@ -700,7 +679,7 @@ int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ chip = simple_strtoul(argv[1], NULL, 16); - if(i2c_read(chip, 0, 1, data, sizeof(data)) != 0) { + if (i2c_read(chip, 0, 1, data, sizeof(data)) != 0) { puts ("No SDRAM Serial Presence Detect found.\n"); return 1; } @@ -709,7 +688,7 @@ int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) for (j = 0; j < 63; j++) { cksum += data[j]; } - if(cksum != data[63]) { + if (cksum != data[63]) { printf ("WARNING: Configuration data checksum failure:\n" " is 0x%02x, calculated 0x%02x\n", data[63], cksum); @@ -725,17 +704,15 @@ int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) default: puts ("unknown\n"); break; } puts ("Row address bits "); - if((data[3] & 0x00F0) == 0) { + if ((data[3] & 0x00F0) == 0) printf("%d\n", data[3] & 0x0F); - } else { + else printf("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F); - } puts ("Column address bits "); - if((data[4] & 0x00F0) == 0) { + if ((data[4] & 0x00F0) == 0) printf("%d\n", data[4] & 0x0F); - } else { + else printf("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F); - } printf("Module rows %d\n", data[5]); printf("Module data width %d bits\n", (data[7] << 8) | data[6]); puts ("Interface signal levels "); @@ -758,11 +735,10 @@ int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) case 2: puts ("ECC\n"); break; default: puts ("unknown\n"); break; } - if((data[12] & 0x80) == 0) { + if ((data[12] & 0x80) == 0) puts ("No self refresh, rate "); - } else { + else puts ("Self refresh, rate "); - } switch(data[12] & 0x7F) { case 0: puts ("15.625uS\n"); break; case 1: puts ("3.9uS\n"); break; @@ -773,17 +749,16 @@ int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) default: puts ("unknown\n"); break; } printf("SDRAM width (primary) %d\n", data[13] & 0x7F); - if((data[13] & 0x80) != 0) { + if ((data[13] & 0x80) != 0) { printf(" (second bank) %d\n", 2 * (data[13] & 0x7F)); } - if(data[14] != 0) { + if (data[14] != 0) { printf("EDC width %d\n", data[14] & 0x7F); - if((data[14] & 0x80) != 0) { + if ((data[14] & 0x80) != 0) printf(" (second bank) %d\n", 2 * (data[14] & 0x7F)); - } } printf("Min clock delay, back-to-back random column addresses %d\n", data[15]); @@ -881,18 +856,18 @@ int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) (data[35] & 0x80) ? '-' : '+', (data[35] >> 4) & 0x07, data[35] & 0x0F); puts ("Manufacturer's JEDEC ID "); - for(j = 64; j <= 71; j++) + for (j = 64; j <= 71; j++) printf("%02X ", data[j]); putc ('\n'); printf("Manufacturing Location %02X\n", data[72]); puts ("Manufacturer's Part Number "); - for(j = 73; j <= 90; j++) + for (j = 73; j <= 90; j++) printf("%02X ", data[j]); putc ('\n'); printf("Revision Code %02X %02X\n", data[91], data[92]); printf("Manufacturing Date %02X %02X\n", data[93], data[94]); puts ("Assembly Serial Number "); - for(j = 95; j <= 98; j++) + for (j = 95; j <= 98; j++) printf("%02X ", data[j]); putc ('\n'); printf("Speed rating PC%d\n", @@ -908,19 +883,15 @@ int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int bus_idx, ret=0; - if (argc == 1) /* querying current setting */ - { + if (argc == 1) + /* querying current setting */ printf("Current bus is %d\n", i2c_get_bus_num()); - } - else - { + else { bus_idx = simple_strtoul(argv[1], NULL, 10); printf("Setting bus to %d\n", bus_idx); ret = i2c_set_bus_num(bus_idx); - if(ret) - { + if (ret) printf("Failure changing bus number (%d)\n", ret); - } } return ret; } @@ -930,19 +901,15 @@ int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int speed, ret=0; - if (argc == 1) /* querying current speed */ - { + if (argc == 1) + /* querying current speed */ printf("Current bus speed=%d\n", i2c_get_bus_speed()); - } - else - { + else { speed = simple_strtoul(argv[1], NULL, 10); printf("Setting bus speed to %d Hz\n", speed); ret = i2c_set_bus_speed(speed); - if(ret) - { + if (ret) printf("Failure changing bus speed (%d)\n", ret); - } } return ret; } @@ -950,53 +917,31 @@ int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { #if defined(CONFIG_I2C_MULTI_BUS) - if(!strncmp(argv[1], "de", 2)) - { + if (!strncmp(argv[1], "de", 2)) return do_i2c_bus_num(cmdtp, flag, --argc, ++argv); - } #endif /* CONFIG_I2C_MULTI_BUS */ - if(!strncmp(argv[1], "sp", 2)) - { + if (!strncmp(argv[1], "sp", 2)) return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv); - } - if(!strncmp(argv[1], "md", 2)) - { + if (!strncmp(argv[1], "md", 2)) return do_i2c_md(cmdtp, flag, --argc, ++argv); - } - if(!strncmp(argv[1], "mm", 2)) - { + if (!strncmp(argv[1], "mm", 2)) return do_i2c_mm(cmdtp, flag, --argc, ++argv); - } - if(!strncmp(argv[1], "mw", 2)) - { + if (!strncmp(argv[1], "mw", 2)) return do_i2c_mw(cmdtp, flag, --argc, ++argv); - } - if(!strncmp(argv[1], "nm", 2)) - { + if (!strncmp(argv[1], "nm", 2)) return do_i2c_nm(cmdtp, flag, --argc, ++argv); - } - if(!strncmp(argv[1], "cr", 2)) - { + if (!strncmp(argv[1], "cr", 2)) return do_i2c_crc(cmdtp, flag, --argc, ++argv); - } - if(!strncmp(argv[1], "pr", 2)) - { + if (!strncmp(argv[1], "pr", 2)) return do_i2c_probe(cmdtp, flag, --argc, ++argv); - } - if(!strncmp(argv[1], "lo", 2)) - { + if (!strncmp(argv[1], "lo", 2)) return do_i2c_loop(cmdtp, flag, --argc, ++argv); - } #if (CONFIG_COMMANDS & CFG_CMD_SDRAM) - if(!strncmp(argv[1], "sd", 2)) - { + if (!strncmp(argv[1], "sd", 2)) return do_sdram(cmdtp, flag, --argc, ++argv); - } #endif /* CFG_CMD_SDRAM */ else - { printf ("Usage:\n%s\n", cmdtp->usage); - } return 0; } #endif /* CONFIG_I2C_CMD_TREE */ diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 1d169bab2..1b5107881 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -18,11 +18,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - * - * Change log: - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) */ /* diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 4f80f4a09..e5725fb91 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -18,11 +18,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - * - * Change log: - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) */ #include diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c index 98fccff22..bb1fe1af3 100644 --- a/cpu/mpc83xx/interrupts.c +++ b/cpu/mpc83xx/interrupts.c @@ -21,13 +21,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - * - * Change log: - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00 - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) */ #include diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index dc8f6790a..cfc42c4a8 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -25,15 +25,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - * - * Change log: - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - * 20060601: Dave Liu (daveliu@freescale.com) - * DDR ECC support - * unify variable names for 83xx - * code cleanup */ #include @@ -45,6 +36,8 @@ #ifdef CONFIG_SPD_EEPROM +DECLARE_GLOBAL_DATA_PTR; + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) extern void dma_init(void); extern uint dma_check(void); @@ -58,19 +51,16 @@ extern int dma_xfer(void *dest, uint count, void *src); /* * Convert picoseconds into clock cycles (rounding up if needed). */ -extern ulong get_ddr_clk(ulong dummy); - int picos_to_clk(int picos) { unsigned int ddr_bus_clk; int clks; - ddr_bus_clk = get_ddr_clk(0) >> 1; + ddr_bus_clk = gd->ddr_clk >> 1; clks = picos / ((1000000000 / ddr_bus_clk) * 1000); - if (picos % ((1000000000 / ddr_bus_clk) * 1000) !=0) { + if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0) clks++; - } return clks; } @@ -249,7 +239,7 @@ long int spd_sdram() debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate); - ddrc_clk = get_ddr_clk(0) / 1000000; + ddrc_clk = gd->ddr_clk / 1000000; if (max_data_rate >= 390) { /* it is DDR 400 */ if (ddrc_clk <= 410 && ddrc_clk > 350) { @@ -259,31 +249,28 @@ long int spd_sdram() } else if (ddrc_clk <= 350 && ddrc_clk > 280) { /* DDR controller clk at 280~350 */ effective_data_rate = 333; /* 6ns */ - if (spd.clk_cycle2 == 0x60) { + if (spd.clk_cycle2 == 0x60) caslat = caslat - 1; - } else { + else caslat = caslat; - } } else if (ddrc_clk <= 280 && ddrc_clk > 230) { /* DDR controller clk at 230~280 */ effective_data_rate = 266; /* 7.5ns */ - if (spd.clk_cycle3 == 0x75) { + if (spd.clk_cycle3 == 0x75) caslat = caslat - 2; - } else if (spd.clk_cycle2 == 0x60) { + else if (spd.clk_cycle2 == 0x60) caslat = caslat - 1; - } else { + else caslat = caslat; - } } else if (ddrc_clk <= 230 && ddrc_clk > 90) { /* DDR controller clk at 90~230 */ effective_data_rate = 200; /* 10ns */ - if (spd.clk_cycle3 == 0x75) { + if (spd.clk_cycle3 == 0x75) caslat = caslat - 2; - } else if (spd.clk_cycle2 == 0x60) { + else if (spd.clk_cycle2 == 0x60) caslat = caslat - 1; - } else { + else caslat = caslat; - } } } else if (max_data_rate >= 323) { /* it is DDR 333 */ if (ddrc_clk <= 350 && ddrc_clk > 280) { @@ -293,21 +280,19 @@ long int spd_sdram() } else if (ddrc_clk <= 280 && ddrc_clk > 230) { /* DDR controller clk at 230~280 */ effective_data_rate = 266; /* 7.5ns */ - if (spd.clk_cycle2 == 0x75) { + if (spd.clk_cycle2 == 0x75) caslat = caslat - 1; - } else { + else caslat = caslat; - } } else if (ddrc_clk <= 230 && ddrc_clk > 90) { /* DDR controller clk at 90~230 */ effective_data_rate = 200; /* 10ns */ - if (spd.clk_cycle3 == 0xa0) { + if (spd.clk_cycle3 == 0xa0) caslat = caslat - 2; - } else if (spd.clk_cycle2 == 0x75) { + else if (spd.clk_cycle2 == 0x75) caslat = caslat - 1; - } else { + else caslat = caslat; - } } } else if (max_data_rate >= 256) { /* it is DDR 266 */ if (ddrc_clk <= 350 && ddrc_clk > 280) { @@ -322,9 +307,8 @@ long int spd_sdram() } else if (ddrc_clk <= 230 && ddrc_clk > 90) { /* DDR controller clk at 90~230 */ effective_data_rate = 200; /* 10ns */ - if (spd.clk_cycle2 == 0xa0) { + if (spd.clk_cycle2 == 0xa0) caslat = caslat - 1; - } } } else if (max_data_rate >= 190) { /* it is DDR 200 */ if (ddrc_clk <= 350 && ddrc_clk > 230) { @@ -346,13 +330,13 @@ long int spd_sdram() * Errata DDR6 work around: input enable 2 cycles earlier. * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2. */ - if (caslat == 2) { + if (caslat == 2) ddr->debug_reg = 0x201c0000; /* CL=2 */ - } else if (caslat == 3) { + else if (caslat == 3) ddr->debug_reg = 0x202c0000; /* CL=2.5 */ - } else if (caslat == 4) { + else if (caslat == 4) ddr->debug_reg = 0x202c0000; /* CL=3.0 */ - } + __asm__ __volatile__ ("sync"); debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); @@ -392,11 +376,10 @@ long int spd_sdram() } /* Is this an ECC DDR chip? */ - if (spd.config == 0x02) { + if (spd.config == 0x02) printf(" with ECC\n"); - } else { + else printf(" without ECC\n"); - } /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus, Burst type is sequential @@ -482,14 +465,13 @@ long int spd_sdram() sdram_cfg = 0xC2000000; /* sdram_cfg[3] = RD_EN - registered DIMM enable */ - if (spd.mod_attr & 0x02) { + if (spd.mod_attr & 0x02) sdram_cfg |= 0x10000000; - } /* The DIMM is 32bit width */ - if (spd.dataw_lsb == 0x20) { + if (spd.dataw_lsb == 0x20) sdram_cfg |= 0x000C0000; - } + ddrc_ecc_enable = 0; #if defined(CONFIG_DDR_ECC) diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 213e7180a..7e53b1e60 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -21,11 +21,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - * - * Change log: - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) */ #include @@ -343,11 +338,6 @@ int get_clocks(void) } -ulong get_ddr_clk(ulong dummy) -{ - return gd->ddr_clk; -} - /******************************************** * get_bus_freq * return system bus freq in Hz diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c index 44345afbf..152fa7356 100644 --- a/cpu/mpc83xx/traps.c +++ b/cpu/mpc83xx/traps.c @@ -1,5 +1,8 @@ /* - * linux/arch/ppc/kernel/traps.c + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -15,19 +18,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - * - * Change log: - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) */ /* -- cgit v1.2.3-70-g09d2