From 49f5befafd0f71e3ba033081e80fa4965d682ebc Mon Sep 17 00:00:00 2001
From: Xie Xiaobo <X.Xie@freescale.com>
Date: Mon, 24 Jun 2013 15:01:30 +0800
Subject: powerpc/85xx: Add TWR-P10xx board support

TWR-P1025 Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (on board DDR)
   64Mbyte 16bit NOR flash
   One microSD Card slot

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC3: Connected to Atheros AR8035 GETH PHY

UART:
   Two UARTs are routed to the FDTI dual USB to RS232 convertor

USB: Two USB2.0 Type A ports

I2C:
   AT24C01B 1K Board EEPROM (8 bit address)

QUICC Engine:
   Connected to DP83849i PHY supply two 10/100M ethernet ports
   QE UART for RS485 or RS232

PCIE:
   One mini-PCIE slot

Signed-off-by: Michael Johnston <michael.johnston@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
[yorksun: Fixup include/configs/p1_twr.h]
Signed-off-by: York Sun <yorksun@freescale.com>
---
 board/freescale/p1_twr/ddr.c | 71 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 board/freescale/p1_twr/ddr.c

(limited to 'board/freescale/p1_twr/ddr.c')

diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
new file mode 100644
index 000000000..ff278ae9f
--- /dev/null
+++ b/board/freescale/p1_twr/ddr.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+/* Fixed sdram init -- doesn't use serial presence detect. */
+phys_size_t fixed_sdram(void)
+{
+	sys_info_t sysinfo;
+	char buf[32];
+	size_t ddr_size;
+	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
+		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+#endif
+		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
+		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
+		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
+		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
+		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
+		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
+		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+		.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
+		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
+		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+	};
+
+	get_sys_info(&sysinfo);
+	printf("Configuring DDR for %s MT/s data rate\n",
+			strmhz(buf, sysinfo.freqDDRBus));
+
+	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
+		printf("ERROR setting Local Access Windows for DDR\n");
+		return 0;
+	};
+
+	return ddr_size;
+}
-- 
cgit v1.2.3-70-g09d2


From c63e137014cf148bc1d234128941dccee3d519ae Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Tue, 25 Jun 2013 11:37:48 -0700
Subject: powerpc/mpc8xxx: Add memory reset control

JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/ddr-gen1.c      |  2 +-
 arch/powerpc/cpu/mpc85xx/ddr-gen2.c      |  2 +-
 arch/powerpc/cpu/mpc85xx/ddr-gen3.c      | 29 ++++++++++++++++-
 arch/powerpc/cpu/mpc86xx/ddr-8641.c      |  2 +-
 arch/powerpc/cpu/mpc8xxx/ddr/ddr.h       |  2 +-
 arch/powerpc/cpu/mpc8xxx/ddr/main.c      | 54 +++++++++++++++++++++++++++-----
 arch/powerpc/include/asm/fsl_ddr_sdram.h | 24 +++++++++++++-
 board/freescale/bsc9131rdb/ddr.c         |  2 +-
 board/freescale/bsc9132qds/ddr.c         |  2 +-
 board/freescale/common/qixis.c           | 20 ++++++++++++
 board/freescale/corenet_ds/ddr.c         |  4 +--
 board/freescale/p1010rdb/ddr.c           |  2 +-
 board/freescale/p1_p2_rdb/ddr.c          |  2 +-
 board/freescale/p1_p2_rdb_pc/ddr.c       |  2 +-
 board/freescale/p1_twr/ddr.c             |  2 +-
 include/configs/T4240QDS.h               |  1 +
 16 files changed, 131 insertions(+), 21 deletions(-)

(limited to 'board/freescale/p1_twr/ddr.c')

diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
index 8a86819fb..4dd8c0b5b 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
@@ -15,7 +15,7 @@
 #endif
 
 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-			     unsigned int ctrl_num)
+			     unsigned int ctrl_num, int step)
 {
 	unsigned int i;
 	volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
index a70586252..542bc84ac 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
@@ -16,7 +16,7 @@
 #endif
 
 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-			     unsigned int ctrl_num)
+			     unsigned int ctrl_num, int step)
 {
 	unsigned int i;
 	ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index 3e7a56489..1be51d330 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -15,8 +15,18 @@
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
 #endif
 
+
+/*
+ * regs has the to-be-set values for DDR controller registers
+ * ctrl_num is the DDR controller number
+ * step: 0 goes through the initialization in one pass
+ *       1 sets registers and returns before enabling controller
+ *       2 resumes from step 1 and continues to initialize
+ * Dividing the initialization to two steps to deassert DDR reset signal
+ * to comply with JEDEC specs for RDIMMs.
+ */
 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-			     unsigned int ctrl_num)
+			     unsigned int ctrl_num, int step)
 {
 	unsigned int i, bus_width;
 	volatile ccsr_ddr_t *ddr;
@@ -54,6 +64,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		return;
 	}
 
+	if (step == 2)
+		goto step2;
+
 	if (regs->ddr_eor)
 		out_be32(&ddr->eor, regs->ddr_eor);
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
@@ -157,6 +170,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->debug[21], 0x24000000);
 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 
+	/*
+	 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
+	 * deasserted. Clocks start when any chip select is enabled and clock
+	 * control register is set. Because all DDR components are connected to
+	 * one reset signal, this needs to be done in two steps. Step 1 is to
+	 * get the clocks started. Step 2 resumes after reset signal is
+	 * deasserted.
+	 */
+	if (step == 1) {
+		udelay(200);
+		return;
+	}
+
+step2:
 	/* Set, but do not enable the memory */
 	temp_sdram_cfg = regs->ddr_sdram_cfg;
 	temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
diff --git a/arch/powerpc/cpu/mpc86xx/ddr-8641.c b/arch/powerpc/cpu/mpc86xx/ddr-8641.c
index 92ba26dc8..33a91f9f7 100644
--- a/arch/powerpc/cpu/mpc86xx/ddr-8641.c
+++ b/arch/powerpc/cpu/mpc86xx/ddr-8641.c
@@ -15,7 +15,7 @@
 #endif
 
 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-			     unsigned int ctrl_num)
+			     unsigned int ctrl_num, int step)
 {
 	unsigned int i;
 	volatile ccsr_ddr_t *ddr;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index 4dd55fc4c..c173a5a74 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -96,7 +96,7 @@ unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
 
 /* processor specific function */
 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-				   unsigned int ctrl_num);
+				   unsigned int ctrl_num, int step);
 
 /* board specific function */
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index c35405dcc..9f4f25343 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -25,10 +25,6 @@ void fsl_ddr_set_lawbar(
 		unsigned int ctrl_num);
 void fsl_ddr_set_intl3r(const unsigned int granule_size);
 
-/* processor specific function */
-extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-				   unsigned int ctrl_num);
-
 #if defined(SPD_EEPROM_ADDRESS) || \
     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
@@ -365,9 +361,11 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 {
 	unsigned int i, j;
 	unsigned long long total_mem = 0;
+	int assert_reset;
 
 	fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 	common_timing_params_t *timing_params = pinfo->common_timing_params;
+	assert_reset = board_need_mem_reset();
 
 	/* data bus width capacity adjust shift amount */
 	unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
@@ -462,7 +460,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 					timing_params[i].all_DIMMs_registered,
 					&pinfo->memctl_opts[i],
 					pinfo->dimm_params[i], i);
+			/*
+			 * For RDIMMs, JEDEC spec requires clocks to be stable
+			 * before reset signal is deasserted. For the boards
+			 * using fixed parameters, this function should be
+			 * be called from board init file.
+			 */
+			if (timing_params[i].all_DIMMs_registered)
+				assert_reset = 1;
+		}
+		if (assert_reset) {
+			debug("Asserting mem reset\n");
+			board_assert_mem_reset();
 		}
+
 	case STEP_ASSIGN_ADDRESSES:
 		/* STEP 5:  Assign addresses to chip selects */
 		check_interleaving_options(pinfo);
@@ -537,6 +548,7 @@ phys_size_t fsl_ddr_sdram(void)
 	unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
 	unsigned long long total_memory;
 	fsl_ddr_info_t info;
+	int deassert_reset;
 
 	/* Reset info structure. */
 	memset(&info, 0, sizeof(fsl_ddr_info_t));
@@ -565,7 +577,21 @@ phys_size_t fsl_ddr_sdram(void)
 		}
 	}
 
-	/* Program configuration registers. */
+	/*
+	 * Program configuration registers.
+	 * JEDEC specs requires clocks to be stable before deasserting reset
+	 * for RDIMMs. Clocks start after chip select is enabled and clock
+	 * control register is set. During step 1, all controllers have their
+	 * registers set but not enabled. Step 2 proceeds after deasserting
+	 * reset through board FPGA or GPIO.
+	 * For non-registered DIMMs, initialization can go through but it is
+	 * also OK to follow the same flow.
+	 */
+	deassert_reset = board_need_mem_reset();
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		if (info.common_timing_params[i].all_DIMMs_registered)
+			deassert_reset = 1;
+	}
 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 		debug("Programming controller %u\n", i);
 		if (info.common_timing_params[i].ndimms_present == 0) {
@@ -573,8 +599,22 @@ phys_size_t fsl_ddr_sdram(void)
 					"skipping programming\n", i);
 			continue;
 		}
-
-		fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
+		/*
+		 * The following call with step = 1 returns before enabling
+		 * the controller. It has to finish with step = 2 later.
+		 */
+		fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i,
+					deassert_reset ? 1 : 0);
+	}
+	if (deassert_reset) {
+		/* Use board FPGA or GPIO to deassert reset signal */
+		debug("Deasserting mem reset\n");
+		board_deassert_mem_reset();
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			/* Call with step = 2 to continue initialization */
+			fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]),
+						i, 2);
+		}
 	}
 
 	/* program LAWs */
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index bac22fcd1..f4eec82d5 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -331,9 +331,31 @@ extern phys_size_t fsl_ddr_sdram(void);
 extern phys_size_t fsl_ddr_sdram_size(void);
 extern int fsl_use_spd(void);
 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-					unsigned int ctrl_num);
+					unsigned int ctrl_num, int step);
 u32 fsl_ddr_get_intl3r(void);
 
+static void __board_assert_mem_reset(void)
+{
+}
+
+static void __board_deassert_mem_reset(void)
+{
+}
+
+void board_assert_mem_reset(void)
+	__attribute__((weak, alias("__board_assert_mem_reset")));
+
+void board_deassert_mem_reset(void)
+	__attribute__((weak, alias("__board_deassert_mem_reset")));
+
+static int __board_need_mem_reset(void)
+{
+	return 0;
+}
+
+int board_need_mem_reset(void)
+	__attribute__((weak, alias("__board_need_mem_reset")));
+
 /*
  * The 85xx boards have a common prototype for fixed_sdram so put the
  * declaration here.
diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c
index a4161ad64..c82fe0aab 100644
--- a/board/freescale/bsc9131rdb/ddr.c
+++ b/board/freescale/bsc9131rdb/ddr.c
@@ -87,7 +87,7 @@ phys_size_t fixed_sdram(void)
 	}
 
 	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
 	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
 					LAW_TRGT_IF_DDR_1) < 0) {
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
index 05bea8ad5..fdea19312 100644
--- a/board/freescale/bsc9132qds/ddr.c
+++ b/board/freescale/bsc9132qds/ddr.c
@@ -109,7 +109,7 @@ phys_size_t fixed_sdram(void)
 					strmhz(buf, ddr_freq));
 
 	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
 	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
 					LAW_TRGT_IF_DDR_1) < 0) {
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 40ce6b082..a49e3006d 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -107,6 +107,26 @@ const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
 	return buf;
 }
 
+#ifdef QIXIS_RST_FORCE_MEM
+void board_assert_mem_reset(void)
+{
+	u8 rst;
+
+	rst = QIXIS_READ(rst_frc[0]);
+	if (!(rst & QIXIS_RST_FORCE_MEM))
+		QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
+}
+
+void board_deassert_mem_reset(void)
+{
+	u8 rst;
+
+	rst = QIXIS_READ(rst_frc[0]);
+	if (rst & QIXIS_RST_FORCE_MEM)
+		QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
+}
+#endif
+
 void qixis_reset(void)
 {
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index da284cde9..517e87ff4 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -56,14 +56,14 @@ phys_size_t fixed_sdram(void)
 
 	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
 	memcpy(&ddr_cfg_regs,
 		fixed_ddr_parm_1[i].ddr_settings,
 		sizeof(ddr_cfg_regs));
 	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0);
 #endif
 
 	/*
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index aa8badab4..681f052e4 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -139,7 +139,7 @@ phys_size_t fixed_sdram(void)
 	}
 
 	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
 	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
 					LAW_TRGT_IF_DDR_1) < 0) {
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 0038077fc..5bee22e63 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -220,7 +220,7 @@ phys_size_t fixed_sdram (void)
 		ddr_cfg_regs.cs[0].bnds = 0x0000001F;
 	}
 
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
 	set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
 	return ddr_size;
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 9355536b3..14f0539b4 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -251,7 +251,7 @@ phys_size_t fixed_sdram(void)
 
 	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
 	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
 				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
index ff278ae9f..f94e1ab17 100644
--- a/board/freescale/p1_twr/ddr.c
+++ b/board/freescale/p1_twr/ddr.c
@@ -59,7 +59,7 @@ phys_size_t fixed_sdram(void)
 
 	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
 	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
 				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 2cf4a69f2..d92de3596 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -161,6 +161,7 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
 #define QIXIS_RST_CTL_RESET		0x83
+#define QIXIS_RST_FORCE_MEM		0x1
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
-- 
cgit v1.2.3-70-g09d2


From 3aab0cd852d7c9565c2559a7983cbb73852bac28 Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Mon, 12 Aug 2013 14:57:12 -0700
Subject: powerpc/mpc85xx: Cleanup license header in source files

Fix the license header introduced by the following patches

Add TWR-P10xx board support
Add T4240EMU target
IDT8T49N222A configuration code
Add C29x SoC support
Add support for C29XPCIE board

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/c29x_serdes.c           |  5 +----
 board/freescale/c29xpcie/Makefile                |  6 +-----
 board/freescale/c29xpcie/c29xpcie.c              |  5 +----
 board/freescale/c29xpcie/cpld.c                  |  5 +----
 board/freescale/c29xpcie/cpld.h                  |  5 +----
 board/freescale/c29xpcie/ddr.c                   |  5 +----
 board/freescale/c29xpcie/law.c                   |  5 +----
 board/freescale/c29xpcie/tlb.c                   |  5 +----
 board/freescale/common/idt8t49n222a_serdes_clk.c | 15 +--------------
 board/freescale/common/idt8t49n222a_serdes_clk.h | 15 +--------------
 board/freescale/p1_twr/Makefile                  | 19 +------------------
 board/freescale/p1_twr/ddr.c                     |  4 +---
 board/freescale/p1_twr/law.c                     | 18 +-----------------
 board/freescale/p1_twr/p1_twr.c                  | 18 +-----------------
 board/freescale/p1_twr/tlb.c                     | 18 +-----------------
 board/freescale/t4qds/ddr.h                      | 15 +--------------
 board/freescale/t4qds/t4240emu.c                 | 18 +-----------------
 board/freescale/t4qds/t4240qds.c                 | 18 +-----------------
 include/configs/C29XPCIE.h                       | 18 +-----------------
 include/configs/T4240EMU.h                       | 18 +-----------------
 include/configs/p1_twr.h                         | 18 +-----------------
 21 files changed, 21 insertions(+), 232 deletions(-)

(limited to 'board/freescale/p1_twr/ddr.c')

diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
index 4b3214dd5..51972cb7c 100644
--- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
@@ -1,10 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <config.h>
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index 15bef9a85..ab8eb8f72 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -1,11 +1,7 @@
 #
 # Copyright 2013 Freescale Semiconductor, Inc.
 #
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License as published by the Free
-# Software Foundation; either version 2 of the License, or (at your option)
-# any later version.
-#
+# SPDX-License-Identifier:	GPL-2.0+
 
 include $(TOPDIR)/config.mk
 
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index acc59d2a0..48c4b308b 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -1,10 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
index b17a7ba38..5cbccff63 100644
--- a/board/freescale/c29xpcie/cpld.c
+++ b/board/freescale/c29xpcie/cpld.c
@@ -3,10 +3,7 @@
  * Author: Mingkai Hu <Mingkai.hu@freescale.com>
  *         Po Liu <Po.Liu@freescale.com>
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier:	GPL-2.0+
  *
  * This file provides support for the board-specific CPLD used on some Freescale
  * reference boards.
diff --git a/board/freescale/c29xpcie/cpld.h b/board/freescale/c29xpcie/cpld.h
index 24093c4e3..20862a3c0 100644
--- a/board/freescale/c29xpcie/cpld.h
+++ b/board/freescale/c29xpcie/cpld.h
@@ -3,10 +3,7 @@
  * Author: Mingkai Hu <Mingkai.Hu@freescale.com>
  *         Po Liu <Po.Liu@freescale.com>
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier:	GPL-2.0+
  *
  * This file provides support for the ngPIXIS, a board-specific FPGA used on
  * some Freescale reference boards.
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
index 62476cae6..b017cfd96 100644
--- a/board/freescale/c29xpcie/ddr.c
+++ b/board/freescale/c29xpcie/ddr.c
@@ -1,10 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c
index 10a2fbf5e..cd8fc2105 100644
--- a/board/freescale/c29xpcie/law.c
+++ b/board/freescale/c29xpcie/law.c
@@ -1,10 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index a175906a0..ddd1ef80b 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -1,10 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.c b/board/freescale/common/idt8t49n222a_serdes_clk.c
index 8798c87af..d34716227 100644
--- a/board/freescale/common/idt8t49n222a_serdes_clk.c
+++ b/board/freescale/common/idt8t49n222a_serdes_clk.c
@@ -2,20 +2,7 @@
  * Copyright 2013 Freescale Semiconductor, Inc.
  * Author: Shaveta Leekha <shaveta@freescale.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include "idt8t49n222a_serdes_clk.h"
diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.h b/board/freescale/common/idt8t49n222a_serdes_clk.h
index d7d64e71e..787bdd9ca 100644
--- a/board/freescale/common/idt8t49n222a_serdes_clk.h
+++ b/board/freescale/common/idt8t49n222a_serdes_clk.h
@@ -2,20 +2,7 @@
  * Copyright 2013 Freescale Semiconductor, Inc.
  * Author: Shaveta Leekha <shaveta@freescale.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __IDT8T49N222A_SERDES_CLK_H_
diff --git a/board/freescale/p1_twr/Makefile b/board/freescale/p1_twr/Makefile
index fb29b147c..915b9bc89 100644
--- a/board/freescale/p1_twr/Makefile
+++ b/board/freescale/p1_twr/Makefile
@@ -1,24 +1,7 @@
 #
 # Copyright 2013 Freescale Semiconductor, Inc.
 #
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
+# SPDX-License-Identifier:	GPL-2.0+
 
 include $(TOPDIR)/config.mk
 
diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
index f94e1ab17..697c0dd37 100644
--- a/board/freescale/p1_twr/ddr.c
+++ b/board/freescale/p1_twr/ddr.c
@@ -1,9 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
diff --git a/board/freescale/p1_twr/law.c b/board/freescale/p1_twr/law.c
index a7af20098..e79d8a4c1 100644
--- a/board/freescale/p1_twr/law.c
+++ b/board/freescale/p1_twr/law.c
@@ -1,23 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <common.h>
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
index 79c1047d2..ea8db6fc0 100644
--- a/board/freescale/p1_twr/p1_twr.c
+++ b/board/freescale/p1_twr/p1_twr.c
@@ -1,23 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
diff --git a/board/freescale/p1_twr/tlb.c b/board/freescale/p1_twr/tlb.c
index 68e109c95..308335c97 100644
--- a/board/freescale/p1_twr/tlb.c
+++ b/board/freescale/p1_twr/tlb.c
@@ -1,23 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
index 4f73285ac..d0a0951af 100644
--- a/board/freescale/t4qds/ddr.h
+++ b/board/freescale/t4qds/ddr.h
@@ -1,20 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __DDR_H__
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
index 589a2ae35..7a610367d 100644
--- a/board/freescale/t4qds/t4240emu.c
+++ b/board/freescale/t4qds/t4240emu.c
@@ -1,23 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 89e56a312..7ee0f5478 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -1,23 +1,7 @@
 /*
  * Copyright 2009-2012 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 045368884..83779eff8 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -1,23 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /*
diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h
index 033992db9..9fa6b77ab 100644
--- a/include/configs/T4240EMU.h
+++ b/include/configs/T4240EMU.h
@@ -1,23 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /*
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index cd41bbb40..4aa706422 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -1,23 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /*
-- 
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