From 45fdb627b3849432cd17adda4bd2763e68c8df94 Mon Sep 17 00:00:00 2001 From: "Haijun.Zhang" Date: Fri, 28 Jun 2013 10:47:09 +0800 Subject: p1020rdb-pd: platform support Add new board p1020RDB-PD. P1020RDB-PD board was update from P1020RDB. DDR changed from DDR2 1G to DDR3 2G. NAND: 128 MiB Flash: 64 MiB Also change P1020RDB to P1020RDB-PC to distinguish from P1020RDB board. Signed-off-by: Jerry Huang Signed-off-by: Haijun Zhang CC: Scott Wood Acked-by: York Sun --- board/freescale/p1_p2_rdb_pc/ddr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board/freescale/p1_p2_rdb_pc/ddr.c') diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 14f0539b4..5c51845dd 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -80,7 +80,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tFAW_ps = 30000, }; -#elif defined(CONFIG_P1020MBG) +#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) /* Micron MT41J512M8_187E */ dimm_params_t ddr_raw_timing = { .n_ranks = 2, @@ -111,7 +111,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tFAW_ps = 37500, }; -#elif defined(CONFIG_P1020RDB) +#elif defined(CONFIG_P1020RDB_PC) /* * Samsung K4B2G0846C-HCF8 * The following timing are for "downshift" -- cgit v1.2.3-70-g09d2