From ef5a5b004997a0759d6f5f3206a419f90d5ffac5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 29 Nov 2011 18:05:07 +0000 Subject: x86: Initial commit for running as a coreboot payload Add a target for running u-boot as a coreboot payload in boards.cfg, a board, CPU and a config. This is a skeleton implementation which always reports the size of memory as 64 MB. Signed-off-by: Gabe Black --- board/chromebook-x86/coreboot/coreboot.c | 77 ++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 board/chromebook-x86/coreboot/coreboot.c (limited to 'board/chromebook-x86/coreboot/coreboot.c') diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/chromebook-x86/coreboot/coreboot.c new file mode 100644 index 000000000..44c6f155b --- /dev/null +++ b/board/chromebook-x86/coreboot/coreboot.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; + +/* + * Miscellaneous platform dependent initializations + */ +int board_early_init_f(void) +{ + return 0; +} + +int board_early_init_r(void) +{ + /* CPU Speed to 100MHz */ + gd->cpu_clk = 100000000; + + /* Crystal is 33.000MHz */ + gd->bus_clk = 33000000; + + return 0; +} + +void show_boot_progress(int val) +{ +} + + +int last_stage_init(void) +{ + return 0; +} + +#ifndef CONFIG_SYS_NO_FLASH +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + return 0; +} +#endif + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +void setup_pcat_compatibility() +{ +} -- cgit v1.2.3-70-g09d2