From e761ecdbb83e3151ffea5b531523256c57e62527 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 17 Apr 2013 16:13:36 +0000 Subject: x86: Add TSC timer This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing. Tidy up some old broken and unneeded implementations at the same time. To provide a consistent view of boot time, we use the same time base as coreboot. Use the base timestamp supplied by coreboot as U-Boot's base time. Signed-off-by: Simon Glass base Signed-off-by: Simon Glass --- arch/x86/lib/tsc_timer.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 arch/x86/lib/tsc_timer.c (limited to 'arch/x86/lib/tsc_timer.c') diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c new file mode 100644 index 000000000..d931e5f5e --- /dev/null +++ b/arch/x86/lib/tsc_timer.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void timer_set_base(u64 base) +{ + gd->arch.tsc_base = base; +} + +/* + * Get the number of CPU time counter ticks since it was read first time after + * restart. This yields a free running counter guaranteed to take almost 6 + * years to wrap around even at 100GHz clock rate. + */ +u64 get_ticks(void) +{ + u64 now_tick = rdtsc(); + + /* We assume that 0 means the base hasn't been set yet */ + if (!gd->arch.tsc_base) + panic("No tick base available"); + return now_tick - gd->arch.tsc_base; +} + +#define PLATFORM_INFO_MSR 0xce + +/* Get the speed of the TSC timer in MHz */ +unsigned long get_tbclk_mhz(void) +{ + u32 ratio; + u64 platform_info = native_read_msr(PLATFORM_INFO_MSR); + + /* 100MHz times Max Non Turbo ratio */ + ratio = (platform_info >> 8) & 0xff; + return 100 * ratio; +} + +unsigned long get_tbclk(void) +{ + return get_tbclk_mhz() * 1000 * 1000; +} + +static ulong get_ms_timer(void) +{ + return (get_ticks() * 1000) / get_tbclk(); +} + +ulong get_timer(ulong base) +{ + return get_ms_timer() - base; +} + +ulong timer_get_us(void) +{ + return get_ticks() / get_tbclk_mhz(); +} + +ulong timer_get_boot_us(void) +{ + return timer_get_us(); +} + +void __udelay(unsigned long usec) +{ + u64 now = get_ticks(); + u64 stop; + + stop = now + usec * get_tbclk_mhz(); + + while ((int64_t)(stop - get_ticks()) > 0) + ; +} + +int timer_init(void) +{ + /* Nothing to do here - the timer needs no init */ + return 0; +} -- cgit v1.2.3-70-g09d2 From d0b6f247a1e7ffd06d931ca4088426134dc4e546 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 17 Apr 2013 16:13:39 +0000 Subject: x86: Re-enable PCAT timer 2 for beeping While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot. Signed-off-by: Simon Glass --- arch/x86/include/asm/u-boot-x86.h | 1 + arch/x86/lib/Makefile | 2 +- arch/x86/lib/pcat_timer.c | 69 ++------------------------------------- arch/x86/lib/tsc_timer.c | 6 +++- include/configs/coreboot.h | 1 + 5 files changed, 11 insertions(+), 68 deletions(-) (limited to 'arch/x86/lib/tsc_timer.c') diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index bec583feb..22e093427 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -41,6 +41,7 @@ typedef void (timer_fnc_t) (void); int register_timer_isr (timer_fnc_t *isr_func); unsigned long get_tbclk_mhz(void); void timer_set_base(uint64_t base); +int pcat_timer_init(void); /* Architecture specific - can be in arch/x86/cpu/, arch/x86/lib/, or $(BOARD)/ */ int dram_init_f(void); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index c61447978..f66ad3074 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -31,7 +31,7 @@ COBJS-y += gcc.o COBJS-y += init_helpers.o COBJS-y += interrupts.o COBJS-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o -COBJS-$(CONFIG_SYS_GENERIC_TIMER) += pcat_timer.o +COBJS-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o COBJS-$(CONFIG_PCI) += pci_type1.o COBJS-y += relocate.o COBJS-y += physmem.o diff --git a/arch/x86/lib/pcat_timer.c b/arch/x86/lib/pcat_timer.c index b0b6637f3..1ca3eb9e9 100644 --- a/arch/x86/lib/pcat_timer.c +++ b/arch/x86/lib/pcat_timer.c @@ -24,83 +24,20 @@ #include #include #include -#include -#include -#define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */ #define TIMER2_VALUE 0x0a8e /* 440Hz */ -static int timer_init_done; - -int timer_init(void) +int pcat_timer_init(void) { - /* initialize timer 0 and 2 - * - * Timer 0 is used to increment system_tick 1000 times/sec - * Timer 1 was used for DRAM refresh in early PC's - * Timer 2 is used to drive the speaker + /* + * initialize 2, used to drive the speaker * (to start a beep: write 3 to port 0x61, * to stop it again: write 0) */ - outb(PIT_CMD_CTR0 | PIT_CMD_BOTH | PIT_CMD_MODE2, - PIT_BASE + PIT_COMMAND); - outb(TIMER0_VALUE & 0xff, PIT_BASE + PIT_T0); - outb(TIMER0_VALUE >> 8, PIT_BASE + PIT_T0); - outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3, PIT_BASE + PIT_COMMAND); outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2); outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2); - irq_install_handler(0, timer_isr, NULL); - unmask_irq(0); - - timer_init_done = 1; - return 0; } - -static u16 read_pit(void) -{ - u8 low; - - outb(PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND); - low = inb(PIT_BASE + PIT_T0); - - return (inb(PIT_BASE + PIT_T0) << 8) | low; -} - -/* this is not very exact */ -void __udelay(unsigned long usec) -{ - int counter; - int wraps; - - if (timer_init_done) { - counter = read_pit(); - wraps = usec / 1000; - usec = usec % 1000; - - usec *= 1194; - usec /= 1000; - usec += counter; - - while (usec > 1194) { - usec -= 1194; - wraps++; - } - - while (1) { - int new_count = read_pit(); - - if (((new_count < usec) && !wraps) || wraps < 0) - break; - - if (new_count > counter) - wraps--; - - counter = new_count; - } - } - -} diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c index d931e5f5e..c509801f9 100644 --- a/arch/x86/lib/tsc_timer.c +++ b/arch/x86/lib/tsc_timer.c @@ -98,6 +98,10 @@ void __udelay(unsigned long usec) int timer_init(void) { - /* Nothing to do here - the timer needs no init */ +#ifdef CONFIG_SYS_PCAT_TIMER + /* Set up the PCAT timer if required */ + pcat_timer_init(); +#endif + return 0; } diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 99408dcc5..7953ec615 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -235,6 +235,7 @@ #define CONFIG_SYS_X86_TSC_TIMER #define CONFIG_SYS_PCAT_INTERRUPTS +#define CONFIG_SYS_PCAT_TIMER #define CONFIG_SYS_NUM_IRQS 16 /*----------------------------------------------------------------------- -- cgit v1.2.3-70-g09d2