From 01a0f5a1ebba7eeccf13fc5992ed59e8614fd58a Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:14 +0000 Subject: cosmetic: checkpatch cleanup of arch/x86/cpu/sc520/*.c Signed-off-by: Graeme Russ --- arch/x86/cpu/sc520/sc520_pci.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) (limited to 'arch/x86/cpu/sc520/sc520_pci.c') diff --git a/arch/x86/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c index e26793ab1..a13798f1f 100644 --- a/arch/x86/cpu/sc520/sc520_pci.c +++ b/arch/x86/cpu/sc520/sc520_pci.c @@ -70,26 +70,28 @@ int pci_sc520_set_irq(int pci_pin, int irq) debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); - if (irq < 0 || irq > 15) { + if (irq < 0 || irq > 15) return -1; /* illegal irq */ - } - if (pci_pin < 0 || pci_pin > 15) { + if (pci_pin < 0 || pci_pin > 15) return -1; /* illegal pci int pin */ - } /* first disable any non-pci interrupt source that use * this level */ /* PCI interrupt mapping (A through D)*/ - for (i=0; i<=3 ;i++) { - if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority) + for (i = 0; i <= 3 ; i++) { + tmpb = readb(&sc520_mmcr->pci_int_map[i]); + + if (tmpb == sc520_irq[irq].priority) writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]); } /* GP IRQ interrupt mapping */ - for (i=0; i<=10 ;i++) { - if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority) + for (i = 0; i <= 10 ; i++) { + tmpb = readb(&sc520_mmcr->gp_int_map[i]); + + if (tmpb == sc520_irq[irq].priority) writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]); } @@ -102,10 +104,12 @@ int pci_sc520_set_irq(int pci_pin, int irq) if (pci_pin < 4) { /* PCI INTA-INTD */ /* route the interrupt */ - writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]); + writeb(sc520_irq[irq].priority, + &sc520_mmcr->pci_int_map[pci_pin]); } else { /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ - writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]); + writeb(sc520_irq[irq].priority, + &sc520_mmcr->gp_int_map[pci_pin - 4]); /* also set the polarity in this case */ tmpw = readw(&sc520_mmcr->intpinpol); -- cgit v1.2.3-70-g09d2 From 1cfcf0370132315d6eee375afdf7207ff60a07e0 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:22 +0000 Subject: x86: Misc PCI touchups Signed-off-by: Graeme Russ --- arch/x86/cpu/sc520/sc520_pci.c | 4 +--- arch/x86/include/asm/pci.h | 2 +- arch/x86/lib/pci_type1.c | 10 +++++++--- 3 files changed, 9 insertions(+), 7 deletions(-) (limited to 'arch/x86/cpu/sc520/sc520_pci.c') diff --git a/arch/x86/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c index a13798f1f..52d07c119 100644 --- a/arch/x86/cpu/sc520/sc520_pci.c +++ b/arch/x86/cpu/sc520/sc520_pci.c @@ -130,9 +130,7 @@ void pci_sc520_init(struct pci_controller *hose) hose->last_busno = 0xff; hose->region_count = pci_set_regions(hose); - pci_setup_type1(hose, - SC520_REG_ADDR, - SC520_REG_DATA); + pci_setup_type1(hose); pci_register_hose(hose); diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index c09078eb8..37cc7e3a0 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -29,7 +29,7 @@ #define DEFINE_PCI_DEVICE_TABLE(_table) \ const struct pci_device_id _table[] -void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); +void pci_setup_type1(struct pci_controller *hose); int pci_enable_legacy_video_ports(struct pci_controller* hose); int pci_shadow_rom(pci_dev_t dev, unsigned char *dest); void pci_remove_rom_window(struct pci_controller* hose, u32 addr); diff --git a/arch/x86/lib/pci_type1.c b/arch/x86/lib/pci_type1.c index 6fc4df47d..a25fa051d 100644 --- a/arch/x86/lib/pci_type1.c +++ b/arch/x86/lib/pci_type1.c @@ -50,7 +50,11 @@ TYPE1_PCI_OP(write, byte, u8, outb, 3) TYPE1_PCI_OP(write, word, u16, outw, 2) TYPE1_PCI_OP(write, dword, u32, outl, 0) -void pci_setup_type1(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) +/* bus mapping constants (used for PCI core initialization) */ +#define PCI_REG_ADDR 0x00000cf8 +#define PCI_REG_DATA 0x00000cfc + +void pci_setup_type1(struct pci_controller *hose) { pci_set_ops(hose, type1_read_config_byte, @@ -60,6 +64,6 @@ void pci_setup_type1(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) type1_write_config_word, type1_write_config_dword); - hose->cfg_addr = (unsigned int *)cfg_addr; - hose->cfg_data = (unsigned char *)cfg_data; + hose->cfg_addr = (unsigned int *)PCI_REG_ADDR; + hose->cfg_data = (unsigned char *)PCI_REG_DATA; } -- cgit v1.2.3-70-g09d2