From d653244b12dbc4a954e1bdfd04222bbbaf67329c Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 27 Dec 2011 22:46:43 +1100 Subject: x86: Create weak init_cache() and default enable_caches() functions -- Changes for v2: - Tweaked commit title --- arch/x86/cpu/cpu.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'arch/x86/cpu/cpu.c') diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 8c3b92c78..e9bb0d770 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -139,6 +139,14 @@ int x86_cpu_init_f(void) int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f"))); int x86_cpu_init_r(void) +{ + /* Initialize core interrupt and exception functionality of CPU */ + cpu_init_interrupts(); + return 0; +} +int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); + +void x86_enable_caches(void) { const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD); @@ -147,12 +155,16 @@ int x86_cpu_init_r(void) "andl %0, %%eax\n" "movl %%eax, %%cr0\n" "wbinvd\n" : : "i" (nw_cd_rst) : "eax"); +} +void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); + +int x86_init_cache(void) +{ + enable_caches(); - /* Initialize core interrupt and exception functionality of CPU */ - cpu_init_interrupts(); return 0; } -int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); +int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { -- cgit v1.2.3-70-g09d2