From 6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:08 +0000 Subject: powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/fdt.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/cpu/mpc85xx/fdt.c') diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index a0a9b4c5a..d54527aa4 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -220,12 +220,19 @@ static inline void ft_fixup_l2cache(void *blob) /* we dont bother w/L3 since no platform of this type has one */ } -#elif defined(CONFIG_BACKSIDE_L2_CACHE) +#elif defined(CONFIG_BACKSIDE_L2_CACHE) || \ + defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) static inline void ft_fixup_l2cache(void *blob) { int off, l2_off, l3_off = -1; u32 *ph; +#ifdef CONFIG_BACKSIDE_L2_CACHE u32 l2cfg0 = mfspr(SPRN_L2CFG0); +#else + struct ccsr_cluster_l2 *l2cache = + (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2); + u32 l2cfg0 = in_be32(&l2cache->l2cfg0); +#endif u32 size, line_size, num_ways, num_sets; int has_l2 = 1; @@ -257,7 +264,12 @@ static inline void ft_fixup_l2cache(void *blob) if (has_l2) { #ifdef CONFIG_SYS_CACHE_STASHING u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + /* Only initialize every eighth thread */ + if (reg && !((*reg) % 8)) +#else if (reg) +#endif fdt_setprop_cell(blob, l2_off, "cache-stash-id", (*reg * 2) + 32 + 1); #endif -- cgit v1.2.3-70-g09d2