From 2f848f97d7b27a88135de98aae76531a6fdd44e6 Mon Sep 17 00:00:00 2001 From: Shruti Kanetkar Date: Thu, 15 Aug 2013 11:25:37 -0500 Subject: powerpc: Use print_size() where appropriate Makes the startup output more consistent Signed-off-by: Shruti Kanetkar Acked-by: Andy Fleming Acked-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2d65157c7..565c28159 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -167,7 +167,8 @@ static void enable_cpc(void) } - printf("Corenet Platform Cache: %d KB enabled\n", size); + puts("Corenet Platform Cache: "); + print_size(size * 1024, " enabled\n"); } static void invalidate_cpc(void) @@ -526,13 +527,14 @@ int cpu_init_r(void) if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) ; - printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); + print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); } skip_l2: #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) if (l2cache->l2csr0 & L2CSR0_L2E) - printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64); + print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, + " enabled\n"); enable_cluster_l2(); #else -- cgit v1.2.3-70-g09d2 From 6b44d9e5b79948a73f9fae4b84c21f62224fa46b Mon Sep 17 00:00:00 2001 From: Shruti Kanetkar Date: Thu, 15 Aug 2013 11:25:38 -0500 Subject: powerpcv2: Print hardcoded size like print_size() does Makes the startup output more consistent Signed-off-by: Shruti Kanetkar Acked-by: Andy Fleming Acked-by: Stefan Roese Acked-by: York Sun --- arch/powerpc/cpu/mpc824x/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 14 +++++++------- arch/powerpc/cpu/mpc86xx/cpu.c | 6 +++--- arch/powerpc/cpu/mpc8xx/cpu.c | 6 +++--- arch/powerpc/cpu/mpc8xx/video.c | 4 ++-- arch/powerpc/cpu/ppc4xx/cpu.c | 8 ++++---- 7 files changed, 21 insertions(+), 21 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c') diff --git a/arch/powerpc/cpu/mpc824x/cpu.c b/arch/powerpc/cpu/mpc824x/cpu.c index 7ed38c886..eaa4e8707 100644 --- a/arch/powerpc/cpu/mpc824x/cpu.c +++ b/arch/powerpc/cpu/mpc824x/cpu.c @@ -45,7 +45,7 @@ int checkcpu (void) return -1; /* no valid CPU revision info */ } - printf (" at %s MHz: ", strmhz (buf, clock)); + printf(" at %s MHz: ", strmhz(buf, clock)); print_size(checkicache(), " I-Cache "); print_size(checkdcache(), " D-Cache\n"); diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index b77964a4c..1a0196c7c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -210,7 +210,7 @@ int checkcpu (void) printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme)); #endif - puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); + puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); #ifdef CONFIG_FSL_CORENET /* Display the RCW, so that no one gets confused as to what RCW diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 565c28159..c6e09ca90 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -458,28 +458,28 @@ int cpu_init_r(void) case 0x1: if (ver == SVR_8540 || ver == SVR_8560 || ver == SVR_8541 || ver == SVR_8555) { - puts("128 KB "); - /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ + puts("128 KiB "); + /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ cache_ctl = 0xc4000000; } else { - puts("256 KB "); + puts("256 KiB "); cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ } break; case 0x2: if (ver == SVR_8540 || ver == SVR_8560 || ver == SVR_8541 || ver == SVR_8555) { - puts("256 KB "); - /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ + puts("256 KiB "); + /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ cache_ctl = 0xc8000000; } else { - puts ("512 KB "); + puts("512 KiB "); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; } break; case 0x3: - puts("1024 KB "); + puts("1024 KiB "); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; break; diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c index ab3250ba4..30518544d 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu.c +++ b/arch/powerpc/cpu/mpc86xx/cpu.c @@ -85,8 +85,8 @@ checkcpu(void) sysinfo.freq_localbus); } - puts("L1: D-cache 32 KB enabled\n"); - puts(" I-cache 32 KB enabled\n"); + puts("L1: D-cache 32 KiB enabled\n"); + puts(" I-cache 32 KiB enabled\n"); puts("L2: "); if (get_l2cr() & 0x80000000) { @@ -95,7 +95,7 @@ checkcpu(void) #elif defined(CONFIG_MPC8641) puts("512"); #endif - puts(" KB enabled\n"); + puts(" KiB enabled\n"); } else { puts("Disabled\n"); } diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 63668b6a6..5c96b5fe1 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -202,7 +202,7 @@ static int check_CPU (long clock, uint pvr, uint immr) printf ("unknown MPC857 (0x%08x)", k); #endif - printf (" at %s MHz: ", strmhz (buf, clock)); + printf(" at %s MHz: ", strmhz(buf, clock)); print_size(checkicache(), " I-Cache "); print_size(checkdcache(), " D-Cache"); @@ -263,7 +263,7 @@ static int check_CPU (long clock, uint pvr, uint immr) if (suf) printf ("PPC823ZTnn%s", suf); - printf (" at %s MHz: ", strmhz (buf, clock)); + printf(" at %s MHz: ", strmhz(buf, clock)); print_size(checkicache(), " I-Cache "); print_size(checkdcache(), " D-Cache"); @@ -319,7 +319,7 @@ static int check_CPU (long clock, uint pvr, uint immr) default: printf ("unknown MPC850 (0x%08x)", k); } - printf (" at %s MHz: ", strmhz (buf, clock)); + printf(" at %s MHz: ", strmhz(buf, clock)); print_size(checkicache(), " I-Cache "); print_size(checkdcache(), " D-Cache"); diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c index 02a046789..fc351585b 100644 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ b/arch/powerpc/cpu/mpc8xx/video.c @@ -1176,7 +1176,7 @@ static void *video_logo (void) #ifndef CONFIG_FADS /* all normal boards */ /* leave one blank line */ - sprintf (info, "MPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash", + sprintf(info, "MPC823 CPU at %s MHz, %ld MiB RAM, %ld MiB Flash", strmhz(temp, gd->cpu_clk), gd->ram_size >> 20, gd->bd->bi_flashsize >> 20 ); @@ -1187,7 +1187,7 @@ static void *video_logo (void) video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, info); - sprintf (info, "2MB FLASH - 8MB DRAM - 4MB SRAM"); + sprintf(info, "2MiB FLASH - 8MiB DRAM - 4MiB SRAM"); video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, info); #endif diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index fe050985e..78d212d56 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -647,12 +647,12 @@ int checkcpu (void) #endif #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) - printf (" 16 kB I-Cache 16 kB D-Cache"); + printf(" 16 KiB I-Cache 16 KiB D-Cache"); #elif defined(CONFIG_440) - printf (" 32 kB I-Cache 32 kB D-Cache"); + printf(" 32 KiB I-Cache 32 KiB D-Cache"); #else - printf (" 16 kB I-Cache %d kB D-Cache", - ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); + printf(" 16 KiB I-Cache %d KiB D-Cache", + ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); #endif #endif /* !defined(CONFIG_405) */ -- cgit v1.2.3-70-g09d2 From 424bf94273b2cd0171eca7ed5619b211f1b96d8f Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 15 Aug 2013 09:31:47 +0800 Subject: powerpc/sec: Add workaround for SEC A-003571 Multiple read/write transactions initiated by security engine may cause system to hang. Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang. Signed-off-by: Shengzhou Liu Acked-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 +++++++++- arch/powerpc/include/asm/config_mpc85xx.h | 1 + 3 files changed, 14 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c') diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index cbb443fd2..8a2a3ee76 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -245,6 +245,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts("Work-around for Erratum A006593 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 + if (IS_SVR_REV(svr, 1, 0)) + puts("Work-around for Erratum A003571 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 puts("Work-around for Erratum A-005812 enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index c6e09ca90..6036333ea 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -357,7 +357,9 @@ int cpu_init_r(void) extern int spin_table_compat; const char *spin; #endif - +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 + ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; +#endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) /* @@ -548,6 +550,12 @@ skip_l2: fsl_serdes_init(); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 +#define MCFGR_AXIPIPE 0x000000f0 + if (IS_SVR_REV(svr, 1, 0)) + clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 if (IS_SVR_REV(svr, 1, 0)) { int i; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index e1fc0f72c..d748cb62d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -131,6 +131,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 +#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 /* P1011 is single core version of P1020 */ -- cgit v1.2.3-70-g09d2