From ab48ca1a661b9ab8e3fee9fe2df65432b09ed073 Mon Sep 17 00:00:00 2001 From: Srikanth Srinivasan Date: Wed, 10 Feb 2010 17:32:43 +0800 Subject: ppc/p4080: Fix synchronous frequency calculations When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan Signed-off-by: Dave Liu Signed-off-by: Ed Swarthout Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/cpu.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 0cc6e0323..15b7b231e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2007-2009 Freescale Semiconductor, Inc. + * Copyright 2004,2007-2010 Freescale Semiconductor, Inc. * (C) Copyright 2002, 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -44,21 +44,17 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; -#ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_FSL_CORENET - u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) - >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; -#else +#ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; -#endif #else #ifdef CONFIG_FSL_CORENET - u32 ddr_sync = 0; + u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) + >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #else u32 ddr_ratio = 0; -#endif +#endif /* CONFIG_FSL_CORENET */ #endif /* CONFIG_DDR_CLK_FREQ */ int i; -- cgit v1.2.3-70-g09d2