From 133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 16 Sep 2013 12:49:31 -0700 Subject: powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/powerpc/cpu/mpc85xx/cmd_errata.c') diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index c441bd2f5..1e5a43f0e 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "fsl_corenet_serdes.h" @@ -245,6 +246,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts("Work-around for Erratum A006593 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) + puts("Work-around for Erratum A006379 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 if (IS_SVR_REV(svr, 1, 0)) puts("Work-around for Erratum A003571 enabled\n"); -- cgit v1.2.3-70-g09d2