From 5106ebfb00bb22353d2758e3ad1adf4058a4b02c Mon Sep 17 00:00:00 2001 From: mattis fjallstrom Date: Fri, 5 Jun 2015 12:15:23 -0700 Subject: Adding off-mode settings for unused pins. Change-Id: I22b6028976753549f32cfc629ff67e72e3f5a804 --- board/olio/h1/pinmux.h | 244 ++++++++++++++++++++++++------------------------- 1 file changed, 122 insertions(+), 122 deletions(-) diff --git a/board/olio/h1/pinmux.h b/board/olio/h1/pinmux.h index 50c93ac2a..23cfede2e 100644 --- a/board/olio/h1/pinmux.h +++ b/board/olio/h1/pinmux.h @@ -25,35 +25,35 @@ #define MUX_EVM() \ /* Design Status: NO ERRORS */\ -MUX_VAL(CONTROL_PADCONF_GPIO_112, (IEN | PD | M4 )) /* gpio_112 */\ -MUX_VAL(CONTROL_PADCONF_GPIO_113, (IEN | PD | M4 )) /* gpio_113 */\ -MUX_VAL(CONTROL_PADCONF_GPIO_114, (IEN | PD | M4 )) /* gpio_114 */\ +MUX_VAL(CONTROL_PADCONF_GPIO_112, (IEN | PD | M7| SB_PD)) /* gpio_112 - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_GPIO_113, (IEN | PD | M7 | SB_PD)) /* gpio_113 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPIO_114, (IEN | PD | M7 | SB_PD)) /* gpio_114 - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_GPIO_115, (IEN | PD | M4 )) /* gpio_115 */\ -MUX_VAL(CONTROL_PADCONF_GPIO_126, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPIO_127, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPIO_128, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPIO_129, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_D0, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_D3, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_D4, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | PD | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_GPIO_126, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPIO_127, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPIO_128, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPIO_129, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_CAM_D0, (IEN | PI | M7 )) /* safe_mode - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | PI | M7 )) /* safe_mode - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | PI | M7 )) /* safe_mode - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_CAM_D3, (IEN | PI | M7 )) /* safe_mode - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_CAM_D4, (IEN | PI | M7 )) /* safe_mode - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PD | M7 )) /* safe_mode - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PI | M7 )) /* safe_mode - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PI | M7 )) /* safe_mode - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | PI | M7 )) /* safe_mode - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | PI | M7 )) /* safe_mode - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PI | M7 )) /* safe_mode - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PI | M7 )) /* safe_mode - edit 2014-05-11 */\ +MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IEN | PD | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_CAM_VS, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IEN | PD | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IEN | PD | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IEN | PD | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IEN | PD | M7 )) /* safe_mode */\ @@ -72,80 +72,80 @@ MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IEN | PD | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IEN | PD | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IEN | PD | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IEN | PD | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IEN | PD | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PI | M4 )) /* gpio_93 */\ MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IEN | PU | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IEN | PU | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IEN | PU | M4 )) /* gpio_12 */\ -MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IEN | PU | M4 )) /* gpio_13 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PU | M4 )) /* gpio_14 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PU | M4 )) /* gpio_15 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PU | M4 )) /* gpio_16 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PU | M4 )) /* gpio_17 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PD | M4 )) /* gpio_18 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PD | M4 )) /* gpio_19 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PD | M4 )) /* gpio_20 */\ +MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_12 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_13 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_14 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_15 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_16 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_17 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_18 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_19 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_20 - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PD | M4 )) /* gpio_21 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PD | M4 )) /* gpio_22 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PD | M4 )) /* gpio_23 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IEN | PD | M4 )) /* gpio_24 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IEN | PD | M4 )) /* gpio_25 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PD | M4 )) /* gpio_26 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PD | M4 )) /* gpio_27 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PD | M4 )) /* gpio_28 */\ -MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PD | M4 )) /* gpio_29 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IDIS | PI | M0 )) /* gpmc_clk */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PU | M0 )) /* gpmc_d0 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PU | M0 )) /* gpmc_d1 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PU | M0 )) /* gpmc_d2 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PU | M0 )) /* gpmc_d3 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PU | M0 )) /* gpmc_d4 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PU | M0 )) /* gpmc_d5 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PU | M0 )) /* gpmc_d6 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PU | M0 )) /* gpmc_d7 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PU | M0 )) /* gpmc_d8 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PU | M0 )) /* gpmc_d9 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PU | M0 )) /* gpmc_d10 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PU | M0 )) /* gpmc_d11 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PU | M0 )) /* gpmc_d12 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PU | M0 )) /* gpmc_d13 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PU | M0 )) /* gpmc_d14 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PU | M0 )) /* gpmc_d15 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | PI | M0 )) /* gpmc_nadv_ale */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | PI | M0 )) /* gpmc_nbe0_cle */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | PI | M0 )) /* gpmc_ncs0 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IDIS | PI | M0 )) /* gpmc_ncs1 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | PI | M0 )) /* gpmc_noe */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | PI | M0 )) /* gpmc_nwe */\ -MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | PI | M0 )) /* gpmc_nwp */\ -MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | PU | M0 )) /* gpmc_wait0 */\ -MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | PU | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_22 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_23 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_24 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_25 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_26 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_27 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_28 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PD | M7 | SB_PD)) /* gpio_29 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PD | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IDIS | PI | M0 )) /* gpmc_clk - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PU | M0 | SB_PU)) /* gpmc_d0 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PU | M0 | SB_PU)) /* gpmc_d1 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PU | M0 | SB_PU)) /* gpmc_d2 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PU | M0 | SB_PU)) /* gpmc_d3 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PU | M0 | SB_PU)) /* gpmc_d4 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PU | M0 | SB_PU)) /* gpmc_d5 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PU | M0 | SB_PU)) /* gpmc_d6 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PU | M0 | SB_PU)) /* gpmc_d7 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PU | M0 | SB_PU)) /* gpmc_d8 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PU | M0 | SB_PU)) /* gpmc_d9 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PU | M0 | SB_PU)) /* gpmc_d10 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PU | M0 | SB_PU)) /* gpmc_d11 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PU | M0 | SB_PU)) /* gpmc_d12 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PU | M0 | SB_PU)) /* gpmc_d13 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PU | M0 | SB_PU)) /* gpmc_d14 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PU | M0 | SB_PU)) /* gpmc_d15 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | PI | M0 )) /* gpmc_nadv_ale - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | PI | M0 )) /* gpmc_nbe0_cle - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PD | M7 | SB_PD )) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | PI | M0 )) /* gpmc_ncs0 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IDIS | PI | M0 )) /* gpmc_ncs1 - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | PI | M0 )) /* gpmc_noe - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | PI | M0 )) /* gpmc_nwe - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | PI | M0 )) /* gpmc_nwp - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | PU | M0 | SB_PU)) /* gpmc_wait0 */\ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PD | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PD | M4 )) /* gpio_125 */\ MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PD | M4 )) /* gpio_130 */\ @@ -174,20 +174,20 @@ MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PD | M0 )) /* jtag_tck */\ MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PU | M0 )) /* jtag_tdi */\ MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | PI | M0 )) /* jtag_tdo */\ MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PU | M0 )) /* jtag_tms_tmsc */\ -MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | PD | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PD | M0 )) /* mcbsp2_clkx */\ MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PD | M0 )) /* mcbsp2_dr */\ MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IDIS | PD | M0 )) /* mcbsp2_dx */\ MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PD | M0 )) /* mcbsp2_fsx */\ MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IEN | PD | M0 )) /* mcbsp3_clkx */\ MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IEN | PD | M0 )) /* mcbsp3_dr */\ -MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PD | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PD | M0 )) /* mcbsp3_fsx */\ MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PD | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PD | M7 )) /* safe_mode */\ @@ -197,30 +197,30 @@ MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PD | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PU | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PU | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PU | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PD | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PD | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PU | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IDIS | PI | M4 )) /* gpio_180 */\ -MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PU | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PU | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PU | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IEN | PD | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PD | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | PI | M0 )) /* sdrc_a0 */\ MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | PI | M0 )) /* sdrc_a1 */\ MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | PI | M0 )) /* sdrc_a2 */\ @@ -295,9 +295,9 @@ MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | PI | M0 )) /* sys_boot3 */\ MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | PI | M0 )) /* sys_boot4 */\ MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | PI | M0 )) /* sys_boot5 */\ MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | PI | M0 )) /* sys_boot6 */\ -MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IEN | PD | M7 )) /* safe_mode */\ -MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | PI | M4 )) /* gpio_1 */\ +MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \ +MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | PD | M7 | SB_PD)) /* gpio_1 - edit 2014-05-11 */ \ MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PU | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PU | M0 )) /* sys_nreswarm */\ MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IEN | PD | M7 )) /* safe_mode */\ -- cgit v1.2.3-70-g09d2