diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/mpc7448hpc2.h | 290 | ||||
| -rw-r--r-- | include/tsi108.h | 250 |
2 files changed, 270 insertions, 270 deletions
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 24cc86beb..b13b699b5 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -24,12 +24,11 @@ * MA 02111-1307 USA */ -/**************************************************************** - * +/* * board specific configuration options for Freescale * MPC7448HPC2 (High-Performance Computing II) (Taiga) board * - ****************************************************************/ + */ #ifndef __CONFIG_H #define __CONFIG_H @@ -45,11 +44,11 @@ #define CONFIG_750FX /* this option to enable init of extended BATs */ #define CONFIG_ALTIVEC /* undef to disable */ -#define CFG_BOARD_NAME "MPC7448 HPC II" -#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" +#define CFG_BOARD_NAME "MPC7448 HPC II" +#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" -#define CFG_OCN_CLK 133000000 /* 133 MHz */ -#define CFG_CONFIG_BUS_CLK 133000000 +#define CFG_OCN_CLK 133000000 /* 133 MHz */ +#define CFG_CONFIG_BUS_CLK 133000000 #define CFG_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ @@ -63,10 +62,10 @@ /* Default MAC Addresses for on-chip GIGE Controller */ -#define CONFIG_ETHADDR 00:06:D2:00:00:01 +#define CONFIG_ETHADDR 00:06:D2:00:00:01 #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:06:D2:00:00:02 +#define CONFIG_ETH1ADDR 00:06:D2:00:00:02 #define CONFIG_ENV_OVERWRITE @@ -75,12 +74,12 @@ * (easy to change) */ -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ /*#define CFG_HUSH_PARSER */ #undef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " /* Pass open firmware flat tree */ #define CONFIG_OF_FLAT_TREE 1 @@ -99,29 +98,30 @@ * for your console driver. * * what to do: - * If you have hacked a serial cable onto the second DUART channel, change the CFG_DUART port from 1 - * to 0 below. + * If you have hacked a serial cable onto the second DUART channel, + * change the CFG_DUART port from 1 to 0 below. * */ -#define CONFIG_CONS_INDEX 1 +#define CONFIG_CONS_INDEX 1 #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK CFG_OCN_CLK * 8 -#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808) -#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08) +#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808) +#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08) #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #define CONFIG_ZERO_BOOTDELAY_CHECK #undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ +/* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" + * to mount root filesystem over NFS;echo" */ #if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ +#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " @@ -130,34 +130,34 @@ #undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_SERIAL "No. 1" +#define CONFIG_SERIAL "No. 1" /* Networking Configuration */ -#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */ +#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */ #define CONFIG_TSI108_ETH -#define CONFIG_TSI108_ETH_NUM_PORTS 2 +#define CONFIG_TSI108_ETH_NUM_PORTS 2 #define CONFIG_NET_MULTI -#define CONFIG_IPADDR 172.27.234.48 -#define CONFIG_SERVERIP 172.27.234.10 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_GATEWAYIP 172.27.255.254 +#define CONFIG_IPADDR 172.27.234.48 +#define CONFIG_SERVERIP 172.27.234.10 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_GATEWAYIP 172.27.255.254 -#define CONFIG_BOOTFILE zImage.initrd.elf -#define CONFIG_LOADADDR 0x400000 +#define CONFIG_BOOTFILE zImage.initrd.elf +#define CONFIG_LOADADDR 0x400000 /*-------------------------------------------------------------------------- */ -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ @@ -178,59 +178,59 @@ /*set date in u-boot*/ #define CONFIG_RTC_M48T35A -#define CFG_NVRAM_BASE_ADDR 0xfc000000 -#define CFG_NVRAM_SIZE 0x8000 +#define CFG_NVRAM_BASE_ADDR 0xfc000000 +#define CFG_NVRAM_SIZE 0x8000 /* * Miscellaneous configurable options */ -#define CONFIG_VERSION_VARIABLE 1 +#define CONFIG_VERSION_VARIABLE 1 #define CONFIG_TSI108_I2C -#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ /* #define CFG_DRAM_TEST - * DRAM tests - * CFG_DRAM_TEST - enables the following tests. + * DRAM tests + * CFG_DRAM_TEST - enables the following tests. * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. + * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines + * Environment variable 'test_dram_data' must be + * set to 'y'. + * CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word + * is uniquely addressable. Environment variable + * 'test_dram_address' must be set to 'y'. + * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. + * This test takes about 6 minutes to test 64 MB. + * Environment variable 'test_dram_walk' must be + * set to 'y'. */ #undef CFG_DRAM_TEST -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ #if defined(CFG_DRAM_TEST) #define CFG_DRAM_TEST_DATA #define CFG_DRAM_TEST_ADDRESS #define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ +#endif /* CFG_DRAM_TEST */ -#define CFG_LOAD_ADDR 0x00400000 /* default load address */ +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ /* * Low Level Configuration Settings @@ -246,12 +246,12 @@ * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS * To an unused memory region. The stack will remain in cache until RAM * is initialized -*/ + */ #undef CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ -#define CFG_INIT_RAM_END 0x4000 /* larger space - we have SDRAM initialized */ +#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ +#define CFG_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_SIZE 128/* size in bytes reserved for init data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) /*----------------------------------------------------------------------- @@ -260,54 +260,54 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ -#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ +#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ +#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ -#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ -#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ +#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ +#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ -#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ +#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ -#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ +#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ -#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ +#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ -#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */ -#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ +#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */ +#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 +#define PCI0_IO_BASE_BOOTM 0xfd000000 -#define CFG_RESET_ADDRESS 0x3fffff00 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */ -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ +#define CFG_RESET_ADDRESS 0x3fffff00 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ /* Peripheral Device section */ -/******************************************************* +/* * Resources on the Tsi108 - *******************************************************/ + */ -#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ -#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ +#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ +#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ #define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */ #undef DISABLE_PBM -/*----------------------------------------------------------------------- +/* * PCI stuff - *----------------------------------------------------------------------- + * */ #define CONFIG_PCI /* include pci support */ #define CONFIG_TSI108_PCI /* include tsi108 pci support */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -315,20 +315,20 @@ /* PCI MEMORY MAP section */ /* PCI view of System Memory */ -#define CFG_PCI_MEMORY_BUS 0x00000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x80000000 +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 /* PCI Memory Space */ -#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) -#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) //CFG_PCI_MEM32_BASE = 0xE0000000 -#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ +#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) +#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) /* 0xE0000000 */ +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ /* PCI I/O Space */ -#define CFG_PCI_IO_BUS 0x00000000 -#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ +#define CFG_PCI_IO_BUS 0x00000000 +#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ -#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */ +#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */ #define _IO_BASE 0x00000000 /* points to PCI I/O space */ @@ -336,91 +336,91 @@ #define CFG_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ #define CFG_PCI_CFG_SIZE 0x01000000 /* 16MB */ -#define CFG_IBAT0U 0xFE0003FF -#define CFG_IBAT0L 0xFE000002 +#define CFG_IBAT0U 0xFE0003FF +#define CFG_IBAT0L 0xFE000002 -#define CFG_IBAT1U 0x00007FFF -#define CFG_IBAT1L 0x00000012 +#define CFG_IBAT1U 0x00007FFF +#define CFG_IBAT1L 0x00000012 -#define CFG_IBAT2U 0x80007FFF -#define CFG_IBAT2L 0x80000022 +#define CFG_IBAT2U 0x80007FFF +#define CFG_IBAT2L 0x80000022 -#define CFG_IBAT3U 0x00000000 -#define CFG_IBAT3L 0x00000000 +#define CFG_IBAT3U 0x00000000 +#define CFG_IBAT3L 0x00000000 -#define CFG_IBAT4U 0x00000000 -#define CFG_IBAT4L 0x00000000 +#define CFG_IBAT4U 0x00000000 +#define CFG_IBAT4L 0x00000000 -#define CFG_IBAT5U 0x00000000 -#define CFG_IBAT5L 0x00000000 +#define CFG_IBAT5U 0x00000000 +#define CFG_IBAT5L 0x00000000 -#define CFG_IBAT6U 0x00000000 -#define CFG_IBAT6L 0x00000000 +#define CFG_IBAT6U 0x00000000 +#define CFG_IBAT6L 0x00000000 -#define CFG_IBAT7U 0x00000000 -#define CFG_IBAT7L 0x00000000 +#define CFG_IBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 -#define CFG_DBAT0U 0xE0003FFF -#define CFG_DBAT0L 0xE000002A +#define CFG_DBAT0U 0xE0003FFF +#define CFG_DBAT0L 0xE000002A -#define CFG_DBAT1U 0x00007FFF -#define CFG_DBAT1L 0x00000012 +#define CFG_DBAT1U 0x00007FFF +#define CFG_DBAT1L 0x00000012 -#define CFG_DBAT2U 0x00000000 -#define CFG_DBAT2L 0x00000000 +#define CFG_DBAT2U 0x00000000 +#define CFG_DBAT2L 0x00000000 -#define CFG_DBAT3U 0xC0000003 -#define CFG_DBAT3L 0xC000002A +#define CFG_DBAT3U 0xC0000003 +#define CFG_DBAT3L 0xC000002A -#define CFG_DBAT4U 0x00000000 -#define CFG_DBAT4L 0x00000000 +#define CFG_DBAT4U 0x00000000 +#define CFG_DBAT4L 0x00000000 -#define CFG_DBAT5U 0x00000000 -#define CFG_DBAT5L 0x00000000 +#define CFG_DBAT5U 0x00000000 +#define CFG_DBAT5L 0x00000000 -#define CFG_DBAT6U 0x00000000 -#define CFG_DBAT6L 0x00000000 +#define CFG_DBAT6U 0x00000000 +#define CFG_DBAT6L 0x00000000 -#define CFG_DBAT7U 0x00000000 -#define CFG_DBAT7L 0x00000000 +#define CFG_DBAT7U 0x00000000 +#define CFG_DBAT7L 0x00000000 /* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x51 -#define DIMM1_I2C_ADDR 0x52 +#define DIMM0_I2C_ADDR 0x51 +#define DIMM1_I2C_ADDR 0x52 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */ -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ +#define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */ +#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_CFI_SWAP -#define PHYS_FLASH_SIZE 0x01000000 -#define CFG_MAX_FLASH_SECT (128) +#define PHYS_FLASH_SIZE 0x01000000 +#define CFG_MAX_FLASH_SECT (128) #define CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_ADDR 0xFC000000 +#define CFG_ENV_ADDR 0xFC000000 -#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ +#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- @@ -429,16 +429,16 @@ */ #undef CFG_L2 -#define L2_INIT 0 -#define L2_ENABLE (L2_INIT | L2CR_L2E) +#define L2_INIT 0 +#define L2_ENABLE (L2_INIT | L2CR_L2E) /* * Internal Definitions * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_EXCEPTION_AFTER_RELOCATE #define CFG_SERIAL_HANG_IN_EXCEPTION -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/tsi108.h b/include/tsi108.h index 072daa03c..ba62e7abe 100644 --- a/include/tsi108.h +++ b/include/tsi108.h @@ -31,191 +31,191 @@ #ifndef _TSI108_H_ #define _TSI108_H_ -#define TSI108_HLP_REG_OFFSET (0x0000) -#define TSI108_PCI_REG_OFFSET (0x1000) -#define TSI108_CLK_REG_OFFSET (0x2000) -#define TSI108_PB_REG_OFFSET (0x3000) -#define TSI108_SD_REG_OFFSET (0x4000) -#define TSI108_MPIC_REG_OFFSET (0x7400) +#define TSI108_HLP_REG_OFFSET (0x0000) +#define TSI108_PCI_REG_OFFSET (0x1000) +#define TSI108_CLK_REG_OFFSET (0x2000) +#define TSI108_PB_REG_OFFSET (0x3000) +#define TSI108_SD_REG_OFFSET (0x4000) +#define TSI108_MPIC_REG_OFFSET (0x7400) -#define PB_ID (0x000) -#define PB_RSR (0x004) -#define PB_BUS_MS_SELECT (0x008) -#define PB_ISR (0x00C) -#define PB_ARB_CTRL (0x018) -#define PB_PVT_CTRL2 (0x034) -#define PB_SCR (0x400) -#define PB_ERRCS (0x404) -#define PB_AERR (0x408) -#define PB_REG_BAR (0x410) -#define PB_OCN_BAR1 (0x414) -#define PB_OCN_BAR2 (0x418) -#define PB_SDRAM_BAR1 (0x41C) -#define PB_SDRAM_BAR2 (0x420) -#define PB_MCR (0xC00) -#define PB_MCMD (0xC04) +#define PB_ID (0x000) +#define PB_RSR (0x004) +#define PB_BUS_MS_SELECT (0x008) +#define PB_ISR (0x00C) +#define PB_ARB_CTRL (0x018) +#define PB_PVT_CTRL2 (0x034) +#define PB_SCR (0x400) +#define PB_ERRCS (0x404) +#define PB_AERR (0x408) +#define PB_REG_BAR (0x410) +#define PB_OCN_BAR1 (0x414) +#define PB_OCN_BAR2 (0x418) +#define PB_SDRAM_BAR1 (0x41C) +#define PB_SDRAM_BAR2 (0x420) +#define PB_MCR (0xC00) +#define PB_MCMD (0xC04) -#define HLP_B0_ADDR (0x000) -#define HLP_B1_ADDR (0x010) -#define HLP_B2_ADDR (0x020) -#define HLP_B3_ADDR (0x030) +#define HLP_B0_ADDR (0x000) +#define HLP_B1_ADDR (0x010) +#define HLP_B2_ADDR (0x020) +#define HLP_B3_ADDR (0x030) -#define HLP_B0_MASK (0x004) -#define HLP_B1_MASK (0x014) -#define HLP_B2_MASK (0x024) -#define HLP_B3_MASK (0x034) +#define HLP_B0_MASK (0x004) +#define HLP_B1_MASK (0x014) +#define HLP_B2_MASK (0x024) +#define HLP_B3_MASK (0x034) -#define HLP_B0_CTRL0 (0x008) -#define HLP_B1_CTRL0 (0x018) -#define HLP_B2_CTRL0 (0x028) -#define HLP_B3_CTRL0 (0x038) +#define HLP_B0_CTRL0 (0x008) +#define HLP_B1_CTRL0 (0x018) +#define HLP_B2_CTRL0 (0x028) +#define HLP_B3_CTRL0 (0x038) -#define HLP_B0_CTRL1 (0x00C) -#define HLP_B1_CTRL1 (0x01C) -#define HLP_B2_CTRL1 (0x02C) -#define HLP_B3_CTRL1 (0x03C) +#define HLP_B0_CTRL1 (0x00C) +#define HLP_B1_CTRL1 (0x01C) +#define HLP_B2_CTRL1 (0x02C) +#define HLP_B3_CTRL1 (0x03C) -#define PCI_CSR (0x004) -#define PCI_P2O_BAR0 (0x010) -#define PCI_P2O_BAR0_UPPER (0x014) -#define PCI_P2O_BAR2 (0x018) -#define PCI_P2O_BAR2_UPPER (0x01C) -#define PCI_P2O_BAR3 (0x020) -#define PCI_P2O_BAR3_UPPER (0x024) +#define PCI_CSR (0x004) +#define PCI_P2O_BAR0 (0x010) +#define PCI_P2O_BAR0_UPPER (0x014) +#define PCI_P2O_BAR2 (0x018) +#define PCI_P2O_BAR2_UPPER (0x01C) +#define PCI_P2O_BAR3 (0x020) +#define PCI_P2O_BAR3_UPPER (0x024) -#define PCI_MISC_CSR (0x040) -#define PCI_P2O_PAGE_SIZES (0x04C) +#define PCI_MISC_CSR (0x040) +#define PCI_P2O_PAGE_SIZES (0x04C) -#define PCI_PCIX_STAT (0x0F4) +#define PCI_PCIX_STAT (0x0F4) -#define PCI_IRP_STAT (0x184) +#define PCI_IRP_STAT (0x184) -#define PCI_PFAB_BAR0 (0x204) -#define PCI_PFAB_BAR0_UPPER (0x208) -#define PCI_PFAB_IO (0x20C) -#define PCI_PFAB_IO_UPPER (0x210) +#define PCI_PFAB_BAR0 (0x204) +#define PCI_PFAB_BAR0_UPPER (0x208) +#define PCI_PFAB_IO (0x20C) +#define PCI_PFAB_IO_UPPER (0x210) -#define PCI_PFAB_MEM32 (0x214) -#define PCI_PFAB_MEM32_REMAP (0x218) -#define PCI_PFAB_MEM32_MASK (0x21C) +#define PCI_PFAB_MEM32 (0x214) +#define PCI_PFAB_MEM32_REMAP (0x218) +#define PCI_PFAB_MEM32_MASK (0x21C) -#define CG_PLL0_CTRL0 (0x210) -#define CG_PLL0_CTRL1 (0x214) -#define CG_PLL1_CTRL0 (0x220) -#define CG_PLL1_CTRL1 (0x224) -#define CG_PWRUP_STATUS (0x234) +#define CG_PLL0_CTRL0 (0x210) +#define CG_PLL0_CTRL1 (0x214) +#define CG_PLL1_CTRL0 (0x220) +#define CG_PLL1_CTRL1 (0x224) +#define CG_PWRUP_STATUS (0x234) #define MPIC_CSR(n) (0x30C + (n * 0x40)) -#define SD_CTRL (0x000) -#define SD_STATUS (0x004) -#define SD_TIMING (0x008) -#define SD_REFRESH (0x00C) -#define SD_INT_STATUS (0x010) -#define SD_INT_ENABLE (0x014) -#define SD_INT_SET (0x018) -#define SD_D0_CTRL (0x020) -#define SD_D1_CTRL (0x024) -#define SD_D0_BAR (0x028) -#define SD_D1_BAR (0x02C) -#define SD_ECC_CTRL (0x040) -#define SD_DLL_STATUS (0x250) +#define SD_CTRL (0x000) +#define SD_STATUS (0x004) +#define SD_TIMING (0x008) +#define SD_REFRESH (0x00C) +#define SD_INT_STATUS (0x010) +#define SD_INT_ENABLE (0x014) +#define SD_INT_SET (0x018) +#define SD_D0_CTRL (0x020) +#define SD_D1_CTRL (0x024) +#define SD_D0_BAR (0x028) +#define SD_D1_BAR (0x02C) +#define SD_ECC_CTRL (0x040) +#define SD_DLL_STATUS (0x250) -#define TS_SD_CTRL_ENABLE (1 << 31) +#define TS_SD_CTRL_ENABLE (1 << 31) -#define PB_ERRCS_ES (1 << 1) -#define PB_ISR_PBS_RD_ERR (1 << 8) -#define PCI_IRP_STAT_P_CSR (1 << 23) +#define PB_ERRCS_ES (1 << 1) +#define PB_ISR_PBS_RD_ERR (1 << 8) +#define PCI_IRP_STAT_P_CSR (1 << 23) -/* +/* * I2C : Register address offset definitions */ -#define I2C_CNTRL1 (0x00000000) -#define I2C_CNTRL2 (0x00000004) -#define I2C_RD_DATA (0x00000008) -#define I2C_TX_DATA (0x0000000c) +#define I2C_CNTRL1 (0x00000000) +#define I2C_CNTRL2 (0x00000004) +#define I2C_RD_DATA (0x00000008) +#define I2C_TX_DATA (0x0000000c) /* * I2C : Register Bit Masks and Reset Values - * definitions for every register + * definitions for every register */ /* I2C_CNTRL1 : Reset Value */ -#define I2C_CNTRL1_RESET_VALUE (0x0000000a) +#define I2C_CNTRL1_RESET_VALUE (0x0000000a) /* I2C_CNTRL1 : Register Bits Masks Definitions */ -#define I2C_CNTRL1_DEVCODE (0x0000000f) -#define I2C_CNTRL1_PAGE (0x00000700) -#define I2C_CNTRL1_BYTADDR (0x00ff0000) -#define I2C_CNTRL1_I2CWRITE (0x01000000) +#define I2C_CNTRL1_DEVCODE (0x0000000f) +#define I2C_CNTRL1_PAGE (0x00000700) +#define I2C_CNTRL1_BYTADDR (0x00ff0000) +#define I2C_CNTRL1_I2CWRITE (0x01000000) /* I2C_CNTRL1 : Read/Write Bit Mask Definition */ -#define I2C_CNTRL1_RWMASK (0x01ff070f) +#define I2C_CNTRL1_RWMASK (0x01ff070f) /* I2C_CNTRL1 : Unused/Reserved bits Definition */ -#define I2C_CNTRL1_RESERVED (0xfe00f8f0) +#define I2C_CNTRL1_RESERVED (0xfe00f8f0) /* I2C_CNTRL2 : Reset Value */ -#define I2C_CNTRL2_RESET_VALUE (0x00000000) +#define I2C_CNTRL2_RESET_VALUE (0x00000000) /* I2C_CNTRL2 : Register Bits Masks Definitions */ -#define I2C_CNTRL2_SIZE (0x00000003) -#define I2C_CNTRL2_LANE (0x0000000c) -#define I2C_CNTRL2_MULTIBYTE (0x00000010) -#define I2C_CNTRL2_START (0x00000100) -#define I2C_CNTRL2_WR_STATUS (0x00010000) -#define I2C_CNTRL2_RD_STATUS (0x00020000) -#define I2C_CNTRL2_I2C_TO_ERR (0x04000000) -#define I2C_CNTRL2_I2C_CFGERR (0x08000000) -#define I2C_CNTRL2_I2C_CMPLT (0x10000000) +#define I2C_CNTRL2_SIZE (0x00000003) +#define I2C_CNTRL2_LANE (0x0000000c) +#define I2C_CNTRL2_MULTIBYTE (0x00000010) +#define I2C_CNTRL2_START (0x00000100) +#define I2C_CNTRL2_WR_STATUS (0x00010000) +#define I2C_CNTRL2_RD_STATUS (0x00020000) +#define I2C_CNTRL2_I2C_TO_ERR (0x04000000) +#define I2C_CNTRL2_I2C_CFGERR (0x08000000) +#define I2C_CNTRL2_I2C_CMPLT (0x10000000) /* I2C_CNTRL2 : Read/Write Bit Mask Definition */ -#define I2C_CNTRL2_RWMASK (0x0000011f) +#define I2C_CNTRL2_RWMASK (0x0000011f) /* I2C_CNTRL2 : Unused/Reserved bits Definition */ -#define I2C_CNTRL2_RESERVED (0xe3fcfee0) +#define I2C_CNTRL2_RESERVED (0xe3fcfee0) /* I2C_RD_DATA : Reset Value */ -#define I2C_RD_DATA_RESET_VALUE (0x00000000) +#define I2C_RD_DATA_RESET_VALUE (0x00000000) /* I2C_RD_DATA : Register Bits Masks Definitions */ -#define I2C_RD_DATA_RBYTE0 (0x000000ff) -#define I2C_RD_DATA_RBYTE1 (0x0000ff00) -#define I2C_RD_DATA_RBYTE2 (0x00ff0000) -#define I2C_RD_DATA_RBYTE3 (0xff000000) +#define I2C_RD_DATA_RBYTE0 (0x000000ff) +#define I2C_RD_DATA_RBYTE1 (0x0000ff00) +#define I2C_RD_DATA_RBYTE2 (0x00ff0000) +#define I2C_RD_DATA_RBYTE3 (0xff000000) /* I2C_RD_DATA : Read/Write Bit Mask Definition */ -#define I2C_RD_DATA_RWMASK (0x00000000) +#define I2C_RD_DATA_RWMASK (0x00000000) /* I2C_RD_DATA : Unused/Reserved bits Definition */ -#define I2C_RD_DATA_RESERVED (0x00000000) +#define I2C_RD_DATA_RESERVED (0x00000000) /* I2C_TX_DATA : Reset Value */ -#define I2C_TX_DATA_RESET_VALUE (0x00000000) +#define I2C_TX_DATA_RESET_VALUE (0x00000000) /* I2C_TX_DATA : Register Bits Masks Definitions */ -#define I2C_TX_DATA_TBYTE0 (0x000000ff) -#define I2C_TX_DATA_TBYTE1 (0x0000ff00) -#define I2C_TX_DATA_TBYTE2 (0x00ff0000) -#define I2C_TX_DATA_TBYTE3 (0xff000000) +#define I2C_TX_DATA_TBYTE0 (0x000000ff) +#define I2C_TX_DATA_TBYTE1 (0x0000ff00) +#define I2C_TX_DATA_TBYTE2 (0x00ff0000) +#define I2C_TX_DATA_TBYTE3 (0xff000000) /* I2C_TX_DATA : Read/Write Bit Mask Definition */ -#define I2C_TX_DATA_RWMASK (0xffffffff) +#define I2C_TX_DATA_RWMASK (0xffffffff) /* I2C_TX_DATA : Unused/Reserved bits Definition */ -#define I2C_TX_DATA_RESERVED (0x00000000) +#define I2C_TX_DATA_RESERVED (0x00000000) -#define TSI108_I2C_OFFSET 0x7000 /* register block offset for general use I2C channel */ -#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* register block offset for SPD I2C channel */ +#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */ +#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */ -#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */ +#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */ /* I2C status codes */ -#define TSI108_I2C_SUCCESS 0 -#define TSI108_I2C_PARAM_ERR 1 -#define TSI108_I2C_TIMEOUT_ERR 2 -#define TSI108_I2C_IF_BUSY 3 -#define TSI108_I2C_IF_ERROR 4 +#define TSI108_I2C_SUCCESS 0 +#define TSI108_I2C_PARAM_ERR 1 +#define TSI108_I2C_TIMEOUT_ERR 2 +#define TSI108_I2C_IF_BUSY 3 +#define TSI108_I2C_IF_ERROR 4 #endif /* _TSI108_H_ */ |