diff options
Diffstat (limited to 'include')
144 files changed, 6270 insertions, 2171 deletions
diff --git a/include/common.h b/include/common.h index 893af5cc1..00e266ed6 100644 --- a/include/common.h +++ b/include/common.h @@ -180,11 +180,13 @@ typedef void (interrupt_handler_t)(void *); * General Purpose Utilities */ #define min(X, Y) \ - ({ typeof (X) __x = (X), __y = (Y); \ + ({ typeof (X) __x = (X); \ + typeof (Y) __y = (Y); \ (__x < __y) ? __x : __y; }) #define max(X, Y) \ - ({ typeof (X) __x = (X), __y = (Y); \ + ({ typeof (X) __x = (X); \ + typeof (Y) __y = (Y); \ (__x > __y) ? __x : __y; }) #define MIN(x, y) min(x, y) @@ -270,9 +272,9 @@ int setenv (char *, char *); # include <asm/setup.h> # include <asm/u-boot-arm.h> /* ARM version to be fixed! */ #endif /* CONFIG_ARM */ -#ifdef CONFIG_I386 /* x86 version to be fixed! */ -# include <asm/u-boot-i386.h> -#endif /* CONFIG_I386 */ +#ifdef CONFIG_X86 /* x86 version to be fixed! */ +# include <asm/u-boot-x86.h> +#endif /* CONFIG_X86 */ #ifdef CONFIG_AUTO_COMPLETE int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); @@ -447,6 +449,11 @@ void out16(unsigned int, unsigned short value); #if defined (CONFIG_MPC83xx) void ppcDWload(unsigned int *addr, unsigned int *ret); void ppcDWstore(unsigned int *addr, unsigned int *value); +void disable_addr_trans(void); +void enable_addr_trans(void); +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +void ddr_enable_ecc(unsigned int dram_size); +#endif #endif /* $(CPU)/cpu.c */ @@ -538,6 +545,10 @@ ulong get_ddr_freq (ulong); #if defined(CONFIG_MPC86xx) typedef MPC86xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); +static inline ulong get_ddr_freq(ulong dummy) +{ + return get_bus_freq(dummy); +} #endif #if defined(CONFIG_4xx) || defined(CONFIG_IOP480) diff --git a/include/config_cmd_defaults.h b/include/config_cmd_defaults.h index 9283daa3d..a55b268b9 100644 --- a/include/config_cmd_defaults.h +++ b/include/config_cmd_defaults.h @@ -1,7 +1,7 @@ /* * config_cmd_defaults.h - sane defaults for everyone * - * Copyright (c) 2010 Analog Devices Inc. + * Copyright (c) 2010-2011 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -10,5 +10,9 @@ #define _CONFIG_CMD_DEFAULTS_H_ #define CONFIG_CMD_BOOTM 1 +#define CONFIG_CMD_CRC32 1 +#define CONFIG_CMD_EXPORTENV 1 +#define CONFIG_CMD_GO 1 +#define CONFIG_CMD_IMPORTENV 1 #endif diff --git a/include/config_defaults.h b/include/config_defaults.h index abdf3beb0..0337163c2 100644 --- a/include/config_defaults.h +++ b/include/config_defaults.h @@ -12,7 +12,6 @@ /* Support bootm-ing different OSes */ #define CONFIG_BOOTM_LINUX 1 #define CONFIG_BOOTM_NETBSD 1 -#define CONFIG_BOOTM_OSE 1 #define CONFIG_BOOTM_RTEMS 1 #define CONFIG_GZIP 1 diff --git a/include/config_phylib_all_drivers.h b/include/config_phylib_all_drivers.h new file mode 100644 index 000000000..903c7a775 --- /dev/null +++ b/include/config_phylib_all_drivers.h @@ -0,0 +1,32 @@ +/* + * Enable all PHYs + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2011 Freescale Semiconductor, Inc. + * author Andy Fleming + * + */ +#ifndef _CONFIG_PHYLIB_ALL_H +#define _CONFIG_PHYLIB_ALL_H + +#ifdef CONFIG_PHYLIB + +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_MARVELL +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_BROADCOM +#define CONFIG_PHY_DAVICOM +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_NATSEMI +#define CONFIG_PHY_LXT + +#ifdef CONFIG_PHYLIB_10G +#define CONFIG_PHY_TERANETICS +#endif /* CONFIG_PHYLIB_10G */ + +#endif /* CONFIG_PHYLIB */ + +#endif /*_CONFIG_PHYLIB_ALL_H */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 1191eea10..e25d5acc1 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -348,7 +348,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 4 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif @@ -360,7 +360,7 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 #endif diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index affa3a9cf..f136a8e16 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -361,7 +361,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 3 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif @@ -373,7 +373,7 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 4 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 #endif diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index a9599405d..49d64a55e 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -402,7 +402,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #endif @@ -414,7 +414,7 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #endif diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index b0cdc02c1..a4f42cf22 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -319,7 +319,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 2 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_RXID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #endif @@ -331,7 +331,7 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 4 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_RXID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #endif diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 13300de3e..7f7ff9f4e 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -40,6 +40,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif @@ -360,13 +361,13 @@ #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM \ +#define CONFIG_SYS_NAND_BR_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | OR_FCM_PGS /* Large Page*/ \ | OR_FCM_CSCT \ | OR_FCM_CST \ @@ -376,15 +377,15 @@ | OR_FCM_EHTR) #ifdef CONFIG_RAMBOOT_NAND -#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #else #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #endif #define CONFIG_SYS_BR4_PRELIM \ @@ -393,14 +394,14 @@ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR5_PRELIM \ (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR6_PRELIM \ (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \ @@ -408,7 +409,7 @@ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -720,11 +721,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 8b3aff8e0..e1d933ec4 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -420,11 +420,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 7101230e5..5918e644d 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -432,11 +432,11 @@ extern unsigned long get_clock_freq(void); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 62bac6d64..b25fb55a4 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -452,11 +452,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 43e2c2eb1..0c0ae0289 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -491,11 +491,11 @@ extern unsigned long get_clock_freq(void); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 106034db4..4c580a37e 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -430,11 +430,11 @@ extern unsigned long get_clock_freq(void); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 15ebb6f16..f55ef9d79 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -461,11 +461,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 3674e495c..f7df7f038 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -334,7 +334,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 7 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #endif @@ -346,7 +346,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #endif #endif /* CONFIG_QE */ @@ -451,11 +451,11 @@ extern unsigned long get_clock_freq(void); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 9e24e1290..fa626bb97 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -72,6 +72,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif #endif @@ -138,8 +139,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) /* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ -#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ @@ -240,12 +240,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -254,15 +254,15 @@ extern unsigned long get_clock_freq(void); | OR_FCM_EHTR) #ifdef CONFIG_RAMBOOT_NAND -#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */ #define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #else #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #endif #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ @@ -385,13 +385,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 7 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH1 */ @@ -406,13 +406,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH2 */ @@ -427,13 +427,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC3_PHY_ADDR 2 -#define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ -#define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH3 */ @@ -448,13 +448,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC4_PHY_ADDR 3 -#define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ -#define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH4 */ @@ -468,7 +468,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC6_PHY_ADDR 4 -#define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII +#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 #endif /* CONFIG_UEC_ETH6 */ @@ -481,7 +481,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC8_PHY_ADDR 6 -#define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII +#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 #endif /* CONFIG_UEC_ETH8 */ @@ -590,11 +590,11 @@ extern unsigned long get_clock_freq(void); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index bf2fdd668..bb8fb669c 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -40,6 +40,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif @@ -361,12 +362,12 @@ /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | OR_FCM_PGS /* Large Page*/ \ | OR_FCM_CSCT \ | OR_FCM_CST \ @@ -376,35 +377,35 @@ | OR_FCM_EHTR) #ifdef CONFIG_RAMBOOT_NAND -#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #else #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #endif #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ /* Serial Port - controlled on board with jumper J8 @@ -671,6 +672,20 @@ #define CONFIG_CMD_EXT2 #endif +/* + * USB + */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI_PCI +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_STORAGE +#define CONFIG_PCI_EHCI_DEVICE 0 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 +#endif + #undef CONFIG_WATCHDOG /* watchdog disabled */ /* @@ -693,11 +708,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ @@ -740,7 +755,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "memctl_intlv_ctl=2\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 03ee394b3..31dbc3b7d 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -21,14 +21,16 @@ #define CONFIG_SYS_TEXT_BASE 0xfff00000 -#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ /* video */ -#undef CONFIG_VIDEO +#define CONFIG_FSL_DIU_FB -#ifdef CONFIG_VIDEO +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) +#define CONFIG_VIDEO #define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO @@ -88,8 +90,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE @@ -108,7 +108,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ @@ -494,9 +494,6 @@ #define CONFIG_WATCHDOG /* watchdog enabled */ #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ -/*DIU Configuration*/ -#define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ - /* * Miscellaneous configurable options */ @@ -630,8 +627,6 @@ "diuregs=md e002c000 1d\0" \ "dium=mw e002c01c\0" \ "diuerr=md e002c014 1\0" \ - "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \ - "monitor=0-DVI\0" \ "pmregs=md e00e1000 2b\0" \ "lawregs=md e0000c08 4b\0" \ "lbcregs=md e0005000 36\0" \ @@ -651,9 +646,7 @@ "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ - "bdev=sda3\0" \ - "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\ - "monitor=0-DVI\0" + "bdev=sda3\0" #endif #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 0cca603ff..0ddb76f86 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -90,8 +90,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 84b7e1d22..a11897552 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -14,6 +14,10 @@ #include "../board/freescale/common/ics307_clk.h" +#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ @@ -39,10 +43,11 @@ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PHYS_64BIT +#ifdef CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif #define CONFIG_FSL_LAW /* Use common FSL init code */ @@ -65,7 +70,11 @@ */ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* DDR Setup */ @@ -87,7 +96,7 @@ /* I2C addresses of SPD EEPROMs */ #define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* * Memory map @@ -111,7 +120,11 @@ * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif #define CONFIG_FLASH_BR_PRELIM \ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) @@ -145,7 +158,11 @@ #define CONFIG_FSL_NGPIXIS #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT #define PIXIS_BASE_PHYS 0xfffdf0000ull +#else +#define PIXIS_BASE_PHYS PIXIS_BASE +#endif #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) @@ -153,6 +170,8 @@ #define PIXIS_LBMAP_SWITCH 7 #define PIXIS_LBMAP_MASK 0xF0 #define PIXIS_LBMAP_ALTBANK 0x20 +#define PIXIS_ELBC_SPI_MASK 0xc0 +#define PIXIS_SPI 0x80 #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ @@ -185,13 +204,14 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* Video */ -#undef CONFIG_FSL_DIU_FB +#define CONFIG_FSL_DIU_FB #ifdef CONFIG_FSL_DIU_FB #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) #define CONFIG_VIDEO #define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO @@ -203,6 +223,22 @@ #undef CONFIG_SYS_FLASH_EMPTY_INFO #endif +#ifndef CONFIG_FSL_DIU_FB +#define CONFIG_ATI +#endif + +#ifdef CONFIG_ATI +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT +#define CONFIG_VIDEO +#define CONFIG_BIOSEMU +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_ATI_RADEON_FB +#define CONFIG_VIDEO_LOGO +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif + /* * Pass open firmware flat tree */ @@ -235,38 +271,78 @@ #define CONFIG_SYS_EEPROM_BUS_NUM 1 /* + * eSPI - Enhanced SPI + */ +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION + +#define CONFIG_HARD_SPI +#define CONFIG_FSL_ESPI + +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, Slot 2, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 3, Base address b000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 +#endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI @@ -401,11 +477,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ @@ -448,8 +524,7 @@ "diuregs=md e002c000 1d\0" \ "dium=mw e002c01c\0" \ "diuerr=md e002c014 1\0" \ - "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \ - "monitor=0-DVI\0" + "hwconfig=esdhc;audclk:12\0" #define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 95b85e3f6..59f975546 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -30,6 +30,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + #ifdef CONFIG_P1011RDB #define CONFIG_P1011 #endif @@ -50,20 +54,21 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif #ifndef CONFIG_SYS_TEXT_BASE @@ -122,6 +127,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS 1 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x1fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ @@ -143,7 +153,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * actual resources get mapped (not physical addresses) */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif /* CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ /* CONFIG_SYS_IMMR */ @@ -196,13 +210,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull +#else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xff000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -226,10 +244,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R #define CONFIG_HWCONFIG #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ @@ -241,10 +272,20 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else -#define CONFIG_SYS_NAND_BASE 0xfff00000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull +#else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#endif + #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 @@ -263,13 +304,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -278,22 +319,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); | OR_FCM_EHTR) #ifdef CONFIG_RAMBOOT_NAND -#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #else #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #endif #define CONFIG_SYS_VSC7385_BASE 0xffb00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull +#else #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE +#endif -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V) +#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \ + | BR_PS_8 | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ OR_GPCM_EHTR | OR_GPCM_EAD) @@ -360,9 +406,20 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_BUS_NUM 1 +#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 + #define CONFIG_RTC_DS1337 #define CONFIG_SYS_RTC_DS1337_NOOSC #define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* eSPI - Enhanced SPI */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. @@ -372,23 +429,41 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -456,9 +531,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#elif defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_RAMBOOT_SPIFLASH) + #define CONFIG_ENV_IS_IN_SPI_FLASH + #define CONFIG_ENV_SPI_BUS 0 + #define CONFIG_ENV_SPI_CS 0 + #define CONFIG_ENV_SPI_MAX_HZ 10000000 + #define CONFIG_ENV_SPI_MODE 0 + #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ + #define CONFIG_ENV_SECT_SIZE 0x10000 #define CONFIG_ENV_SIZE 0x2000 #endif #else @@ -546,11 +630,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index b32a9976f..b5db0b3c2 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -33,6 +33,20 @@ #define CONFIG_PHYS_64BIT #endif +#ifdef CONFIG_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -78,6 +92,8 @@ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + #define CONFIG_ENABLE_36BIT_PHYS 1 #ifdef CONFIG_PHYS_64BIT @@ -91,6 +107,18 @@ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* + * Config the L2 Cache + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ @@ -128,7 +156,7 @@ /* I2C addresses of SPD EEPROMs */ #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ @@ -305,12 +333,12 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | OR_FCM_PGS /* Large Page*/ \ | OR_FCM_CSCT \ | OR_FCM_CST \ @@ -321,28 +349,28 @@ #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -397,6 +425,18 @@ #define CONFIG_SYS_EEPROM_BUS_NUM 0 /* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION + +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ @@ -569,6 +609,20 @@ /* * Environment */ +#if defined(CONFIG_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else #define CONFIG_ENV_IS_IN_FLASH 1 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 #define CONFIG_ENV_ADDR 0xfff80000 @@ -577,6 +631,7 @@ #endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -605,15 +660,36 @@ /* * USB */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif #undef CONFIG_WATCHDOG /* watchdog disabled */ /* + * SDHC/MMC + */ +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -633,11 +709,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ @@ -651,13 +727,8 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) #define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:E0:0C:02:00:FD #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD #define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD #endif #define CONFIG_IPADDR 192.168.1.254 @@ -680,8 +751,8 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "perf_mode=stable\0" \ - "memctl_intlv_ctl=2\0" \ + "perf_mode=performance\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ @@ -690,18 +761,25 @@ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ + "satabootcmd=setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p2020ds/ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ + "othbootargs=cache-sram-size=0x10000\0" \ "fdtfile=p2020ds/p2020ds.dtb\0" \ - "bdev=sda3\0" + "bdev=sda3\0" \ + "partition=scsi 0:0\0" #define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ + "ext2load $partition $loadaddr $bootfile;" \ + "ext2load $partition $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h new file mode 100644 index 000000000..46f91ccfc --- /dev/null +++ b/include/configs/P3041DS.h @@ -0,0 +1,37 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P3041 DS board configuration file + * + */ +#define CONFIG_P3041DS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P3041 + +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE4 + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#include "corenet_ds.h" + diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h new file mode 100644 index 000000000..6d279b393 --- /dev/null +++ b/include/configs/P5020DS.h @@ -0,0 +1,37 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P5020 DS board configuration file + * + */ +#define CONFIG_P5020DS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P5020 + +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE4 + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#include "corenet_ds.h" + diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h index 27f137f06..05278220f 100644 --- a/include/configs/a320evb.h +++ b/include/configs/a320evb.h @@ -32,6 +32,11 @@ #undef CONFIG_SKIP_LOWLEVEL_INIT /*----------------------------------------------------------------------- + * Power Management Unit + */ +#define CONFIG_FTPMU010_POWER + +/*----------------------------------------------------------------------- * Timer */ #define CONFIG_SYS_HZ 1000 /* timer ticks per second */ @@ -158,7 +163,8 @@ * Static memory controller configuration */ -#include <asm/arch/ftsmc020.h> +#define CONFIG_FTSMC020 +#include <faraday/ftsmc020.h> #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h new file mode 100644 index 000000000..09cb9510f --- /dev/null +++ b/include/configs/am3517_crane.h @@ -0,0 +1,332 @@ +/* + * am3517_crane.h - Default configuration for AM3517 CraneBoard. + * + * Author: Srinath.R <srinath@mistralsolutions.com> + * + * Based on include/configs/am3517evm.h + * + * Copyright (C) 2011 Mistral Solutions pvt Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ + +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) + /* initial data */ +/* + * DDR related + */ +#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* + * USB configuration + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDC for Device functionalities. + */ +#define CONFIG_USB_AM35X 1 +#define CONFIG_MUSB_HCD 1 + +#ifdef CONFIG_USB_AM35X + +#ifdef CONFIG_MUSB_HCD +#define CONFIG_CMD_USB + +#define CONFIG_USB_STORAGE +#define CONGIG_CMD_STORAGE +#define CONFIG_CMD_FAT + +#ifdef CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_PREBOOT "usb start" +#endif /* CONFIG_USB_KEYBOARD */ + +#endif /* CONFIG_MUSB_HCD */ + +#ifdef CONFIG_MUSB_UDC +/* USB device configuration */ +#define CONFIG_USB_DEVICE 1 +#define CONFIG_USB_TTY 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +/* Change these to suit your needs */ +#define CONFIG_USBD_VENDORID 0x0451 +#define CONFIG_USBD_PRODUCTID 0x5678 +#define CONFIG_USBD_MANUFACTURER "Texas Instruments" +#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" +#endif /* CONFIG_MUSB_UDC */ + +#endif /* CONFIG_USB_AM35X */ + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTFILE uImage + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS2,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "AM3517_CRANE # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ + /* on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_ENV_IS_IN_NAND 1 +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#endif /* __CONFIG_H */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 70e8f07ba..f5d582157 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -294,7 +294,9 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE boot_flash_base +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE @@ -304,9 +306,9 @@ #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off -#define CONFIG_ENV_ADDR boot_flash_env_addr +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET /*----------------------------------------------------------------------- * CFI FLASH driver setup @@ -323,14 +325,6 @@ #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS #define CONFIG_SYS_JFFS2_NUM_BANKS 1 -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif - #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h index fd35f3e11..1619db5b2 100644 --- a/include/configs/aspenite.h +++ b/include/configs/aspenite.h @@ -52,6 +52,7 @@ */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include <config_cmd_default.h> +#define CONFIG_CMD_I2C #define CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h index fa72c7f10..a55e1786d 100644 --- a/include/configs/bct-brettl2.h +++ b/include/configs/bct-brettl2.h @@ -11,7 +11,8 @@ /* * Processor Settings */ -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS +#define CONFIG_BFIN_CPU bf536-0.3 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS /* diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h new file mode 100644 index 000000000..77b6735a7 --- /dev/null +++ b/include/configs/bf506f-ezkit.h @@ -0,0 +1,105 @@ +/* + * U-boot - Configuration file for BF506F EZ-Kit board + */ + +#ifndef __CONFIG_BF506F_EZKIT_H__ +#define __CONFIG_BF506F_EZKIT_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf506-0.0 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 16 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_SIZE 0 + +#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 +#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2 + +#define CONFIG_SYS_MONITOR_BASE (L1_DATA_A_SRAM_END) +#define CONFIG_SYS_MONITOR_LEN (4 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024) + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 71 +#define CONFIG_CMD_FLASH +#define CONFIG_MONITOR_IS_IN_RAM + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x400 +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV + + +/* + * Misc Settings + */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ICACHE_OFF +#define CONFIG_DCACHE_OFF +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_CMD_MEMORY +#undef CONFIG_GZIP +#undef CONFIG_ZLIB +#undef CONFIG_CMD_BOOTM +#undef CONFIG_BOOTM_RTEMS +#undef CONFIG_BOOTM_LINUX + +#endif diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index 64ca9ed43..6eec1c91a 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf518-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h new file mode 100644 index 000000000..1f65130f6 --- /dev/null +++ b/include/configs/bf525-ucr2.h @@ -0,0 +1,102 @@ +/* + * U-boot - Configuration file for bf525-ucr2 board + * The board includes ADSP-BF525 rev. 0.2, + * 32-bit SDRAM (SAMSUNG K4S561632H-UC75), + * USB 2.0 High Speed OTG USB WIFI, + * SPI flash (cFeon EN25Q128 16 MB), + * Support PPI and ITU-R656, + * See http://www.ucrobotics.com/?q=cn/ucr2 + */ + +#ifndef __CONFIG_BF525_UCR2_H__ +#define __CONFIG_BF525_UCR2_H__ + +#include <asm/config-pre.h> + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf525-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 24000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 20 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +/* + * SDRAM reference page + * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram + */ +#define CONFIG_EBIU_SDRRC_VAL 0x3f8 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (320 * 1024) +#define CONFIG_SYS_MALLOC_LEN (320 * 1024) + +/* We don't have a parallel flash chip */ +#define CONFIG_SYS_NO_FLASH + +/* support for serial flash */ +#define CONFIG_BFIN_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SPI_FLASH_EON + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Misc Settings + */ +#define CONFIG_UART_CONSOLE 0 + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" +#define CONFIG_BOOTCOMMAND "run sfboot" +#define CONFIG_BOOTDELAY 5 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "sfboot=sf probe 1;" \ + "sf read 0x1000000 0x20000 0x300000;" \ + "bootm 0x1000000\0" + +/* this sets up the default list of enabled commands */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_IMLS + +#endif diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index 4c30c2539..c28f86712 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf526-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h index 14ade1b1e..9c35f2d0b 100644 --- a/include/configs/bf527-ad7160-eval.h +++ b/include/configs/bf527-ad7160-eval.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf527-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER @@ -127,9 +128,8 @@ * SPI_MMC Settings */ #define CONFIG_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_SPI_MMC -#define CONFIG_SPI_MMC_DEFAULT_CS (MAX_CTRL_CS + GPIO_PH3) +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SPI /* diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index fa9053b61..22a5639e5 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf527-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h index 358284619..c0e8b5adc 100644 --- a/include/configs/bf527-sdp.h +++ b/include/configs/bf527-sdp.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf527-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index e1bb59443..95d3afa85 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf533-0.3 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index bf0f063dc..cb37ee797 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf533-0.3 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index 0ba29bc0c..11929c77b 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -24,6 +24,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER @@ -155,6 +156,7 @@ # define CONFIG_CMD_PING #else # undef CONFIG_CMD_NET +# undef CONFIG_CMD_NFS #endif #define CONFIG_CMD_BOOTLDR diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index da4f2f2f5..0913ce4e6 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index 559428f48..e8024d7a2 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -24,6 +24,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER @@ -155,6 +156,7 @@ # define CONFIG_CMD_PING #else # undef CONFIG_CMD_NET +# undef CONFIG_CMD_NFS #endif #define CONFIG_CMD_BOOTLDR diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 2d1930c36..c31e914f8 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS @@ -136,7 +137,8 @@ * SPI_MMC Settings */ #define CONFIG_MMC -#define CONFIG_SPI_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SPI /* diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index 2469c6a0f..717a35a81 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf538-0.4 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index 1c035cfca..4d7d87705 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf548-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA @@ -109,7 +110,7 @@ #define CONFIG_ENV_IS_EMBEDDED_IN_LDR #elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_ENV_SIZE 0x20000 #else #define CONFIG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h index 2b12c3fbe..1490b2f98 100644 --- a/include/configs/bf561-acvilon.h +++ b/include/configs/bf561-acvilon.h @@ -12,7 +12,8 @@ /* * Processor Settings */ -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS +#define CONFIG_BFIN_CPU bf561-0.5 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS /* diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 7b020e67f..33c7e1874 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf561-0.3 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS @@ -79,8 +80,8 @@ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* The BF561-EZKIT uses a top boot flash */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x20004000 -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x10000 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 03c64339d..3312681e8 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -34,10 +34,14 @@ # define CONFIG_DOS_PARTITION # endif # ifdef CONFIG_MMC +# define CONFIG_CMD_EXT2 # define CONFIG_CMD_FAT # define CONFIG_CMD_MMC # define CONFIG_DOS_PARTITION # endif +# ifdef CONFIG_MMC_SPI +# define CONFIG_CMD_MMC_SPI +# endif # ifdef CONFIG_USB # define CONFIG_CMD_EXT2 # define CONFIG_CMD_FAT @@ -85,9 +89,9 @@ # define CONFIG_CMD_CACHE # define CONFIG_CMD_CPLBINFO # define CONFIG_CMD_ELF -# define CONFIG_ELF_SIMPLE_LOAD # define CONFIG_CMD_GPIO # define CONFIG_CMD_KGDB +# define CONFIG_CMD_LDRINFO # define CONFIG_CMD_REGINFO # define CONFIG_CMD_STRINGS # if defined(__ADSPBF51x__) || defined(__ADSPBF52x__) || defined(__ADSPBF54x__) @@ -273,6 +277,7 @@ */ #ifdef CONFIG_SPI_FLASH_ALL # define CONFIG_SPI_FLASH_ATMEL +# define CONFIG_SPI_FLASH_EON # define CONFIG_SPI_FLASH_MACRONIX # define CONFIG_SPI_FLASH_SPANSION # define CONFIG_SPI_FLASH_SST @@ -300,5 +305,6 @@ #endif #define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */ #define CONFIG_LZMA +#define CONFIG_MONITOR_IS_IN_RAM #endif diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h index 3f5c95917..85f08ea88 100644 --- a/include/configs/blackstamp.h +++ b/include/configs/blackstamp.h @@ -24,6 +24,7 @@ /* CPU Options * Be sure to set the Silicon Revision Correctly */ +#define CONFIG_BFIN_CPU bf532-0.5 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER /* diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h index e4688a27b..9950e44f5 100644 --- a/include/configs/blackvme.h +++ b/include/configs/blackvme.h @@ -23,7 +23,8 @@ #define CONFIG_PANIC_HANG 0 /* CPU Options */ -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER +#define CONFIG_BFIN_CPU bf561-0.5 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER /* * CLOCK SETTINGS CAVEAT diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h index 63f003db2..7f8324915 100644 --- a/include/configs/ca9x4_ct_vxp.h +++ b/include/configs/ca9x4_ct_vxp.h @@ -30,6 +30,7 @@ /* Board info register */ #define SYS_ID 0x10000000 #define CONFIG_REVISION_TAG 1 +#define CONFIG_SYS_TEXT_BASE 0x60800000 /* High Level Configuration Options */ #define CONFIG_ARMV7 1 @@ -43,6 +44,8 @@ #define CONFIG_L2_OFF 1 #define CONFIG_INITRD_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) @@ -86,6 +89,10 @@ #define CONFIG_MMC 1 #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC +#define CONFIG_ARM_PL180_MMCI +#define CONFIG_ARM_PL180_MMCI_BASE 0x10005000 +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 +#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 /* BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index 84c93099c..e0c6d53b2 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf527-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h index dbc4a5b10..75152964b 100644 --- a/include/configs/cm-bf533.h +++ b/include/configs/cm-bf533.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf533-0.3 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index c3de96a38..934b74b57 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index e60ebf20f..c274c20ff 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index 27b1cc519..fa62a8e9c 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf548-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h index 8c350bc26..c60401c8f 100644 --- a/include/configs/cm-bf561.h +++ b/include/configs/cm-bf561.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf561-0.3 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 510c6d47f..e07e8b329 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -1,7 +1,8 @@ /* - * (C) Copyright 2010 + * (C) Copyright 2011 * CompuLab, Ltd. * Mike Rapoport <mike@compulab.co.il> + * Igor Grinberg <grinberg@compulab.co.il> * * Based on omap3_beagle.h * (C) Copyright 2006-2008 @@ -9,7 +10,7 @@ * Richard Woodruff <r-woodruff2@ti.com> * Syed Mohammed Khasim <x0khasim@ti.com> * - * Configuration settings for the CompuLab CM-T35 board + * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards * * See file CREDITS for list of people who contributed to this * project. @@ -26,8 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc. */ #ifndef __CONFIG_H @@ -40,7 +40,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ -#define CONFIG_CM_T35 1 /* working with CM-T35 */ +#define CONFIG_CM_T3X 1 /* working with CM-T35 and CM-T3730 */ #define CONFIG_SYS_TEXT_BASE 0x80008000 @@ -110,9 +110,8 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} -#define CONFIG_GENERIC_MMC 1 #define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 +#define CONFIG_OMAP3_MMC 1 #define CONFIG_DOS_PARTITION 1 /* DDR - I use Micron DDR */ @@ -244,14 +243,17 @@ "fi; " \ "else run nandboot; fi" -#define CONFIG_AUTO_COMPLETE 1 /* * Miscellaneous configurable options */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_TIMESTAMP +#define CONFIG_SYS_AUTOLOAD "no" #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT "CM-T35 # " +#define CONFIG_SYS_PROMPT "CM-T3x # " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ @@ -310,7 +312,9 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE boot_flash_base +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE @@ -320,25 +324,17 @@ #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif - #if defined(CONFIG_CMD_NET) #define CONFIG_NET_MULTI #define CONFIG_SMC911X #define CONFIG_SMC911X_32_BIT -#define CM_T35_SMC911X_BASE 0x2C000000 -#define SB_T35_SMC911X_BASE (CM_T35_SMC911X_BASE + (16 << 20)) -#define CONFIG_SMC911X_BASE CM_T35_SMC911X_BASE +#define CM_T3X_SMC911X_BASE 0x2C000000 +#define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) +#define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE #endif /* (CONFIG_CMD_NET) */ /* additions for new relocation code, must be added to all boards */ @@ -349,4 +345,19 @@ extern unsigned int boot_flash_type; CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) +/* Status LED */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 +#define STATUS_LED_GREEN 0 +#define STATUS_LED_BIT STATUS_LED_GREEN +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BOOT STATUS_LED_BIT +#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ + +/* GPIO banks */ +#ifdef CONFIG_STATUS_LED +#define CONFIG_OMAP3_GPIO_6 1 /* GPIO186 is in GPIO bank 6 */ +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index bff212e40..d1cda151d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -28,6 +28,11 @@ #include "../board/freescale/common/ics307_clk.h" +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -63,12 +68,17 @@ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_RAMBOOT_PBL) + #define CONFIG_SYS_NO_FLASH /* Store ENV in memory only */ +#endif + #ifdef CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_NOWHERE #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ @@ -100,6 +110,18 @@ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ @@ -140,6 +162,7 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* @@ -192,6 +215,47 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Nand Flash */ +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) +#define CONFIG_NAND_FSL_ELBC +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ + | OR_FCM_PGS /* Large Page*/ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) + +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#endif /* CONFIG_NAND_FSL_ELBC */ +#endif + #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} @@ -330,7 +394,7 @@ #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull @@ -357,6 +421,7 @@ #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT @@ -389,33 +454,10 @@ #endif #ifdef CONFIG_PCI - -/*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT - -/* video */ -#define CONFIG_VIDEO - -#ifdef CONFIG_VIDEO -#define CONFIG_BIOSEMU -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_ATI_RADEON_FB -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET -#endif - #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_E1000 -#ifndef CONFIG_PCI_PNP -#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS -#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS -#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ -#endif - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION #endif /* CONFIG_PCI */ @@ -461,7 +503,6 @@ /* * Environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ @@ -473,14 +514,15 @@ */ #include <config_cmd_default.h> +#define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_DHCP #ifdef CONFIG_PCI #define CONFIG_CMD_PCI @@ -530,11 +572,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h index d2394235f..a8ada2d41 100644 --- a/include/configs/cpu9260.h +++ b/include/configs/cpu9260.h @@ -31,35 +31,39 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY - -#define CONFIG_DISPLAY_CPUINFO 1 +/* to be removed once maemory-map.h is fixed */ +#define AT91_BASE_SYS 0xffffe800 +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_HZ 1000 -#define CONFIG_ARM926EJS 1 - -#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9260) -#define CONFIG_CPU9260 1 -#elif defined(CONFIG_CPU9G20_128M) || defined(CONFIG_CPU9G20) -#define CONFIG_CPU9G20 1 -#endif +#define CONFIG_ARM926EJS #if defined(CONFIG_CPU9G20) -#define CONFIG_AT91SAM9G20 1 +#define CONFIG_AT91SAM9G20 #elif defined(CONFIG_CPU9260) -#define CONFIG_AT91SAM9260 1 +#define CONFIG_AT91SAM9260 #else #error "Unknown board" #endif +#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#if defined(CONFIG_NANDBOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_TEXT_BASE 0x23f00000 +#else +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#endif /* clocks */ #if defined(CONFIG_CPU9G20) @@ -113,8 +117,8 @@ /* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ #define CONFIG_SYS_MATRIX_EBICSA_VAL \ - (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\ - AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL) + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \ + AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V) /* SDRAM */ /* SDRAMC_MR Mode register */ @@ -199,67 +203,68 @@ /* setup SMC0, CS0 (NOR Flash) - 16-bit */ #if defined(CONFIG_CPU9G20) #define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \ - AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)) + (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \ + AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0)) #define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) | \ - AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14)) + (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \ + AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14)) #define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14)) + (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14)) #define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(3)) + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | \ + AT91_SMC_MODE_TDF_CYCLE(3)) #elif defined(CONFIG_CPU9260) #define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \ - AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)) + (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \ + AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0)) #define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) | \ - AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10)) + (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \ + AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10)) #define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10)) + (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10)) #define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(2)) + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | \ + AT91_SMC_MODE_TDF_CYCLE(2)) #endif /* user reset enable */ #define CONFIG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) + AT91_RSTC_CR_PROCRST | \ + AT91_RSTC_MR_ERSTL(1) | \ + AT91_RSTC_MR_ERSTL(2)) /* Disable Watchdog */ #define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xfff) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xfff)) /* * Hardware drivers */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 +#define CONFIG_AT91SAM9_WATCHDOG +#define CONFIG_AT91_GPIO +#define CONFIG_ATMEL_USART #undef CONFIG_USART0 #undef CONFIG_USART1 #undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_USART3 #define CONFIG_BOOTDELAY 3 /* * BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. @@ -271,37 +276,41 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 -#define CONFIG_CMD_FAT 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MII /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 #if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M) -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) #define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB #else -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) #define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB #endif /* NAND flash */ -#define CONFIG_NAND_ATMEL 1 +#define CONFIG_NAND_ATMEL #define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 13 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* NOR flash */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 +#if defined(CONFIG_NANDBOOT) +#define CONFIG_SYS_NO_FLASH +#else +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER #define PHYS_FLASH_1 0x10000000 #define PHYS_FLASH_2 0x12000000 #define CONFIG_SYS_FLASH_BANKS_LIST \ @@ -310,23 +319,23 @@ #define CONFIG_SYS_MAX_FLASH_SECT (255+4) #define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 +#endif /* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_RESET_PHY_R 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY 1 +#define CONFIG_MACB_SEARCH_PHY /* LEDS */ /* Status LED */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED 1 +#define CONFIG_STATUS_LED +#define CONFIG_BOARD_SPECIFIC_LED #define STATUS_LED_RED 0 #define STATUS_LED_GREEN 1 #define STATUS_LED_YELLOW 2 @@ -350,39 +359,56 @@ /* Optional value */ #define STATUS_LED_BOOT STATUS_LED_BIT -#define CONFIG_RED_LED AT91_PIN_PC11 -#define CONFIG_GREEN_LED AT91_PIN_PC12 -#define CONFIG_YELLOW_LED AT91_PIN_PC7 -#define CONFIG_BLUE_LED AT91_PIN_PC9 +#define CONFIG_RED_LED AT91_PIO_PORTC, 11 +#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12 +#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7 +#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9 /* USB */ -#define CONFIG_USB_ATMEL 1 -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20" +#elif defined(CONFIG_CPU9260) #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" +#endif #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 +#define CONFIG_USB_STORAGE #define CONFIG_SYS_LOAD_ADDR 0x21000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x21e00000 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END \ + (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024) +#if defined(CONFIG_NANDBOOT) +#define CONFIG_SYS_USE_NANDFLASH +#undef CONFIG_SYS_USE_FLASH +#else +#define CONFIG_SYS_USE_FLASH #undef CONFIG_SYS_USE_NANDFLASH -#define CONFIG_SYS_USE_FLASH 1 +#endif + +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_BASEDIR "cpu9G20" +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_BASEDIR "cpu9260" +#endif #if defined(CONFIG_SYS_USE_FLASH) -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_OFFSET 0x40000 #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_OVERWRITE #define CONFIG_BOOTCOMMAND "run flashboot" -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand" +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand" #define MTDPARTS_DEFAULT \ "mtdparts=physmap-flash.0:" \ "256k(u-boot)ro," \ @@ -393,18 +419,12 @@ #define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 " -#if defined(CONFIG_CPU9G20) -#define CONFIG_SYS_BASEDIR "cpu9G20" -#elif defined(CONFIG_CPU9260) -#define CONFIG_SYS_BASEDIR "cpu9260" -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "partition=nand0,0\0" \ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "ramboot=tftpboot 0x22000000 cpu9260/uImage;" \ + "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \ "run ramargs;bootm 22000000\0" \ "flashboot=run ramargs;bootm 0x10060000\0" \ "basedir=" CONFIG_SYS_BASEDIR "\0" \ @@ -421,6 +441,52 @@ "0x10220000 0x13ffffff;cp.b 0x24000000 " \ "0x10220000 $(filesize)\0" \ "" +#elif defined(CONFIG_NANDBOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BOOTCOMMAND "run flashboot" + +#define MTDIDS_DEFAULT "nand0=atmel_nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=atmel_nand:" \ + "128k(bootstrap)ro," \ + "256k(u-boot)ro," \ + "128k(u-boot-env)ro," \ + "128k(u-boot-env2)ro," \ + "2M(kernel)," \ + "-(rootfs)" + +#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \ + "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "partition=nand0,5\0" \ + "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ + "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \ + "run ramargs;bootm 22000000\0" \ + "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \ + "0x200000; bootm 0x22000000\0" \ + "basedir=" CONFIG_SYS_BASEDIR "\0" \ + "u-boot=u-boot-eukrea-cpu9260.bin\0" \ + "kernel=uImage-eukrea-cpu9260.bin\0" \ + "rootfs=image-eukrea-cpu9260.ubi\0" \ + "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \ + "nand erase 20000 40000; " \ + "nand write ${loadaddr} 20000 40000\0" \ + "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \ + "nand erase a0000 200000; " \ + "nand write ${loadaddr} a0000 200000\0" \ + "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \ + "nand erase 2a0000 fd60000; " \ + "nand write ${loadaddr} 2a0000 ${filesize}\0" #endif #define CONFIG_BAUDRATE 115200 @@ -435,10 +501,10 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_SILENT_CONSOLE 1 -#define CONFIG_NETCONSOLE 1 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SILENT_CONSOLE +#define CONFIG_NETCONSOLE /* * Size of malloc() pool @@ -446,6 +512,9 @@ #define CONFIG_SYS_MALLOC_LEN \ ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \ + GENERATED_GBL_DATA_SIZE) + #define CONFIG_STACKSIZE (32 * 1024) #if defined(CONFIG_USE_IRQ) diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index f31081dbf..cfaef15cb 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -26,30 +26,36 @@ #ifndef _CONFIG_CPUAT91_H #define _CONFIG_CPUAT91_H -#ifdef CONFIG_CPUAT91_RAM -#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#include <asm/sizes.h> + +#ifdef CONFIG_RAMBOOT +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_TEXT_BASE 0x21F00000 #else #define CONFIG_BOOTDELAY 1 +#define CONFIG_SYS_TEXT_BASE 0 #endif -#define AT91C_MAIN_CLOCK 179712000 -#define AT91C_MASTER_CLOCK 59904000 - -#define AT91_SLOW_CLOCK 32768 +#define AT91C_XTAL_CLOCK 18432000 +#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) +#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) +#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) +#define CONFIG_SYS_HZ 1000 -#define CONFIG_ARM920T 1 -#define CONFIG_AT91RM9200 1 -#define CONFIG_CPUAT91 1 +#define CONFIG_ARM920T +#define CONFIG_AT91RM9200 +#define CONFIG_CPUAT91 +#define CONFIG_AT91FAMILY #undef CONFIG_USE_IRQ -#define USE_920T_MMU 1 +#define USE_920T_MMU -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 +#define CONFIG_SYS_USE_MAIN_OSCILLATOR /* flash */ #define CONFIG_SYS_MC_PUIA_VAL 0x00000000 #define CONFIG_SYS_MC_PUP_VAL 0x00000000 @@ -81,17 +87,15 @@ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ /* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_AT91RM9200_USART 1 -#define CONFIG_DBGU 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 +#define CONFIG_AT91RM9200_USART +#define CONFIG_DBGU #undef CONFIG_HARD_I2C -#define CONFIG_SOFT_I2C 1 +#undef CONFIG_SOFT_I2C #define AT91_PIN_SDA (1<<25) #define AT91_PIN_SCL (1<<26) -#define CONFIG_SYS_I2C_INIT_BOARD 1 +#define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_SYS_I2C_SPEED 50000 #define CONFIG_SYS_I2C_SLAVE 0 @@ -117,70 +121,77 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME #include <config_cmd_default.h> -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_MII 1 -#define CONFIG_CMD_CACHE 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_CMD_CACHE #undef CONFIG_CMD_USB #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_IMI #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_NFS +#undef CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM 1 -#define CONFIG_CMD_I2C 1 +#ifdef CONFIG_SOFT_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#endif #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x02000000 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024) + (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024) -#define CONFIG_NET_MULTI 1 -#define CONFIG_DRIVER_AT91EMAC 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#define CONFIG_RMII 1 -#define CONFIG_MII 1 +#define CONFIG_NET_MULTI +#define CONFIG_DRIVER_AT91EMAC +#define CONFIG_SYS_RX_ETH_BUFFER 16 +#define CONFIG_RMII +#define CONFIG_MII #define CONFIG_DRIVER_AT91EMAC_PHYADDR 1 #define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_KS8721_PHY 1 +#define CONFIG_KS8721_PHY -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_PROTECTION #define PHYS_FLASH_1 0x10000000 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MAX_FLASH_SECT 128 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 +#define PHYS_FLASH_SIZE (16 * 1024 * 1024) +#define CONFIG_SYS_FLASH_BANKS_LIST \ + { PHYS_FLASH_1 } #if defined(CONFIG_CMD_USB) -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_AT91C_PQFP_UHPBU 1 +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_AT91C_PQFP_UHPBU #undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 #endif -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 128 * 1024) +#define CONFIG_ENV_SIZE (128 * 1024) +#define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_SYS_LOAD_ADDR 0x21000000 @@ -192,29 +203,33 @@ #define CONFIG_SYS_MAXARGS 32 #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024) + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \ + GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) #define CONFIG_STACKSIZE (32 * 1024) +#define CONFIG_STACKSIZE_IRQ (4 * 1024) +#define CONFIG_STACKSIZE_FIQ (4 * 1024) + #if defined(CONFIG_USE_IRQ) #error CONFIG_USE_IRQ not supported #endif -#define CONFIG_DEVICE_NULLDEV 1 -#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_DEVICE_NULLDEV +#define CONFIG_SILENT_CONSOLE -#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_PROMPT \ "Press SPACE to abort autoboot\n" #define CONFIG_AUTOBOOT_STOP_STR " " #define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_VERSION_VARIABLE 1 +#define CONFIG_VERSION_VARIABLE #define MTDIDS_DEFAULT "nor0=physmap-flash.0" #define MTDPARTS_DEFAULT \ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index d898b777a..e02793dd5 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -61,6 +61,8 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* Size of malloc() pool */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ @@ -297,15 +299,7 @@ #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_ENV_OFFSET boot_flash_off - -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 diff --git a/include/configs/dig297.h b/include/configs/dig297.h new file mode 100644 index 000000000..7aeb24e74 --- /dev/null +++ b/include/configs/dig297.h @@ -0,0 +1,311 @@ +/* + * (C) Copyright 2011 Comelit Group SpA + * Luca Ceresoli <luca.ceresoli@comelit.it> + * + * Based on omap3_beagle.h: + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * + * Configuration settings for the Comelit DIG297 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3430 /* which is in a 3430 */ + +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +#define CONFIG_SDRC /* The chip has SDRC controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* UBI needs >= 512 kB */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration: UART3 (ttyO2) + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC +#define CONFIG_OMAP3_MMC +#define CONFIG_DOS_PARTITION + +/* DDR - I use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR + +/* library portions to compile in */ +#define CONFIG_RBTREE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_LZO + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_UBI /* UBI Support */ +#define CONFIG_CMD_UBIFS /* UBIFS Support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:896k(uboot),"\ + "128k(uboot-env),3m(kernel),252m(ubi)" + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER +#define CONFIG_TWL4030_LED + +/* + * Board NAND Info. + */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + +#if defined(CONFIG_CMD_NET) +/* + * SMSC9220 Ethernet + */ + +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 + +#endif /* (CONFIG_CMD_NET) */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "partition=nand0,3\0"\ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=ubi0:rootfs ro\0" \ + "nandrootfstype=ubifs\0" \ + "nfspath=/srv/nfs\0" \ + "tftpfilename=uImage\0" \ + "gatewayip=0.0.0.0\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${mtdparts} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}::off\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${mtdparts} " \ + "ubi.mtd=3 " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}::off\0" \ + "netargs=setenv bootargs console=${console} " \ + "${mtdparts} " \ + "root=/dev/nfs rw " \ + "nfsroot=${serverip}:${nfspath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}::off\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 100000 300000; " \ + "bootm ${loadaddr}\0" \ + "netboot=echo Booting from network ...; " \ + "run netargs; " \ + "tftp ${loadaddr} ${serverip}:${tftpfilename}; " \ + "bootm ${loadaddr}\0" \ + "resetenv=nand erase e0000 20000\0"\ + +#define CONFIG_BOOTCOMMAND \ + "run nandboot" + +#define CONFIG_AUTO_COMPLETE +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "DIG297# " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ + /* works on */ +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ + /* load address */ + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x0E0000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#endif /* __CONFIG_H */ diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index e7fd0f7f9..c738b3ab4 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -252,6 +252,8 @@ #if defined(CONFIG_DIGSY_REV5) #define CONFIG_SYS_I2C_RTC_ADDR 0x56 #define CONFIG_RTC_RV3029 +/* Enable 5k Ohm trickle charge resistor */ +#define CONFIG_SYS_RV3029_TCR 0x20 #else #define CONFIG_RTC_DS1337 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 @@ -343,7 +345,11 @@ */ #define CONFIG_MPC5xxx_FEC 1 #define CONFIG_MPC5xxx_FEC_MII100 +#if defined(CONFIG_DIGSY_REV5) +#define CONFIG_PHY_ADDR 0x01 +#else #define CONFIG_PHY_ADDR 0x00 +#endif #define CONFIG_PHY_RESET_DELAY 1000 #define CONFIG_NETCONSOLE /* include NetConsole support */ diff --git a/include/configs/dkb.h b/include/configs/dkb.h index 638af5e33..b400d0acf 100644 --- a/include/configs/dkb.h +++ b/include/configs/dkb.h @@ -47,6 +47,7 @@ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include <config_cmd_default.h> #define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_I2C #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS /* @@ -56,6 +57,7 @@ #include "mv-common.h" #undef CONFIG_ARCH_MISC_INIT + /* * Environment variables configurations */ diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index f7609d71a..4fc5262bc 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -42,6 +42,10 @@ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ +#define CONFIG_AUTOBOOT_STOP_STR " " + /* * Configure PLL */ @@ -111,9 +115,10 @@ /* Temp sensor/hwmon/dtt */ #define CONFIG_DTT_LM63 1 /* National LM63 */ -#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ +#define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */ #define CONFIG_DTT_PWM_LOOKUPTABLE \ - { { 40, 10 }, { 50, 20 }, { 60, 40 } } + { { 40, 10 }, { 43, 13 }, { 46, 16 }, \ + { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } } #define CONFIG_DTT_TACH_LIMIT 0xa10 /* EBC peripherals */ @@ -136,6 +141,8 @@ #define CONFIG_SYS_LATCH1_RESET 0xffcf #define CONFIG_SYS_LATCH1_BOOT 0xffff +#define CONFIG_SYS_FPGA_NO_RFL_HI + /* * FLASH organization */ @@ -310,6 +317,7 @@ * OSD Setup */ #define CONFIG_SYS_ICS8N3QV01 +#define CONFIG_SYS_MPC92469AC #define CONFIG_SYS_SIL1178 #define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h new file mode 100644 index 000000000..6b328a547 --- /dev/null +++ b/include/configs/dnp5370.h @@ -0,0 +1,128 @@ +/* + * U-boot - Configuration file for SSV DNP5370 board + */ + +#ifndef __CONFIG_DNP5370_H__ +#define __CONFIG_DNP5370_H__ + +/* this must come first */ +#include <asm/config-pre.h> + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.3 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +#define CONFIG_CLKIN_HZ 25000000 +#define CONFIG_CLKIN_HALF 0 +#define CONFIG_PLL_BYPASS 0 +#define CONFIG_VCO_MULT 24 +#define CONFIG_CCLK_DIV 1 +#define CONFIG_SCLK_DIV 5 + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x03a0 +#define CONFIG_EBIU_SDBCTL_VAL 0x0013 +#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d + +#define CONFIG_EBIU_AMGCTL_VAL 0xF7 +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define CONFIG_ROOTPATH /romfs + +#define CONFIG_NET_MULTI 1 +#define CONFIG_BFIN_MAC 1 +#define CONFIG_PHY_ADDR 0 +#define CONFIG_RMII 1 + +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#endif + +/* + * Flash Settings + * + * Only 3 MB of the 4 MB NOR flash are addressable. + * But limiting the flash size does not seem to work. + * It seems the CFI detection has precedence. + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 71 /* (M29W320EB) */ + +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15 + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x20004000 +#define CONFIG_ENV_SIZE 0x00002000 +#define CONFIG_ENV_SECT_SIZE 0x00002000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_OFFSET 0x00004000 /* (CONFIG_ENV_ADDR - CONFIG_FLASH_BASE) */ + +#define ENV_IS_EMBEDDED +#define LDS_BOARD_TEXT \ + arch/blackfin/lib/libblackfin.o (.text*); \ + arch/blackfin/cpu/libblackfin.o (.text*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text*); + +/* + * Misc Settings + */ +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_STRINGS +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_SYS_LONGHELP + +/* This disables the hardware watchdog (not inside the bfin) */ +#define CONFIG_DNP5370_EXT_WD_DISABLE 1 + +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTCOMMAND "bootm 0x20030000" +#define CONFIG_BOOTARGS "console=ttyBF0,115200 root=/dev/mtdblock3 rootfstype=ext2" + +/* Convenience commands to update Linux in NOR flash */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fetchme=tftpboot 0x01000000 uImage;" \ + "iminfo\0" \ + "flashme=protect off 0x20030000 0x2003ffff;" \ + "erase 0x20030000 0x202effff;" \ + "cp.b 0x01000000 0x20030000 0x2c0000\0" \ + "runme=bootm 0x01000000\0" + +/* this sets up the default list of enabled commands */ +#include <config_cmd_default.h> + +#ifndef CONFIG_BFIN_MAC +# undef CONFIG_CMD_NET +# undef CONFIG_CMD_NFS +#endif + +#endif diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 34a9d6866..548d52c6a 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -33,7 +33,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_X86 #define CONFIG_SYS_SC520 #define CONFIG_SYS_SC520_SSI #define CONFIG_SHOW_BOOT_PROGRESS @@ -158,16 +157,19 @@ /*----------------------------------------------------------------------- * Memory organization: * 32kB Stack + * 16kB Cache-As-RAM @ 0x19200000 * 256kB Monitor + * (128kB + Environment Sector Size) malloc pool */ -#define CONFIG_SYS_STACK_SIZE 0x8000 +#define CONFIG_SYS_STACK_SIZE (32 * 1024) #define CONFIG_SYS_CAR_ADDR 0x19200000 -#define CONFIG_SYS_CAR_SIZE 0x00004000 +#define CONFIG_SYS_CAR_SIZE (16 * 1024) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_CAR_ADDR + \ CONFIG_SYS_CAR_SIZE) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + \ + 128*1024) /* Address of temporary Global Data */ #define CONFIG_SYS_INIT_GD_ADDR CONFIG_SYS_CAR_ADDR @@ -198,17 +200,25 @@ #define CONFIG_SYS_FLASH_LEGACY_512Kx8 #define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */ #define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */ + /*----------------------------------------------------------------------- * Environment configuration + * - Boot flash is 512kB with 64kB sectors + * - StrataFlash is 32MB with 128kB sectors + * - Redundant embedded environment is 25% of the Boot flash + * - Redundant StrataFlash environment is <1% of the StrataFlash + * - Environment is therefore located in StrataFlash + * - Primary copy is located in first sector of first flash + * - Redundant copy is located in second sector of first flash + * - Stack is only 32kB, so environment size is limited to 4kB */ #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SIZE 0x01000 #define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1 -/* Redundant Copy */ #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \ CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /*----------------------------------------------------------------------- * PCI configuration diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index a75f06aa5..19b654444 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> + * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> * * Based on original Kirkwood support which is * (C) Copyright 2009 diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h index 1424347aa..571c3cb72 100644 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@ -66,6 +66,8 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +#define CONFIG_OF_LIBFDT 1 + /* * Size of malloc() pool */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index d004f319d..34bd89917 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -46,4 +46,5 @@ #define CONFIG_MACH_TYPE MACH_TYPE_HARMONY #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ +#define CONFIG_BOARD_EARLY_INIT_F #endif /* __CONFIG_H */ diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index e2dbbb151..055f8a0f4 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf561-0.5 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS @@ -79,8 +80,8 @@ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ /* The BF561-EZKIT uses a top boot flash */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x20004000 -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h index c19ecc0e4..5af9bec8f 100644 --- a/include/configs/igep0020.h +++ b/include/configs/igep0020.h @@ -53,6 +53,8 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* * NS16550 Configuration */ @@ -129,14 +131,61 @@ */ #define CONFIG_TWL4030_POWER 1 -/* Environment information */ -#define CONFIG_BOOTCOMMAND \ - "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0" - #define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS \ - "usbtty=cdc_acm\0" + "usbtty=cdc_acm\0" \ + "loadaddr=0x82000000\0" \ + "usbtty=cdc_acm\0" \ + "console=ttyS2,115200n8\0" \ + "mpurate=500\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=jffs2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from onenand ...; " \ + "run nandargs; " \ + "onenand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" #define CONFIG_AUTO_COMPLETE 1 diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h index 1325bfa01..92144af93 100644 --- a/include/configs/igep0030.h +++ b/include/configs/igep0030.h @@ -53,6 +53,8 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* * NS16550 Configuration */ @@ -127,14 +129,61 @@ */ #define CONFIG_TWL4030_POWER 1 -/* Environment information */ -#define CONFIG_BOOTCOMMAND \ - "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0" - #define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS \ - "usbtty=cdc_acm\0" + "usbtty=cdc_acm\0" \ + "loadaddr=0x82000000\0" \ + "usbtty=cdc_acm\0" \ + "console=ttyS2,115200n8\0" \ + "mpurate=500\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=jffs2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from onenand ...; " \ + "run nandargs; " \ + "onenand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" #define CONFIG_AUTO_COMPLETE 1 diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 502363807..9405f562c 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -28,7 +28,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/mx31-regs.h> +#include <asm/arch/imx-regs.h> /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ diff --git a/include/configs/innokom.h b/include/configs/innokom.h index d8fcbdb42..744d65c6e 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -140,6 +140,8 @@ /* * I2C bus */ +#define CONFIG_I2C_MV 1 +#define CONFIG_MV_I2C_REG 0x40301680 #define CONFIG_HARD_I2C 1 #define CONFIG_SYS_I2C_SPEED 50000 #define CONFIG_SYS_I2C_SLAVE 0xfe diff --git a/include/configs/ip04.h b/include/configs/ip04.h index 528363c6b..c024d78c1 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -20,6 +20,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf532-0.5 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index e3bd264a8..cb6d0fb6c 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008 + * (C) Copyright 2008-2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * See file CREDITS for list of people who contributed to this @@ -25,7 +25,8 @@ #define __CONFIG_KEYMILE_H /* Do boardspecific init for all boards */ -#define CONFIG_BOARD_EARLY_INIT_R 1 +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_LAST_STAGE_INIT #define CONFIG_BOOTCOUNT_LIMIT @@ -39,13 +40,6 @@ #endif /* CONFIG_SYS_KWD_CONFIG */ /* - * CONFIG_SYS_TEXT_BASE can be defined in board specific header file, if needed - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x00400000 -#endif /* CONFIG_SYS_TEXT_BASE */ - -/* * Command line configuration. */ #include <config_cmd_default.h> @@ -56,51 +50,46 @@ #define CONFIG_CMD_IMMAP #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#define CONFIG_CMD_DTT #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C #define CONFIG_CMD_JFFS2 -#define CONFIG_JFFS2_CMDLINE #define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_SETEXPR -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ /* * Miscellaneous configurable options */ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE -#define CONFIG_HUSH_INIT_VAR 1 +#define CONFIG_HUSH_INIT_VAR #define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decr. freq: 1 ms ticks */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_LOADS_ECHO +#define CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */ /* @@ -108,28 +97,28 @@ * to modify in a centralized location. This is used in the HDLC * driver to set the MAC. */ -#define CONFIG_CHECK_ETHERNET_PRESENT 1 -#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE +#define CONFIG_CHECK_ETHERNET_PRESENT +#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_KMBEC_FPGA_BASE #define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ #define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ -#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_MAX_I2C_BUS 1 -#define CONFIG_SYS_I2C_INIT_BOARD 1 -#define CONFIG_I2C_MUX 1 +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MUX /* EEprom support */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 +#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* Support the IVM EEprom */ #define CONFIG_SYS_IVM_EEPROM_ADR 0x50 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100 -#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_PROTECTION /* * BOOTP options @@ -139,139 +128,325 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME -#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */ - -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* UBI Support for all Keymile boards */ #define CONFIG_CMD_UBI #define CONFIG_RBTREE #define CONFIG_MTD_PARTITIONS -#define CONFIG_FLASH_CFI_MTD #define CONFIG_MTD_DEVICE #define CONFIG_MTD_CONCAT -/* define this to use the keymile's io muxing feature */ -/*#define CONFIG_IO_MUXING */ +/* common powerpc specific env settings */ +#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS +#define CONFIG_KM_DEF_ENV_BOOTPARAMS \ + "bootparams=empty\0" \ + "initial_boot_bank=0\0" +#endif -#ifdef CONFIG_IO_MUXING -#define CONFIG_KM_DEF_ENV_IOMUX \ - "nc=setenv ethact HDLC \0" \ - "nce=setenv ethact SCC \0" \ - "stderr=serial,nc \0" \ - "stdin=serial,nc \0" \ - "stdout=serial,nc \0" \ - "tftpsrcp=69 \0" \ - "tftpdstp=69 \0" -#else -#define CONFIG_KM_DEF_ENV_IOMUX \ - "stderr=serial \0" \ - "stdin=serial \0" \ - "stdout=serial \0" +#ifndef CONFIG_KM_DEF_NETDEV +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" #endif -#ifndef CONFIG_KM_DEF_ENV_PRIVATE -#define CONFIG_KM_DEF_ENV_PRIVATE \ - "kmprivate=empty\0" +#ifndef CONFIG_KM_UBI_PARTITION_NAME +#define CONFIG_KM_UBI_PARTITION_NAME "ubi0" +#endif +#ifndef CONFIG_KM_UBI_LINUX_MTD_NAME +#define CONFIG_KM_UBI_LINUX_MTD_NAME "ubi0" #endif #define xstr(s) str(s) #define str(s) #s +/* + * bootrunner + * - run all commands in 'subbootcmds' + * - on error, stop running the remaing commands + */ +#define CONFIG_KM_DEF_ENV_BOOTRUNNER \ + "bootrunner=" \ + "break=0; " \ + "for subbootcmd in ${subbootcmds}; do " \ + "if test ${break} -eq 0; then; " \ + "echo \"[INFO] running \\c\"; " \ + "print ${subbootcmd}; " \ + "run ${subbootcmd} || break=1; " \ + "if test ${break} -eq 1; then; " \ + "echo \"[ERR] failed \\c\"; " \ + "print ${subbootcmd}; " \ + "fi; " \ + "fi; " \ + "done\0" \ + "" + +/* + * boottargets + * - set 'subbootcmds' for the bootrunner + * - set 'bootcmd' and 'altbootcmd' + * available targets: + * - 'release': for a standalone system kernel/rootfs from flash + * - 'develop': for development kernel(tftp)/rootfs(NFS) + * - 'ramfs': rootfilesystem in RAM kernel(tftp)/rootfs(RAM) + * + * - 'commonargs': bootargs common to all targets + */ +#define CONFIG_KM_DEF_ENV_BOOTTARGETS \ + "commonargs=" \ + "addip " \ + "addtty " \ + "addmem " \ + "addinit " \ + "addvar " \ + "addmtdparts " \ + "addbootcount " \ + "\0" \ + "develop=" \ + "setenv subbootcmds \"" \ + "tftpfdt tftpkernel " \ + "nfsargs ${commonargs} " \ + "printbootargs boot " \ + "\" && " \ + "setenv bootcmd \'" \ + "run bootrunner" \ + "\' && " \ + "setenv altbootcmd \'" \ + "run bootcmd" \ + "\' && " \ + "run setboardid && " \ + "saveenv && " \ + "reset\0" \ + "ramfs=" \ + "setenv actual_bank -1 && " \ + "setenv subbootcmds \"" \ + "tftpfdt tftpkernel " \ + "setrootfsaddr tftpramfs " \ + "flashargs ${commonargs} " \ + "addpanic addramfs " \ + "printbootargs boot " \ + "\" && " \ + "setenv bootcmd \'" \ + "run bootrunner" \ + "\' && " \ + "setenv altbootcmd \'" \ + "run bootcmd" \ + "\' && " \ + "run setboardid && " \ + "run setramfspram && " \ + "saveenv && " \ + "reset\0" \ + "release=" \ + "setenv actual_bank ${initial_boot_bank} && " \ + "setenv subbootcmds \"" \ + "checkboardidlist " \ + "checkboardid " \ + "ubiattach ubicopy " \ + "cramfsloadfdt cramfsloadkernel " \ + "flashargs ${commonargs} " \ + "addpanic " \ + "printbootargs boot " \ + "\" && " \ + "setenv bootcmd \'" \ + "run bootrunner; reset" \ + "\' && " \ + "setenv altbootcmd \'" \ + "run actual0 bootcmd; reset" \ + "\' && " \ + "saveenv && " \ + "reset\0" \ + "" + +/* + * bootargs + * - modify 'bootargs' + * + * - 'addip': add ip configuration + * - 'addmem': limit kernel memory mem= + * - 'addpanic': add kernel panic options + * - 'addramfs': add phram device for the rootfilesysten in ram + * - 'addtty': add console=... + * - 'addvar': add phram device for /var + * - 'nfsargs': default arguments for nfs boot + * - 'flashargs': defaults arguments for flash base boot + * + * processor specific settings + * - 'addbootcount': add boot counter + * - 'addmtdparts': add mtd partition information + */ +#define CONFIG_KM_DEF_ENV_BOOTARGS \ + "addinit=" \ + "setenv bootargs ${bootargs} init=${init}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off\0" \ + "addmem=" \ + "setenv bootargs ${bootargs} mem=0x${pnvramaddr}\0" \ + "addpanic=" \ + "setenv bootargs ${bootargs} " \ + "panic=1 panic_on_oops=1\0" \ + "addramfs=" \ + "setenv bootargs \"" \ + "${bootargs} phram.phram=" \ + "rootfs${actual_bank},${rootfsaddr},${rootfssize}\"\0" \ + "addtty=" \ + "setenv bootargs ${bootargs}" \ + " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}\0" \ + "addvar=" \ + "setenv bootargs ${bootargs} phram.phram=phvar," \ + "${varaddr},0x" xstr(CONFIG_KM_PHRAM) "\0" \ + "nfsargs=" \ + "setenv bootargs " \ + "ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \ + "root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "flashargs=" \ + "setenv bootargs " \ + "ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \ + "root=mtdblock:rootfs${actual_bank} " \ + "rootfstype=squashfs ro\0" \ + "" + +/* + * compute_addr + * - compute addresses and sizes + * - addresses are calculated form the end of memory 'memsize' + * + * - 'setramfspram': compute PRAM size for ramfs target + * - 'setrootfsaddr': compute rootfilesystem address for phram + */ +#define CONFIG_KM_DEF_ENV_COMPUTE_ADDR \ + "setboardid=" \ + "if test \"x${boardId}\" = \"x\"; then; " \ + "setenv boardId ${IVM_BoardId} && " \ + "setenv hwKey ${IVM_HWKey}; " \ + "else; " \ + "echo \\\\c; " \ + "fi\0" \ + "setramfspram=" \ + "setexpr value ${rootfssize} / 0x400 && " \ + "setexpr value 0x${value} + ${pram} && " \ + "setenv pram 0x${value}\0" \ + "setrootfsaddr=" \ + "setexpr value ${pnvramaddr} - ${rootfssize} && " \ + "setenv rootfsaddr 0x${value}\0" \ + "" + +/* + * flash_boot + * - commands for booting from flash + * + * - 'cramfsaddr': address to the cramfs (in ram) + * - 'cramfsloadkernel': copy kernel from a cramfs to ram + * - 'ubiattach': attach ubi partition + * - 'ubicopy': copy ubi volume to ram + * - volume names: bootfs0, bootfs1, bootfs2, ... + * - 'ubiparition': mtd parition name for ubi + * + * processor specific settings + * - 'cramfsloadfdt': copy fdt from a cramfs to ram + */ +#define CONFIG_KM_DEF_ENV_FLASH_BOOT \ + "cramfsaddr="xstr(CONFIG_KM_CRAMFS_ADDR) "\0" \ + "cramfsloadkernel=" \ + "cramfsload ${kernel_addr_r} uImage && " \ + "setenv actual_kernel_addr ${kernel_addr_r}\0" \ + "ubiattach=ubi part ${ubipartition}\0" \ + "ubicopy=ubi read ${cramfsaddr} bootfs${actual_bank}\0" \ + "ubipartition=" CONFIG_KM_UBI_PARTITION_NAME "\0" \ + "" + +/* + * net_boot + * - commands for booting over the network + * + * - 'tftpkernel': load a kernel with tftp into ram + * - 'tftpramfs': load rootfs with tftp into ram + * + * processor specific settings + * - 'tftpfdt': load fdt with tftp into ram + */ +#define CONFIG_KM_DEF_ENV_NET_BOOT \ + "tftpkernel=" \ + "tftpboot ${kernel_addr_r} ${kernel_file} && " \ + "setenv actual_kernel_addr ${kernel_addr_r}\0" \ + "tftpramfs=" \ + "tftpboot ${rootfsaddr} \"\\\"${rootfsfile}\\\"\" && " \ + "setenv loadaddr\0" \ + "" + +/* + * constants + * - KM specific constants and commands + * + * - 'default': setup default environment + */ +#define CONFIG_KM_DEF_ENV_CONSTANTS \ + "actual=setenv actual_bank ${initial_boot_bank}\0" \ + "actual0=setenv actual_bank 0\0" \ + "actual_bank=${initial_boot_bank}\0" \ + "default=" \ + "setenv default 'run newenv; reset' && " \ + "run release && saveenv; reset\0" \ + "checkboardidlist=" \ + "if test \"x${boardIdListHex}\" != \"x\"; then " \ + "IVMbidhwk=${IVM_BoardId}_${IVM_HWKey}; " \ + "found=0; " \ + "for bidhwk in \"${boardIdListHex}\"; do " \ + "echo trying $bidhwk ...; " \ + "if test \"x$bidhwk\" = \"x$IVMbidhwk\"; then " \ + "found=1; " \ + "echo match found for $bidhwk; " \ + "if test \"x$bidhwk\" != \"x${boardId}_${hwKey}\";then "\ + "setenv boardid ${IVM_BoardId}; " \ + "setenv boardId ${IVM_BoardId}; " \ + "setenv hwkey ${IVM_HWKey}; " \ + "setenv hwKey ${IVM_HWKey}; " \ + "echo \"boardId set to ${boardId}\"; " \ + "echo \"hwKey set to ${hwKey}\"; " \ + "saveenv; " \ + "fi; " \ + "fi; " \ + "done; " \ + "else " \ + "echo \"boardIdListHex not set, not checked\"; "\ + "found=1; " \ + "fi; " \ + "test \"$found\" = 1 \0" \ + "checkboardid=" \ + "test \"x${boardId}\" = \"x${IVM_BoardId}\" && " \ + "test \"x${hwKey}\" = \"x${IVM_HWKey}\"\0" \ + "printbootargs=print bootargs\0" \ + "rootfsfile="xstr(CONFIG_HOSTNAME) "/rootfsImage\0" \ + "" + #ifndef CONFIG_KM_DEF_ENV #define CONFIG_KM_DEF_ENV \ - "netdev=eth0\0" \ - "u-boot_addr_r=100000\0" \ - "kernel_addr_r=200000\0" \ - "fdt_addr_r=600000\0" \ - "ram_ws=800000 \0" \ - "script_ws=780000 \0" \ - "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \ - xstr(CONFIG_HOSTNAME) ".dtb\0" \ - "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \ - "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off " xstr(BOOTFLASH_START) " +${filesize};" \ - "erase " xstr(BOOTFLASH_START) " +${filesize};" \ - "cp.b ${u-boot_addr_r} " xstr(BOOTFLASH_START) \ - " ${filesize};" \ - "protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \ - "load_fdt=tftp ${fdt_addr_r} ${fdt_file}; " \ - "setenv actual_fdt_addr ${fdt_addr_r} \0" \ - "load_kernel=tftp ${kernel_addr_r} ${kernel_file}; " \ - "setenv actual_kernel_addr ${kernel_addr_r} \0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "mtdargs=setenv bootargs root=${actual_rootfs} rw " \ - "rootfstype=jffs2 \0" \ - "altmtdargs=setenv bootargs root=${backup_rootfs} rw " \ - "rootfstype=jffs2 \0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addboardid=setenv bootargs ${bootargs} " \ - "hwKey=${IVM_HWKey} boardId=0x${IVM_BoardId} \0" \ - "addpram=setenv bootargs ${bootargs} " \ - "mem=${mem} pram=${pram}\0" \ - "pram=" xstr(CONFIG_PRAM) "k\0" \ - "net_nfs=tftp ${kernel_addr_r} ${kernel_file}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addcon addboardid addpram;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_self=tftp ${kernel_addr_r} ${kernel_file}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "tftp ${ramdisk_addr} ${ramdisk_file}; " \ - "run ramargs addip addboardid addpram; " \ - "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0"\ - "flash_nfs=run nfsargs addip addcon;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addcon addboardid addpram;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "bootcmd=run mtdargs addip addcon addboardid addpram; " \ - "bootm ${actual_kernel_addr} - ${actual_fdt_addr} \0" \ - "altbootcmd=run altmtdargs addip addcon addboardid addpram; " \ - "bootm ${backup_kernel_addr} - ${backup_fdt_addr} \0" \ - "actual0=setenv actual_bank 0; setenv actual_kernel_addr " \ - "${bank0_kernel_addr}; " \ - "setenv actual_fdt_addr ${bank0_fdt_addr}; " \ - "setenv actual_rootfs ${bank0_rootfs} \0" \ - "actual1=setenv actual_bank 1; setenv actual_kernel_addr " \ - "${bank1_kernel_addr}; " \ - "setenv actual_fdt_addr ${bank1_fdt_addr}; " \ - "setenv actual_rootfs ${bank1_rootfs} \0" \ - "backup0=setenv backup_bank 0; setenv backup_kernel_addr " \ - "${bank0_kernel_addr}; " \ - "setenv backup_fdt_addr ${bank0_fdt_addr}; " \ - "setenv backup_rootfs ${bank0_rootfs} \0" \ - "backup1=setenv backup_bank 1; setenv backup_kernel_addr " \ - "${bank1_kernel_addr}; " \ - "setenv backup_fdt_addr ${bank1_fdt_addr}; " \ - "setenv backup_rootfs ${bank1_rootfs} \0" \ - "setbank0=run actual0 backup1 \0" \ - "setbank1=run actual1 backup0 \0" \ - "release=setenv bootcmd " \ - "\'run mtdargs addip addcon addboardid addpram;" \ - "bootm ${actual_kernel_addr} - ${actual_fdt_addr} \'; " \ - "saveenv \0" \ - "develop=setenv bootcmd " \ - "\'run nfsargs addip addcon addboardid addpram;" \ - "bootm ${actual_kernel_addr} - ${actual_fdt_addr} \'; " \ - "saveenv \0" \ - "developall=setenv bootcmd " \ - "\'run load_fdt load_kernel nfsargs " \ - "addip addcon addboardid addpram; " \ - "bootm ${actual_kernel_addr} - ${actual_fdt_addr} \'; " \ - "saveenv \0" \ - "set_new_esw_script=setenv new_esw_script " \ - "new_esw_0x${IVM_BoardId}_0x${IVM_HWKey}.scr \0" \ - "new_esw=run set_new_esw_script; " \ - "tftp ${script_ws} ${new_esw_script}; " \ - "iminfo ${script_ws}; source ${script_ws} \0" \ - "bootlimit=0 \0" \ - CONFIG_KM_DEF_ENV_IOMUX \ - CONFIG_KM_DEF_ENV_PRIVATE \ + CONFIG_KM_DEF_ENV_BOOTPARAMS \ + CONFIG_KM_DEF_NETDEV \ + CONFIG_KM_DEF_ENV_CPU \ + CONFIG_KM_DEF_ENV_BOOTRUNNER \ + CONFIG_KM_DEF_ENV_BOOTTARGETS \ + CONFIG_KM_DEF_ENV_BOOTARGS \ + CONFIG_KM_DEF_ENV_COMPUTE_ADDR \ + CONFIG_KM_DEF_ENV_FLASH_BOOT \ + CONFIG_KM_DEF_ENV_NET_BOOT \ + CONFIG_KM_DEF_ENV_CONSTANTS \ + "altbootcmd=run bootcmd\0" \ + "bootcmd=run default\0" \ + "bootlimit=2\0" \ + "init=/sbin/init-overlay.sh\0" \ + "kernel_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \ + "kernel_file="xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "kernel_name=uImage\0" \ + "load=tftpboot ${u-boot_addr_r} ${u-boot}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "u-boot_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \ "" #endif /* CONFIG_KM_DEF_ENV */ diff --git a/include/configs/km-powerpc.h b/include/configs/km-powerpc.h new file mode 100644 index 000000000..335160998 --- /dev/null +++ b/include/configs/km-powerpc.h @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_KEYMILE_POWERPC_H +#define __CONFIG_KEYMILE_POWERPC_H + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_CMD_DTT +#define CONFIG_JFFS2_CMDLINE + +#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */ +#define CONFIG_FLASH_CFI_MTD + +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ + +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ + +/****************************************************************************** + * (PRAM usage) + * ... ------------------------------------------------------- + * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM + * ... |<------------------- pram -------------------------->| + * ... ------------------------------------------------------- + * @END_OF_RAM: + * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose + * @CONFIG_KM_PHRAM: address for /var + * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) + * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM + */ + +/* size of rootfs in RAM */ +#define CONFIG_KM_ROOTFSSIZE 0x0 +/* pseudo-non volatile RAM [hex] */ +#define CONFIG_KM_PNVRAM 0x80000 +/* physical RAM MTD size [hex] */ +#define CONFIG_KM_PHRAM 0x100000 +/* resereved pram area at the end of memroy [hex] */ +#define CONFIG_KM_RESERVED_PRAM 0x0 +/* enable protected RAM */ +#define CONFIG_PRAM 0 + +#define CONFIG_KM_CRAMFS_ADDR 0x800000 +#define CONFIG_KM_KERNEL_ADDR 0x400000 /* 3968Kbytes */ +#define CONFIG_KM_FDT_ADDR 0x7E0000 /* 128Kbytes */ + +#define CONFIG_KM_DEF_ENV_CPU \ + "addbootcount=echo \\\\c\0" \ + "addmtdparts=echo \\\\c\0" \ + "boot=bootm ${actual_kernel_addr} - ${actual_fdt_addr}\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb && " \ + "setenv actual_fdt_addr ${fdt_addr_r}\0" \ + "fdt_addr_r=" xstr(CONFIG_KM_FDT_ADDR) "\0" \ + "fdt_file=" \ + xstr(CONFIG_HOSTNAME) "/" \ + xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "tftpfdt=" \ + "tftpboot ${fdt_addr_r} ${fdt_file} && " \ + "setenv actual_fdt_addr ${fdt_addr_r} \0" \ + "update=" \ + "protect off " xstr(BOOTFLASH_START) " +${filesize} && "\ + "erase " xstr(BOOTFLASH_START) " +${filesize} && " \ + "cp.b ${u-boot_addr_r} " xstr(BOOTFLASH_START) \ + " ${filesize} && " \ + "protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \ + "" + +#endif /* __CONFIG_KEYMILE_POWERPC_H */ diff --git a/include/configs/km82xx-common.h b/include/configs/km82xx-common.h new file mode 100644 index 000000000..345212ca9 --- /dev/null +++ b/include/configs/km82xx-common.h @@ -0,0 +1,336 @@ +/* + * (C) Copyright 2007-2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __KM82XX_COMMON +#define __KM82XX_COMMON + +/* + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#define CONFIG_CONS_ON_SMC /* Console is on SMC */ +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ +#undef CONFIG_CONS_NONE /* It's not on external UART */ +#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ +#define CONFIG_SYS_SMC_RXBUFLEN 128 +#define CONFIG_SYS_MAXIDLE 10 + +/* + * Select ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for + * SCC, 1-3 for FCC) + * + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines + * must be defined elsewhere (as for the console), or CONFIG_CMD_NET + * must be unset. + */ +#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ +#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ +#undef CONFIG_ETHER_NONE /* No external Ethernet */ +#define CONFIG_NET_MULTI + +#define CONFIG_ETHER_INDEX 4 +#define CONFIG_HAS_ETH0 +#define CONFIG_SYS_SCC_TOUT_LOOP 10000000 + +#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) + +#ifndef CONFIG_8260_CLKIN +#define CONFIG_8260_CLKIN 66000000 /* in Hz */ +#endif + +#define BOOTFLASH_START 0xFE000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyCPM0" + +#define MTDPARTS_DEFAULT "mtdparts=" \ + "app:" \ + "768k(u-boot)," \ + "128k(env)," \ + "128k(envred)," \ + "3072k(free)," \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")" + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + "EEprom_ivm=pca9544a:70:4 \0" \ + "unlock=yes\0" \ + "newenv=" \ + "prot off 0xFE0C0000 +0x40000 && " \ + "era 0xFE0C0000 +0x40000\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "" + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_LEN (768 << 10) + +#define CONFIG_ENV_IS_IN_FLASH + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed */ +#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ + +/* + * Software (bit-bang) I2C driver configuration + */ + +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) do { \ + if (bit) \ + iop->pdat |= 0x00010000; \ + else \ + iop->pdat &= ~0x00010000; \ + } while (0) +#define I2C_SCL(bit) do { \ + if (bit) \ + iop->pdat |= 0x00020000; \ + else \ + iop->pdat &= ~0x00020000; \ + } while (0) +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 +#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +#define CONFIG_SYS_IMMR 0xF0000000 + +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* Hard reset configuration word */ +#define CONFIG_SYS_HRCW_MASTER 0x0604b211 + +/* No slaves */ +#define CONFIG_SYS_HRCW_SLAVE1 0 +#define CONFIG_SYS_HRCW_SLAVE2 0 +#define CONFIG_SYS_HRCW_SLAVE3 0 +#define CONFIG_SYS_HRCW_SLAVE4 0 +#define CONFIG_SYS_HRCW_SLAVE5 0 +#define CONFIG_SYS_HRCW_SLAVE6 0 +#define CONFIG_SYS_HRCW_SLAVE7 0 + +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CONFIG_SYS_HID0_INIT 0 +#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) + +#define CONFIG_SYS_HID2 0 + +#define CONFIG_SYS_SIUMCR 0x4020c200 +#define CONFIG_SYS_SYPCR 0xFFFFFFC3 +#define CONFIG_SYS_BCR 0x10000000 +#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) + +/* + *----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CONFIG_SYS_RMR 0 + +/* + *----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/* + *----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/* + *----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CONFIG_SYS_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 8 bit FLASH + * 1 60x SDRAM 32 bit SDRAM + * 3 60x GPCM 8 bit GPIO/PIGGY + * 5 60x GPCM 16 bit CFG-Flash + * + */ +/* Bank 0 - FLASH + */ +#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV2 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX) + + +/* + * Bank 1 - 60x bus SDRAM + */ +#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ + +#define CONFIG_SYS_MPTPR 0x1800 + +/* + *----------------------------------------------------------------------------- + * Address for Mode Register Set (MRS) command + *----------------------------------------------------------------------------- + */ +#define CONFIG_SYS_MRS_OFFS 0x00000110 +#define CONFIG_SYS_PSRT 0x0e + +#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 + +/* + * SDRAM initialization values + */ + +#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_8 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + +#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_5_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + +/* + * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values + */ +#define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\ + BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\ + ORxG_CSNT | ORxG_ACS_DIV2 |\ + ORxG_SCY_3_CLK | ORxG_TRLX) + +/* + * BFTICU board FPGA on CS4 initialization values + */ +#define CONFIG_SYS_FPGA_BASE 0x40000000 +#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ + +#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\ + BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) + +#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\ + ORxG_CSNT | ORxG_ACS_DIV2 |\ + ORxG_SCY_3_CLK | ORxG_TRLX) + +/* + * CFG-Flash on CS5 initialization values + */ +#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ + BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) + +#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \ + CONFIG_SYS_FLASH_SIZE_2) |\ + ORxG_CSNT | ORxG_ACS_DIV2 |\ + ORxG_SCY_5_CLK | ORxG_TRLX) + +#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ + +/* pass open firmware flat tree */ +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" + +#endif /* __KM82XX_COMMON */ diff --git a/include/configs/km8321-common.h b/include/configs/km8321-common.h new file mode 100644 index 000000000..6fab45eb8 --- /dev/null +++ b/include/configs/km8321-common.h @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada <peterb@logicpd.com> + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov <avorontsov@ru.mvista.com> + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * + * (C) Copyright 2010-2011 + * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_KM8321_COMMON_H +#define __CONFIG_KM8321_COMMON_H + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_MPC832x /* MPC832x CPU specific */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +#define CONFIG_MISC_INIT_R + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860252 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (2 << TIMING_CFG1_WRREC_SHIFT) | \ + (6 << TIMING_CFG1_REFREC_SHIFT) | \ + (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_KM8321_COMMON_H */ diff --git a/include/configs/km83xx-common.h b/include/configs/km83xx-common.h new file mode 100644 index 000000000..85b6ed200 --- /dev/null +++ b/include/configs/km83xx-common.h @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_KM83XX_H +#define __CONFIG_KM83XX_H + +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" +#include "km-powerpc.h" + +#define MTDIDS_DEFAULT "nor0=boot" +#define MTDPARTS_DEFAULT "mtdparts=" \ + "boot:" \ + "768k(u-boot)," \ + "128k(env)," \ + "128k(envred)," \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")" + +#define CONFIG_MISC_INIT_R +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_FSL_I2C +#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 +#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ROOTPATH +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ROOTPATH \ + "dtt_bus=pca9547:70:a\0" \ + "EEprom_ivm=pca9547:70:9\0" \ + "newenv=" \ + "prot off 0xF00C0000 +0x40000 && " \ + "era 0xF00C0000 +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + +#endif /* __CONFIG_KM83XX_H */ diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index bf77cc054..70113d449 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -6,6 +6,9 @@ * (C) Copyright 2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * + * (C) Copyright 2010-2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * * See file CREDITS for list of people who contributed to this * project. * @@ -25,7 +28,10 @@ * MA 02110-1301 USA */ -/* for linking errors see http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ +/* + * for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html + */ #ifndef _CONFIG_KM_ARM_H #define _CONFIG_KM_ARM_H @@ -38,12 +44,34 @@ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KIRKWOOD /* SOC Family Name */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_MACH_SUEN3 /* Machine type */ +#define CONFIG_MACH_KM_KIRKWOOD /* Machine type */ /* include common defines/options for all Keymile boards */ #include "keymile-common.h" -#undef CONFIG_CMD_DTT -#undef CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_SYS_TEXT_BASE 0x04000000 /* code address after reloc */ +#define CONFIG_ENV_SIZE (128 << 10) /* NAND chip block size */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ + +/* pseudo-non volatile RAM [hex] */ +#define CONFIG_KM_PNVRAM 0x80000 +/* physical RAM MTD size [hex] */ +#define CONFIG_KM_PHRAM 0x17F000 + +#define CONFIG_KM_CRAMFS_ADDR 0x2400000 +#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */ + +#define CONFIG_KM_DEF_ENV_CPU \ + "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "boot=bootm ${actual_kernel_addr} - -\0" \ + "cramfsloadfdt=echo \\\\c\0" \ + "tftpfdt=echo \\\\c\0" \ + CONFIG_KM_DEF_ENV_UPDATE \ + "" + + #define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ @@ -152,15 +180,15 @@ void set_sda (int state); void set_scl (int state); int get_sda (void); int get_scl (void); -#define SUEN3_SDA_PIN 8 -#define SUEN3_SCL_PIN 9 -#define SUEN3_ENV_WP 38 +#define KM_KIRKWOOD_SDA_PIN 8 +#define KM_KIRKWOOD_SCL_PIN 9 +#define KM_KIRKWOOD_ENV_WP 38 -#define I2C_ACTIVE __set_direction(SUEN3_SDA_PIN, 0) -#define I2C_TRISTATE __set_direction(SUEN3_SDA_PIN, 1) -#define I2C_READ (kw_gpio_get_value(SUEN3_SDA_PIN) ? 1 : 0) -#define I2C_SDA(bit) kw_gpio_set_value(SUEN3_SDA_PIN, bit); -#define I2C_SCL(bit) kw_gpio_set_value(SUEN3_SCL_PIN, bit); +#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0) +#define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1) +#define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0) +#define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit) +#define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit) #endif #define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ @@ -173,6 +201,47 @@ int get_scl (void); #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ +#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_EEPROM_WREN +#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) +#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0" + +/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#define CONFIG_CMD_SF + +#define CONFIG_SPI_FLASH +#define CONFIG_HARD_SPI +#define CONFIG_KIRKWOOD_SPI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */ + +#define FLASH_GPIO_PIN 0x00010000 + +#define MTDIDS_DEFAULT "nand0=orion_nand" +/* test-only: partitioning needs some tuning, this is just for tests */ +#define MTDPARTS_DEFAULT "mtdparts=" \ + "orion_nand:" \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")" + +#define CONFIG_KM_DEF_ENV_UPDATE \ + "update=" \ + "spi on;sf probe 0;sf erase 0 50000;" \ + "sf write ${u-boot_addr_r} 0 ${filesize};" \ + "spi off\0" + #if defined(CONFIG_SYS_NO_FLASH) #define CONFIG_KM_UBI_PARTITION_NAME "ubi0" #undef CONFIG_FLASH_CFI_MTD @@ -185,4 +254,13 @@ int get_scl (void); #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 /* Do early setups now in board_init_f() */ #define CONFIG_BOARD_EARLY_INIT_F + +/* + * resereved pram area at the end of memroy [hex] + * 8Mbytes for switch + 4Kbytes for bootcount + */ +#define CONFIG_KM_RESERVED_PRAM 0x801000 +/* address for the bootcount (taken from end of RAM) */ +#define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM) + #endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 8fcadfee5..2fcecaf88 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -8,7 +8,7 @@ * Copyright (C) 2007 MontaVista Software, Inc. * Anton Vorontsov <avorontsov@ru.mvista.com> * - * (C) Copyright 2008 + * (C) Copyright 2008-2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * This program is free software; you can redistribute it and/or @@ -23,32 +23,24 @@ /* * High Level Configuration Options */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ -#define CONFIG_KMETER1 1 /* KMETER1 board specific */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_MPC8360 /* MPC8360 CPU specific */ +#define CONFIG_KMETER1 /* KMETER1 board specific */ #define CONFIG_HOSTNAME kmeter1 +#define CONFIG_KM_BOARD_NAME "kmeter1" #define CONFIG_SYS_TEXT_BASE 0xF0000000 +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth2\0" \ -/* include common defines/options for all Keymile boards */ -#include "keymile-common.h" +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" -#define CONFIG_KM_UBI_PARTITION_NAME "ubi0" - -#define MTDIDS_DEFAULT "nor0=boot" -#define MTDPARTS_DEFAULT \ - "mtdparts=boot:768k(u-boot),128k(env),128k(envred)," \ - "-(" CONFIG_KM_UBI_PARTITION_NAME ")" - -#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MISC_INIT_R /* - * System Clock Setup + * System IO Setup */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 +#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) /* * Hardware Reset Configuration Word @@ -69,54 +61,7 @@ HRCWH_LALE_EARLY | \ HRCWH_LDP_CLEAR ) -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000006 -#define CONFIG_SYS_SICRL 0x00000000 - -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -#undef CONFIG_DDR_ECC - -/* - * DDRCDR - DDR Control Driver Register - */ - -#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) - #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_SREN) #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 @@ -124,6 +69,11 @@ #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT)) +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10 | \ + CSCONFIG_ODT_WR_ACS) + #define CONFIG_SYS_DDRCDR 0x40000001 #define CONFIG_SYS_DDR_MODE 0x47860452 #define CONFIG_SYS_DDR_MODE2 0x8080c000 @@ -137,14 +87,14 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_50) | \ - ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \ - ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - ( 3 << TIMING_CFG1_WRREC_SHIFT) | \ - ( 7 << TIMING_CFG1_REFREC_SHIFT) | \ - ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - ( 3 << TIMING_CFG1_PRETOACT_SHIFT)) +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ @@ -156,31 +106,15 @@ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 -#define CONFIG_SYS_PIGGY_BASE 0xE8000000 -#define CONFIG_SYS_PIGGY_SIZE 128 -#define CONFIG_SYS_PAXE_BASE 0xA0000000 +/* PRIO FPGA */ +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 +/* PAXE FPGA */ +#define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 512 -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * Local Bus Configuration & Clock Setup @@ -194,56 +128,14 @@ * * Bank Bus Machine PortSz Size Device * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY * 3 Local GPCM 8 bit 512MB PAXE * */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX | OR_GPCM_EAD) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * PRIO1/PIGGY on the local bus CS1 - */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */ -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ - (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX | OR_GPCM_EAD) /* * PAXE on the local bus CS3 */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \ @@ -255,165 +147,14 @@ OR_GPCM_TRLX | OR_GPCM_EAD) /* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#undef CONFIG_PCI /* No PCI */ - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_RAMBOOT */ -#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ -#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_RAMBOOT */ - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_FSL_I2C -#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_I2C_MUX 1 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 -#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE -#endif - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -#if defined(CFG_RAMBOOT) -#undef CONFIG_CMD_SAVEENV -#undef CONFIG_CMD_LOADS -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* PAXE: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U @@ -441,39 +182,4 @@ #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #endif /* CONFIG_PCI */ -#define BOOTFLASH_START F0000000 - -#define CONFIG_PRAM 512 /* protected RAM [KBytes] */ - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \ - "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \ - "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ - "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0" \ - "unlock=yes\0" \ - "fdt_addr=F0080000\0" \ - "kernel_addr=F00a0000\0" \ - "ramdisk_addr=F03a0000\0" \ - "ramdisk_addr_r=F10000\0" \ - "EEprom_ivm=pca9547:70:9\0" \ - "dtt_bus=pca9547:70:a\0" \ - "mtdids=nor0=app \0" \ - "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h new file mode 100644 index 000000000..55ed3f6a4 --- /dev/null +++ b/include/configs/kmsupx5.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada <peterb@logicpd.com> + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov <avorontsov@ru.mvista.com> + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * + * (C) Copyright 2010-2011 + * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_KMSUPX5 1 /* Keymile PBEC8321 board specific */ +#define CONFIG_HOSTNAME supx5 +#define CONFIG_KM_BOARD_NAME "supx5" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 + +/* include common defines/options for all 8321 Keymile boards */ +#include "km8321-common.h" + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local GPCM 8 bit 256MB LPXF + * 3 Local not used + * + */ + +/* + * LPXF on the local bus CS2 + * Window base at flash base + * Window size: 256 MB + */ + +#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */ +#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */ + +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + (OR_GPCM_TRLX & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_EAD) + +/* LPXF: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +/* Bank 3 not used */ +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#endif /* __CONFIG_H */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 6dec0ee74..dcde76c86 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * See file CREDITS for list of people who contributed to this @@ -29,92 +29,24 @@ * (easy to change) */ -#define CONFIG_MPC8247 1 -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_MGCOGE 1 +#define CONFIG_MPC8247 +#define CONFIG_MGCOGE #define CONFIG_HOSTNAME mgcoge #define CONFIG_SYS_TEXT_BASE 0xFE000000 -#define CONFIG_CPM2 1 /* Has a CPM2 */ - /* include common defines/options for all Keymile boards */ #include "keymile-common.h" - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ -#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ -#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ -#define CONFIG_NET_MULTI 1 - -#define CONFIG_ETHER_INDEX 4 -#define CONFIG_HAS_ETH0 -#define CONFIG_SYS_SCC_TOUT_LOOP 10000000 - -# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif - -#define BOOTFLASH_START FE000000 -#define CONFIG_PRAM 512 /* protected RAM [KBytes] */ - -#define MTDIDS_DEFAULT "nor0=boot,nor1=app" -#define MTDPARTS_DEFAULT \ - "mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \ - "app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)" - -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "addcon=setenv bootargs ${bootargs} " \ - "console=ttyCPM0,${baudrate}\0" \ - "mtdids=nor0=boot,nor1=app \0" \ - "partition=nor1,5 \0" \ - "new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0" \ - "EEprom_ivm=pca9544a:70:4 \0" \ - "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \ - "unlock=yes\0" \ - "" +#include "km-powerpc.h" #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE 0xFE000000 #define CONFIG_SYS_FLASH_SIZE 32 #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 3 +/* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 #define CONFIG_SYS_FLASH_BASE_1 0x50000000 #define CONFIG_SYS_FLASH_SIZE_1 32 @@ -124,228 +56,12 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ CONFIG_SYS_FLASH_BASE_1, \ CONFIG_SYS_FLASH_BASE_2 } +#define MTDIDS_DEFAULT "nor3=app" -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384KB for Monitor */ - -#define CONFIG_ENV_IS_IN_FLASH - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ -#define CONFIG_ENV_BUFFER_PRINT 1 - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 -#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -#define CONFIG_SYS_IMMR 0xF0000000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CONFIG_SYS_HRCW_MASTER 0x0604b211 - -/* No slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SIUMCR 0x4020c200 -#define CONFIG_SYS_SYPCR 0xFFFFFFC3 -#define CONFIG_SYS_BCR 0x10000000 -#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 8 bit FLASH - * 1 60x SDRAM 32 bit SDRAM - * 3 60x GPCM 8 bit GPIO/PIGGY - * 5 60x GPCM 16 bit CFG-Flash - * - */ -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX ) - - -/* Bank 1 - 60x bus SDRAM - */ -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ - -#define CONFIG_SYS_MPTPR 0x1800 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 -#define CONFIG_SYS_PSRT 0x0e - -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 - -/* SDRAM initialization values -*/ - -#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_8 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* GPIO/PIGGY on CS3 initialization values -*/ -#define CONFIG_SYS_PIGGY_BASE 0x30000000 -#define CONFIG_SYS_PIGGY_SIZE 128 - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\ - BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_3_CLK | ORxG_TRLX ) - -/* Board FPGA on CS4 initialization values -*/ -#define CONFIG_SYS_FPGA_BASE 0x40000000 -#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ - -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\ - BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_3_CLK | ORxG_TRLX ) - -/* CFG-Flash on CS5 initialization values -*/ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ - BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \ - CONFIG_SYS_FLASH_SIZE_2) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK | ORxG_TRLX ) - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* pass open firmware flat tree */ -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 +/* include further common stuff for all keymile 82xx boards */ +#include "km82xx-common.h" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" +/* bfticu address */ +#define CONFIG_SYS_BFTICU_BASE 0x40000000 #endif /* __CONFIG_H */ diff --git a/include/configs/mgcoge2ne.h b/include/configs/mgcoge2ne.h new file mode 100644 index 000000000..287b7175c --- /dev/null +++ b/include/configs/mgcoge2ne.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2007-2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MGCOGE2NE +#define __MGCOGE2NE + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC8247 +#define CONFIG_MGCOGE +#define CONFIG_HOSTNAME mgcoge2ne + +#define CONFIG_SYS_TEXT_BASE 0xFE000000 + +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" +#include "km-powerpc.h" + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0xFE000000 +#define CONFIG_SYS_FLASH_SIZE 32 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* + * max num of sects on one + * chip + */ + +#define CONFIG_SYS_FLASH_BASE_1 0x50000000 +#define CONFIG_SYS_FLASH_SIZE_1 64 +#define CONFIG_SYS_FLASH_SIZE_2 0 + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_FLASH_BASE_1 } + +#define MTDIDS_DEFAULT "nor2=app" + +/* include further common stuff for all keymile 82xx boards */ +#include "km82xx-common.h" + +#endif /* __MGCOGE2NE */ diff --git a/include/configs/mgcoge2un.h b/include/configs/mgcoge2un.h new file mode 100644 index 000000000..d3c7bdcdd --- /dev/null +++ b/include/configs/mgcoge2un.h @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla@marvell.com> + * + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2010-2011 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ + +#ifndef _CONFIG_MGCOGE2UN_H +#define _CONFIG_MGCOGE2UN_H + +/* include common defines/options for all arm based Keymile boards */ +#include "km_arm.h" + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nKeymile MGCOGE2UN" + +#define CONFIG_HOSTNAME mgcoge2un + +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + "newenv=setenv addr 0x100000 && " \ + "i2c dev 1; mw.b ${addr} 0 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ + "rootpath=/opt/eldk/arm\0" \ + "EEprom_ivm=" KM_IVM_BUS "\0" \ + "" + +#endif /* _CONFIG_MGCOGE2UN_H */ diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h deleted file mode 100644 index 8e398d720..000000000 --- a/include/configs/mp2usb.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * 2004-2005 Gary Jennejohn <garyj@denx.de> - * - * Modified for the MP2USB by (C) Copyright 2005 Eric Benard - * ebenard@eukrea.com - * - * Configuration settings for the MP2USB board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AT91_LEGACY - -/* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */ -#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ -#define CONFIG_MP2USB 1 /* on an MP2USB Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_SYS_ATMEL_PLL_INIT_BUG 1 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 -/* flash */ -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 -#define CONFIG_SYS_SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ -#define CONFIG_SYS_PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */ -#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */ - -/* sdram */ -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRC_CR_VAL 0x3211295A /* set up the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000020 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */ - -/* - * Hardware drivers - */ - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_AT91RM9200_USART -#define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_AT91C_PQFP_UHPBUG 1 - -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -#undef CONFIG_HARD_I2C - -#ifdef CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 0 /* not used */ -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ -#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW -#endif -/* still about 20 kB free with this defined */ -#define CONFIG_SYS_LONGHELP - -#define CONFIG_BOOTDELAY 3 - -#if !defined(CONFIG_HARD_I2C) -#define CONFIG_TIMESTAMP -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#if defined(CONFIG_HARD_I2C) - - #define CONFIG_CMD_DATE - #define CONFIG_CMD_EEPROM - #define CONFIG_CMD_I2C - #define CONFIG_CMD_MISC - -#else - - #define CONFIG_CMD_CACHE - #define CONFIG_CMD_USB - - #undef CONFIG_CMD_BDI - #undef CONFIG_CMD_FPGA - #undef CONFIG_CMD_IMI - #undef CONFIG_CMD_LOADS - #undef CONFIG_CMD_MISC - #undef CONFIG_CMD_SOURCE - -#endif - - -#define CONFIG_SYS_LONGHELP - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 - -#define CONFIG_NET_MULTI 1 -#ifdef CONFIG_NET_MULTI -#define CONFIG_DRIVER_AT91EMAC 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#else -#define CONFIG_DRIVER_ETHER 1 -#endif -#define CONFIG_NET_RETRY_COUNT 20 -#undef CONFIG_AT91C_USE_RMII - -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x1000000 /* 16 megs main flash */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ -#define CONFIG_SYS_FLASH_LOCK_TOUT (10*CONFIG_SYS_HZ) /* Timeout for Flash Set Lock Bit */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (10*CONFIG_SYS_HZ) /* Timeout for Flash Clear Lock Bits */ -#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x20000 - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } - -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ - -#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */ -#undef CONFIG_SILENT_CONSOLE /* enable silent startup */ - -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR " " -#define CONFIG_AUTOBOOT_DELAY_STR "d" - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index f966325a8..e7ef29809 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -46,16 +46,16 @@ */ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ -#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* video */ -#undef CONFIG_VIDEO - -#ifdef CONFIG_VIDEO +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) +#define CONFIG_VIDEO #define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO @@ -74,7 +74,6 @@ #define CONFIG_MISC_INIT_R #define CONFIG_SYS_IMMR 0x80000000 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index d2798e974..5ea59b4ab 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -22,7 +22,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/mx31-regs.h> +#include <asm/arch/imx-regs.h> /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 86c758f2a..d4c6d1610 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -30,7 +30,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/mx31-regs.h> +#include <asm/arch/imx-regs.h> /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 591d6e1a9..6a785f8b2 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -33,6 +33,8 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_TEXT_BASE 0x97800000 + #define CONFIG_L2_OFF #include <asm/arch/imx-regs.h> @@ -46,6 +48,8 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* * Size of malloc() pool */ @@ -222,4 +226,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_OF_LIBFDT +#define CONFIG_SYS_BOOTMAPSZ 0x800000 + #endif diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index f2a575275..5749a0866 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -38,6 +38,8 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) @@ -190,4 +192,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_OF_LIBFDT +#define CONFIG_SYS_BOOTMAPSZ 0x800000 + #endif /* __CONFIG_H */ diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h index 49a16ab20..758f19dc4 100644 --- a/include/configs/nhk8815.h +++ b/include/configs/nhk8815.h @@ -80,6 +80,11 @@ #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ #define PHYS_SDRAM_2 0x08000000 /* SDR-SDRAM BANK #2*/ #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +/* The IPL loads us at 0, tell so to u-boot. Put stack pointer 1M into RAM */ +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + (1<<20)) #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ #ifdef CONFIG_USE_IRQ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 7161ab18c..2888c7bfb 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -38,6 +38,8 @@ /*#define CONFIG_APTIX 1 #* define if on APTIX test chip */ /*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */ +#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 + /* Clock config to target*/ #define PRCM_CONFIG_II 1 /* #define PRCM_CONFIG_III 1 */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 5cfa4cb69..bc3c45b75 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -56,13 +56,6 @@ #define CONFIG_MISC_INIT_R #define CONFIG_OF_LIBFDT 1 -/* - * The early kernel mapping on ARM currently only maps from the base of DRAM - * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. - * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, - * so that leaves DRAM base to DRAM base + 0x4000 available. - */ -#define CONFIG_SYS_BOOTMAPSZ 0x4000 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 @@ -108,6 +101,18 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 +/* Status LED */ +#define CONFIG_STATUS_LED 1 +#define CONFIG_BOARD_SPECIFIC_LED 1 +#define STATUS_LED_BIT 0x01 +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT1 0x02 +#define STATUS_LED_STATE1 STATUS_LED_ON +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BOOT STATUS_LED_BIT +#define STATUS_LED_GREEN STATUS_LED_BIT1 + /* DDR - I use Micron DDR */ #define CONFIG_OMAP3_MICRON_DDR 1 @@ -121,6 +126,11 @@ #define CONFIG_USB_TTY 1 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +/* USB EHCI */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + /* commands to include */ #include <config_cmd_default.h> @@ -137,7 +147,9 @@ #define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_USB_STORAGE /* USB storage support */ #define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_LED /* LED support */ #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ @@ -190,7 +202,7 @@ "loadaddr=0x82000000\0" \ "usbtty=cdc_acm\0" \ "console=ttyS2,115200n8\0" \ - "mpurate=500\0" \ + "mpurate=auto\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ "defaultdisplay=dvi\0" \ @@ -215,9 +227,9 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ @@ -229,15 +241,19 @@ #define CONFIG_BOOTCOMMAND \ "if mmc rescan ${mmcdev}; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loaduimage; then " \ + "run mmcboot;" \ + "fi;" \ + "fi;" \ + "run nandboot;" \ #define CONFIG_AUTO_COMPLETE 1 /* @@ -306,7 +322,9 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE boot_flash_base +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE @@ -316,18 +334,10 @@ #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif - #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 5bdb3fd9e..5ec079c24 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -298,33 +298,31 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE boot_flash_base +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#elif defined(CONFIG_CMD_ONENAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE +#endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_OMAP_GPMC #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #elif defined(CONFIG_CMD_ONENAND) #define CONFIG_ENV_IS_IN_ONENAND 1 +#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET #endif -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off -#define CONFIG_ENV_ADDR boot_flash_env_addr - -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET /* * Support for relocation diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 1b3d43979..c5e997c87 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -52,6 +52,8 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* * Size of malloc() pool */ @@ -271,7 +273,9 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE boot_flash_base +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE @@ -281,18 +285,10 @@ #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif - #if defined(CONFIG_CMD_NET) /*---------------------------------------------------------------------------- * SMSC9211 Ethernet from SMSC9118 family diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 72b0cc223..39c87a8a1 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -55,6 +55,8 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* * Size of malloc() pool */ @@ -262,7 +264,9 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE boot_flash_base +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE @@ -270,16 +274,8 @@ #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 470898152..1d6ba7f4a 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -71,6 +71,8 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* * Size of malloc() pool * Total Size Environment - 256k @@ -358,14 +360,4 @@ * - rest for filesystem */ -/*--------------------------------------------------------------------------*/ - -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index f7d06521e..5adffb5b4 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -61,6 +61,8 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* * Size of malloc() pool */ @@ -285,7 +287,9 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE boot_flash_base +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE @@ -295,16 +299,8 @@ #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 73779331c..747c69de3 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -62,6 +62,8 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* * Size of malloc() pool */ @@ -254,7 +256,9 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE boot_flash_base +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE @@ -262,16 +266,8 @@ #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 2b03b0f2b..ffcc9aa04 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -60,6 +60,8 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* * Size of malloc() pool * Total Size Environment - 256k diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 9a8bb7334..8d04d0740 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -56,6 +56,8 @@ #undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R +#define CONFIG_OF_LIBFDT 1 + #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h index 37a22a7c4..831af6a7d 100644 --- a/include/configs/pdm360ng.h +++ b/include/configs/pdm360ng.h @@ -64,8 +64,6 @@ #define CONFIG_SPLASH_SCREEN #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_XRES 800 -#define CONFIG_VIDEO_YRES 480 #endif #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ diff --git a/include/configs/purple.h b/include/configs/purple.h deleted file mode 100644 index 25d8ebe95..000000000 --- a/include/configs/purple.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file contains the configuration parameters for the PURPLE board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MIPS32 1 /* MIPS 5Kc CPU core */ -#define CONFIG_PURPLE 1 /* on a PURPLE Board */ - -#define CPU_CLOCK_RATE 125000000 /* 125 MHz clock for the MIPS core */ -#define ASC_CLOCK_RATE 62500000 /* 62.5 MHz ASC clock */ - -#define INFINEON_EBU_BOOTCFG 0xE0CC - -#define CONFIG_STACKSIZE (128 * 1024) - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 19200 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "ethaddr=${ethaddr} " \ - "panic=1\0" \ - "flash_nfs=run nfsargs addip addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 80500000 ${bootfile};" \ - "run nfsargs addip addmisc;bootm\0" \ - "rootpath=/opt/eldk/mips_5KC\0" \ - "bootfile=/tftpboot/purple/uImage\0" \ - "kernel_addr=B0040000\0" \ - "ramdisk_addr=B0100000\0" \ - "u-boot=/tftpboot/purple/u-boot.bin\0" \ - "load=tftp 80500000 ${u-boot}\0" \ - "update=protect off 1:0-4;era 1:0-4;" \ - "cp.b 80500000 B0000000 ${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ELF - - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#define CONFIG_SYS_MALLOC_LEN 128*1024 - -#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "PURPLE # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE/2) -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ - -#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START 0x80200000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 - -#define CONFIG_MISC_INIT_R - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (35) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */ - -/* The following #defines are needed to get flash environment right */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (6 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (6 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_ADDR 0xB0008000 -#define CONFIG_ENV_SIZE 0x4000 - -#define CONFIG_FLASH_32BIT -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_PLB2800_ETHER -#define CONFIG_NET_MULTI - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * Temporary buffer for serial data until the real serial driver - * is initialised (memtest will destroy this buffer) - */ -#define CONFIG_SYS_SCONSOLE_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET - \ - CONFIG_SYS_DCACHE_SIZE / 2) -#define CONFIG_SYS_SCONSOLE_SIZE (CONFIG_SYS_DCACHE_SIZE / 4) - -#endif /* __CONFIG_H */ diff --git a/include/configs/qong.h b/include/configs/qong.h index e2f7a5e9f..c61a689e5 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -22,7 +22,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/mx31-regs.h> +#include <asm/arch/imx-regs.h> /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ @@ -52,6 +52,7 @@ #define CONFIG_SYS_MX31_UART1 1 #define CONFIG_MXC_GPIO +#define CONFIG_HW_WATCHDOG #define CONFIG_MXC_SPI #define CONFIG_DEFAULT_SPI_BUS 1 diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 59eef5658..06ce3e2b7 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -40,4 +40,5 @@ #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ +#define CONFIG_BOARD_EARLY_INIT_F #endif /* __CONFIG_H */ diff --git a/include/configs/suen3.h b/include/configs/suen3.h index b2730a3ce..2b6f19ee0 100644 --- a/include/configs/suen3.h +++ b/include/configs/suen3.h @@ -43,53 +43,14 @@ #define CONFIG_HOSTNAME suen3 -/* - * Environment variables configurations - */ -#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ -#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 -#define CONFIG_ENV_EEPROM_IS_ON_I2C 1 -#define CONFIG_SYS_EEPROM_WREN 1 -#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) -#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0" - -/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_CMD_SF - -#define CONFIG_SPI_FLASH -#define CONFIG_HARD_SPI -#define CONFIG_KIRKWOOD_SPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */ - -#define FLASH_GPIO_PIN 0x00010000 - -#define MTDIDS_DEFAULT "nand0=orion_nand" -/* test-only: partitioning needs some tuning, this is just for tests */ -#define MTDPARTS_DEFAULT "mtdparts=" \ - "orion_nand:" \ - "-(" CONFIG_KM_UBI_PARTITION_NAME ")" - -#define CONFIG_KM_DEF_ENV_UPDATE \ - "update=" \ - "spi on;sf probe 0;sf erase 0 50000;" \ - "sf write ${u-boot_addr_r} 0 ${filesize};" \ - "spi off\0" +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ - "memsize=0x8000000\0" \ "newenv=setenv addr 0x100000 && " \ "i2c dev 1; mw.b ${addr} 0 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ @@ -97,7 +58,7 @@ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ "rootpath=/opt/eldk/arm\0" \ - "EEprom_ivm=pca9544a:70:9\0" \ + "EEprom_ivm=" KM_IVM_BUS "\0" \ "" #endif /* _CONFIG_SUEN3_H */ diff --git a/include/configs/suen8.h b/include/configs/suen8.h new file mode 100644 index 000000000..3f60bc33f --- /dev/null +++ b/include/configs/suen8.h @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla@marvell.com> + * + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2010-2011 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ + +#ifndef _CONFIG_SUEN8_H +#define _CONFIG_SUEN8_H + +/* include common defines/options for all arm based Keymile boards */ +#include "km_arm.h" + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nKeymile SUEN8" + +#define CONFIG_HOSTNAME suen8 + +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + "newenv=setenv addr 0x100000 && " \ + "i2c dev 1; mw.b ${addr} 0 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ + "rootpath=/opt/eldk/arm\0" \ + "EEprom_ivm=" KM_IVM_BUS "\0" \ + "" + +#endif /* _CONFIG_SUEN8_H */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h new file mode 100644 index 000000000..d9eb20192 --- /dev/null +++ b/include/configs/suvd3.h @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada <peterb@logicpd.com> + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov <avorontsov@ru.mvista.com> + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SUVD3 /* SUVD3 board specific */ +#define CONFIG_HOSTNAME suvd3 +#define CONFIG_KM_BOARD_NAME "suvd3" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 + +/* include common defines/options for all 8321 Keymile boards */ +#include "km8321-common.h" + +#define CONFIG_SYS_APP1_BASE 0xA0000000 +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local UPMA 16 bit 256MB APP1 + * 3 Local GPCM 16 bit 256MB APP2 + * + */ + +/* + * APP1 on the local bus CS2 + */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_16 | \ + BR_MS_UPMA | \ + BR_V) +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_16 | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_3 | \ + OR_GPCM_TRLX) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +/* + * MMU Setup + */ + + +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#endif /* __CONFIG_H */ diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h index 042d78915..52055e80d 100644 --- a/include/configs/tcm-bf518.h +++ b/include/configs/tcm-bf518.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf518-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 9036ce341..8ded17583 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -11,6 +11,7 @@ /* * Processor Settings */ +#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 4f4374a74..febce35ac 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -33,6 +33,8 @@ #define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */ #define CONFIG_L2_OFF /* No L2 cache */ +#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */ + #include <asm/arch/tegra2.h> /* get chip and board defs */ /* @@ -45,6 +47,7 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_OF_LIBFDT /* enable passing of devicetree */ /* Environment */ #define CONFIG_ENV_IS_NOWHERE diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h new file mode 100644 index 000000000..1c0b3e003 --- /dev/null +++ b/include/configs/tuda1.h @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada <peterb@logicpd.com> + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov <avorontsov@ru.mvista.com> + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2011 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_TUDA1 /* TUDA1 board specific */ +#define CONFIG_HOSTNAME tuda1 +#define CONFIG_KM_BOARD_NAME "tuda1" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 + +/* include common defines/options for all 8321 Keymile boards */ +#include "km8321-common.h" + +#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local GPCM 8 bit 256MB PAXG + * 3 Local GPCM 8 bit 256MB PINC3 + * + */ + +/* + * PAXG on the local bus CS2 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + (OR_GPCM_TRLX & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_EAD) +/* + * PINC3 on the local bus CS3 + */ +/* Access window base at PINC3 base */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_CSNT | \ + (OR_GPCM_ACS_DIV2 & /* ACS = 11 */\ + (~OR_GPCM_XACS)) | /* XACS = 0 */\ + (OR_GPCM_SCY_2 & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_TRLX) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +/* + * MMU Setup + */ +/* PAXG: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_10 | \ + BATL_MEMCOHERENCE) +/* 512M should also include APP2... */ +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +/* PINC3: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_H */ diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h new file mode 100644 index 000000000..012db9673 --- /dev/null +++ b/include/configs/tuxa1.h @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada <peterb@logicpd.com> + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov <avorontsov@ru.mvista.com> + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010 + * Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_TUXA1 /* TUXA1 board specific */ +#define CONFIG_HOSTNAME tuxa1 +#define CONFIG_KM_BOARD_NAME "tuxa1" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 + +/* include common defines/options for all 8321 Keymile boards */ +#include "km8321-common.h" + +#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */ +#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_PINC2_BASE 0xB0000000 /* PINC2 */ +#define CONFIG_SYS_PINC2_SIZE 256 /* Megabytes */ + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local GPCM 8 bit 256MB LPXF + * 3 Local GPCM 8 bit 256MB PINC2 + * + */ + +/* + * LPXF on the local bus CS2 + * Window base at flash base + * Window size: 256 MB + */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + (OR_GPCM_TRLX & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_EAD) +/* + * PINC2 on the local bus CS3 + * Access window base at PINC2 base + * Window size: 256 MB + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PINC2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PINC2_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \ + OR_GPCM_CSNT | \ + (OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \ + (~OR_GPCM_XACS)) | /* XACS = 0 */ \ + (OR_GPCM_SCY_2 & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_TRLX) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +/* + * MMU Setup + */ +/* LPXF: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +/* PINC2: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_H */ diff --git a/include/configs/xm250.h b/include/configs/xm250.h index 497cb9198..232baf361 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -61,6 +61,8 @@ /* * I2C bus */ +#define CONFIG_I2C_MV 1 +#define CONFIG_MV_I2C_REG 0x40301680 #define CONFIG_HARD_I2C 1 #define CONFIG_SYS_I2C_SPEED 50000 #define CONFIG_SYS_I2C_SLAVE 0xfe diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index a051913ff..17aab5a7b 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -67,7 +67,7 @@ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#define SPD_EEPROM_ADDRESS1 0x54 +#define SPD_EEPROM_ADDRESS 0x54 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 710e5289c..e895d615a 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -304,14 +304,24 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) #define SPD_MEMTYPE_DDR3 (0x0B) -/* - * Byte 3 Key Byte / Module Type for DDR3 SPD - */ -#define SPD_MODULETYPE_RDIMM (0x01) -#define SPD_MODULETYPE_UDIMM (0x02) -#define SPD_MODULETYPE_SODIMM (0x03) -#define SPD_MODULETYPE_MICRODIMM (0x04) -#define SPD_MODULETYPE_MINIRDIMM (0x05) -#define SPD_MODULETYPE_MINIUDIMM (0x06) +/* DIMM Type for DDR2 SPD (according to v1.3) */ +#define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00) +#define DDR2_SPD_DIMMTYPE_RDIMM (0x01) +#define DDR2_SPD_DIMMTYPE_UDIMM (0x02) +#define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04) +#define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06) +#define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07) +#define DDR2_SPD_DIMMTYPE_MICRO_DIMM (0x08) +#define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10) +#define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20) + +/* Byte 3 Key Byte / Module Type for DDR3 SPD */ +#define DDR3_SPD_MODULETYPE_MASK (0x0f) +#define DDR3_SPD_MODULETYPE_RDIMM (0x01) +#define DDR3_SPD_MODULETYPE_UDIMM (0x02) +#define DDR3_SPD_MODULETYPE_SO_DIMM (0x03) +#define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04) +#define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05) +#define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06) #endif /* _DDR_SPD_H_ */ diff --git a/include/exports.h b/include/exports.h index 638231166..ddd1bf494 100644 --- a/include/exports.h +++ b/include/exports.h @@ -45,7 +45,7 @@ enum { #define XF_VERSION 6 -#if defined(CONFIG_I386) +#if defined(CONFIG_X86) extern gd_t *global_data; #endif diff --git a/include/faraday/ftpmu010.h b/include/faraday/ftpmu010.h new file mode 100644 index 000000000..77c29a998 --- /dev/null +++ b/include/faraday/ftpmu010.h @@ -0,0 +1,244 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Power Management Unit + */ +#ifndef __FTPMU010_H +#define __FTPMU010_H + +#ifndef __ASSEMBLY__ +struct ftpmu010 { + unsigned int IDNMBR0; /* 0x00 */ + unsigned int reserved0; /* 0x04 */ + unsigned int OSCC; /* 0x08 */ + unsigned int PMODE; /* 0x0C */ + unsigned int PMCR; /* 0x10 */ + unsigned int PED; /* 0x14 */ + unsigned int PEDSR; /* 0x18 */ + unsigned int reserved1; /* 0x1C */ + unsigned int PMSR; /* 0x20 */ + unsigned int PGSR; /* 0x24 */ + unsigned int MFPSR; /* 0x28 */ + unsigned int MISC; /* 0x2C */ + unsigned int PDLLCR0; /* 0x30 */ + unsigned int PDLLCR1; /* 0x34 */ + unsigned int AHBMCLKOFF; /* 0x38 */ + unsigned int APBMCLKOFF; /* 0x3C */ + unsigned int DCSRCR0; /* 0x40 */ + unsigned int DCSRCR1; /* 0x44 */ + unsigned int DCSRCR2; /* 0x48 */ + unsigned int SDRAMHTC; /* 0x4C */ + unsigned int PSPR0; /* 0x50 */ + unsigned int PSPR1; /* 0x54 */ + unsigned int PSPR2; /* 0x58 */ + unsigned int PSPR3; /* 0x5C */ + unsigned int PSPR4; /* 0x60 */ + unsigned int PSPR5; /* 0x64 */ + unsigned int PSPR6; /* 0x68 */ + unsigned int PSPR7; /* 0x6C */ + unsigned int PSPR8; /* 0x70 */ + unsigned int PSPR9; /* 0x74 */ + unsigned int PSPR10; /* 0x78 */ + unsigned int PSPR11; /* 0x7C */ + unsigned int PSPR12; /* 0x80 */ + unsigned int PSPR13; /* 0x84 */ + unsigned int PSPR14; /* 0x88 */ + unsigned int PSPR15; /* 0x8C */ + unsigned int AHBDMA_RACCS; /* 0x90 */ + unsigned int reserved2; /* 0x94 */ + unsigned int reserved3; /* 0x98 */ + unsigned int JSS; /* 0x9C */ + unsigned int CFC_RACC; /* 0xA0 */ + unsigned int SSP1_RACC; /* 0xA4 */ + unsigned int UART1TX_RACC; /* 0xA8 */ + unsigned int UART1RX_RACC; /* 0xAC */ + unsigned int UART2TX_RACC; /* 0xB0 */ + unsigned int UART2RX_RACC; /* 0xB4 */ + unsigned int SDC_RACC; /* 0xB8 */ + unsigned int I2SAC97_RACC; /* 0xBC */ + unsigned int IRDATX_RACC; /* 0xC0 */ + unsigned int reserved4; /* 0xC4 */ + unsigned int USBD_RACC; /* 0xC8 */ + unsigned int IRDARX_RACC; /* 0xCC */ + unsigned int IRDA_RACC; /* 0xD0 */ + unsigned int ED0_RACC; /* 0xD4 */ + unsigned int ED1_RACC; /* 0xD8 */ +}; +#endif /* __ASSEMBLY__ */ + +/* + * ID Number 0 Register + */ +#define FTPMU010_ID_A320A 0x03200000 +#define FTPMU010_ID_A320C 0x03200010 +#define FTPMU010_ID_A320D 0x03200030 + +/* + * OSC Control Register + */ +#define FTPMU010_OSCC_OSCH_TRI (1 << 11) +#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) +#define FTPMU010_OSCC_OSCH_OFF (1 << 8) + +#define FTPMU010_OSCC_OSCL_TRI (1 << 3) +#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) +#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) +#define FTPMU010_OSCC_OSCL_OFF (1 << 0) + +/* + * Power Mode Register + */ +#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) +#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) +#define FTPMU010_PMODE_FCS (1 << 2) +#define FTPMU010_PMODE_TURBO (1 << 1) +#define FTPMU010_PMODE_SLEEP (1 << 0) + +/* + * Power Manager Status Register + */ +#define FTPMU010_PMSR_SMR (1 << 10) + +#define FTPMU010_PMSR_RDH (1 << 2) +#define FTPMU010_PMSR_PH (1 << 1) +#define FTPMU010_PMSR_CKEHLOW (1 << 0) + +/* + * Multi-Function Port Setting Register + */ +#define FTPMU010_MFPSR_DEBUGSEL (1 << 17) +#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16) +#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15) +#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) +#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) +#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11) +#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10) +#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9) +#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8) +#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6) +#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5) +#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4) +#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) +#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1) +#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0) + +/* + * PLL/DLL Control Register 0 + * Note: + * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: + * Datasheet indicated it starts at bit #21 which was wrong. + * 2. FTPMU010_PDLLCR0_DLLFRAG: + * Datasheet indicated it has 2 bit which was wrong. + */ +#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) +#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) +#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) +#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) +#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) +#define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) +#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) +#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) +#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) +#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) + +/* + * SDRAM Signal Hold Time Control Register + */ +#define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28) +#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24) +#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20) +#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18) +#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17) +#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16) +#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15) +#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14) +#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13) +#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12) + +#ifndef __ASSEMBLY__ +void ftpmu010_32768osc_enable(void); +void ftpmu010_dlldis_disable(void); +void ftpmu010_sdram_clk_disable(unsigned int cr0); +#endif + +#ifdef __ASSEMBLY__ +#define FTPMU010_IDNMBR0 0x00 +#define FTPMU010_reserved0 0x04 +#define FTPMU010_OSCC 0x08 +#define FTPMU010_PMODE 0x0C +#define FTPMU010_PMCR 0x10 +#define FTPMU010_PED 0x14 +#define FTPMU010_PEDSR 0x18 +#define FTPMU010_reserved1 0x1C +#define FTPMU010_PMSR 0x20 +#define FTPMU010_PGSR 0x24 +#define FTPMU010_MFPSR 0x28 +#define FTPMU010_MISC 0x2C +#define FTPMU010_PDLLCR0 0x30 +#define FTPMU010_PDLLCR1 0x34 +#define FTPMU010_AHBMCLKOFF 0x38 +#define FTPMU010_APBMCLKOFF 0x3C +#define FTPMU010_DCSRCR0 0x40 +#define FTPMU010_DCSRCR1 0x44 +#define FTPMU010_DCSRCR2 0x48 +#define FTPMU010_SDRAMHTC 0x4C +#define FTPMU010_PSPR0 0x50 +#define FTPMU010_PSPR1 0x54 +#define FTPMU010_PSPR2 0x58 +#define FTPMU010_PSPR3 0x5C +#define FTPMU010_PSPR4 0x60 +#define FTPMU010_PSPR5 0x64 +#define FTPMU010_PSPR6 0x68 +#define FTPMU010_PSPR7 0x6C +#define FTPMU010_PSPR8 0x70 +#define FTPMU010_PSPR9 0x74 +#define FTPMU010_PSPR10 0x78 +#define FTPMU010_PSPR11 0x7C +#define FTPMU010_PSPR12 0x80 +#define FTPMU010_PSPR13 0x84 +#define FTPMU010_PSPR14 0x88 +#define FTPMU010_PSPR15 0x8C +#define FTPMU010_AHBDMA_RACCS 0x90 +#define FTPMU010_reserved2 0x94 +#define FTPMU010_reserved3 0x98 +#define FTPMU010_JSS 0x9C +#define FTPMU010_CFC_RACC 0xA0 +#define FTPMU010_SSP1_RACC 0xA4 +#define FTPMU010_UART1TX_RACC 0xA8 +#define FTPMU010_UART1RX_RACC 0xAC +#define FTPMU010_UART2TX_RACC 0xB0 +#define FTPMU010_UART2RX_RACC 0xB4 +#define FTPMU010_SDC_RACC 0xB8 +#define FTPMU010_I2SAC97_RACC 0xBC +#define FTPMU010_IRDATX_RACC 0xC0 +#define FTPMU010_reserved4 0xC4 +#define FTPMU010_USBD_RACC 0xC8 +#define FTPMU010_IRDARX_RACC 0xCC +#define FTPMU010_IRDA_RACC 0xD0 +#define FTPMU010_ED0_RACC 0xD4 +#define FTPMU010_ED1_RACC 0xD8 +#endif /* __ASSEMBLY__ */ + +#endif /* __FTPMU010_H */ diff --git a/include/faraday/ftsdmc020.h b/include/faraday/ftsdmc020.h new file mode 100644 index 000000000..069977200 --- /dev/null +++ b/include/faraday/ftsdmc020.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * SDRAM Controller + */ +#ifndef __FTSDMC020_H +#define __FTSDMC020_H + +#define FTSDMC020_OFFSET_TP0 0x00 +#define FTSDMC020_OFFSET_TP1 0x04 +#define FTSDMC020_OFFSET_CR 0x08 +#define FTSDMC020_OFFSET_BANK0_BSR 0x0C +#define FTSDMC020_OFFSET_BANK1_BSR 0x10 +#define FTSDMC020_OFFSET_BANK2_BSR 0x14 +#define FTSDMC020_OFFSET_BANK3_BSR 0x18 +#define FTSDMC020_OFFSET_BANK4_BSR 0x1C +#define FTSDMC020_OFFSET_BANK5_BSR 0x20 +#define FTSDMC020_OFFSET_BANK6_BSR 0x24 +#define FTSDMC020_OFFSET_BANK7_BSR 0x28 +#define FTSDMC020_OFFSET_ACR 0x34 + +/* + * Timing Parametet 0 Register + */ +#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) +#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) +#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) +#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) +#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) + +/* + * Timing Parametet 1 Register + */ +#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) +#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) + +/* + * Configuration Register + */ +#define FTSDMC020_CR_SREF (1 << 0) +#define FTSDMC020_CR_PWDN (1 << 1) +#define FTSDMC020_CR_ISMR (1 << 2) +#define FTSDMC020_CR_IREF (1 << 3) +#define FTSDMC020_CR_IPREC (1 << 4) +#define FTSDMC020_CR_REFTYPE (1 << 5) + +/* + * SDRAM External Bank Base/Size Register + */ +#define FTSDMC020_BANK_ENABLE (1 << 28) + +#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) + +#define FTSDMC020_BANK_DDW_X4 (0 << 12) +#define FTSDMC020_BANK_DDW_X8 (1 << 12) +#define FTSDMC020_BANK_DDW_X16 (2 << 12) +#define FTSDMC020_BANK_DDW_X32 (3 << 12) + +#define FTSDMC020_BANK_DSZ_16M (0 << 8) +#define FTSDMC020_BANK_DSZ_64M (1 << 8) +#define FTSDMC020_BANK_DSZ_128M (2 << 8) +#define FTSDMC020_BANK_DSZ_256M (3 << 8) + +#define FTSDMC020_BANK_MBW_8 (0 << 4) +#define FTSDMC020_BANK_MBW_16 (1 << 4) +#define FTSDMC020_BANK_MBW_32 (2 << 4) + +#define FTSDMC020_BANK_SIZE_1M 0x0 +#define FTSDMC020_BANK_SIZE_2M 0x1 +#define FTSDMC020_BANK_SIZE_4M 0x2 +#define FTSDMC020_BANK_SIZE_8M 0x3 +#define FTSDMC020_BANK_SIZE_16M 0x4 +#define FTSDMC020_BANK_SIZE_32M 0x5 +#define FTSDMC020_BANK_SIZE_64M 0x6 +#define FTSDMC020_BANK_SIZE_128M 0x7 +#define FTSDMC020_BANK_SIZE_256M 0x8 + +/* + * Arbiter Control Register + */ +#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) +#define FTSDMC020_ACR_TOE (1 << 8) + +#endif /* __FTSDMC020_H */ diff --git a/include/faraday/ftsmc020.h b/include/faraday/ftsmc020.h new file mode 100644 index 000000000..95d950033 --- /dev/null +++ b/include/faraday/ftsmc020.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Static Memory Controller + */ +#ifndef __FTSMC020_H +#define __FTSMC020_H + +#ifndef __ASSEMBLY__ + +struct ftsmc020 { + struct { + unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ + unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ + } bank[4]; + unsigned int pad[8]; /* 0x20 - 0x3c */ + unsigned int ssr; /* 0x40 */ +}; + +void ftsmc020_init(void); + +#endif /* __ASSEMBLY__ */ + +/* + * Memory Bank Configuration Register + */ +#define FTSMC020_BANK_ENABLE (1 << 28) +#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) + +#define FTSMC020_BANK_WPROT (1 << 11) + +#define FTSMC020_BANK_SIZE_32K (0xb << 4) +#define FTSMC020_BANK_SIZE_64K (0xc << 4) +#define FTSMC020_BANK_SIZE_128K (0xd << 4) +#define FTSMC020_BANK_SIZE_256K (0xe << 4) +#define FTSMC020_BANK_SIZE_512K (0xf << 4) +#define FTSMC020_BANK_SIZE_1M (0x0 << 4) +#define FTSMC020_BANK_SIZE_2M (0x1 << 4) +#define FTSMC020_BANK_SIZE_4M (0x2 << 4) +#define FTSMC020_BANK_SIZE_8M (0x3 << 4) +#define FTSMC020_BANK_SIZE_16M (0x4 << 4) +#define FTSMC020_BANK_SIZE_32M (0x5 << 4) + +#define FTSMC020_BANK_MBW_8 (0x0 << 0) +#define FTSMC020_BANK_MBW_16 (0x1 << 0) +#define FTSMC020_BANK_MBW_32 (0x2 << 0) + +/* + * Memory Bank Timing Parameter Register + */ +#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) +#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) +#define FTSMC020_TPR_RBE (1 << 20) +#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) +#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) +#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) +#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) +#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) +#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) +#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) + +#endif /* __FTSMC020_H */ diff --git a/include/faraday/fttmr010.h b/include/faraday/fttmr010.h new file mode 100644 index 000000000..72abcb365 --- /dev/null +++ b/include/faraday/fttmr010.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Timer + */ +#ifndef __FTTMR010_H +#define __FTTMR010_H + +struct fttmr010 { + unsigned int timer1_counter; /* 0x00 */ + unsigned int timer1_load; /* 0x04 */ + unsigned int timer1_match1; /* 0x08 */ + unsigned int timer1_match2; /* 0x0c */ + unsigned int timer2_counter; /* 0x10 */ + unsigned int timer2_load; /* 0x14 */ + unsigned int timer2_match1; /* 0x18 */ + unsigned int timer2_match2; /* 0x1c */ + unsigned int timer3_counter; /* 0x20 */ + unsigned int timer3_load; /* 0x24 */ + unsigned int timer3_match1; /* 0x28 */ + unsigned int timer3_match2; /* 0x2c */ + unsigned int cr; /* 0x30 */ + unsigned int interrupt_state; /* 0x34 */ + unsigned int interrupt_mask; /* 0x38 */ +}; + +/* + * Timer Control Register + */ +#define FTTMR010_TM3_UPDOWN (1 << 11) +#define FTTMR010_TM2_UPDOWN (1 << 10) +#define FTTMR010_TM1_UPDOWN (1 << 9) +#define FTTMR010_TM3_OFENABLE (1 << 8) +#define FTTMR010_TM3_CLOCK (1 << 7) +#define FTTMR010_TM3_ENABLE (1 << 6) +#define FTTMR010_TM2_OFENABLE (1 << 5) +#define FTTMR010_TM2_CLOCK (1 << 4) +#define FTTMR010_TM2_ENABLE (1 << 3) +#define FTTMR010_TM1_OFENABLE (1 << 2) +#define FTTMR010_TM1_CLOCK (1 << 1) +#define FTTMR010_TM1_ENABLE (1 << 0) + +/* + * Timer Interrupt State & Mask Registers + */ +#define FTTMR010_TM3_OVERFLOW (1 << 8) +#define FTTMR010_TM3_MATCH2 (1 << 7) +#define FTTMR010_TM3_MATCH1 (1 << 6) +#define FTTMR010_TM2_OVERFLOW (1 << 5) +#define FTTMR010_TM2_MATCH2 (1 << 4) +#define FTTMR010_TM2_MATCH1 (1 << 3) +#define FTTMR010_TM1_OVERFLOW (1 << 2) +#define FTTMR010_TM1_MATCH2 (1 << 1) +#define FTTMR010_TM1_MATCH1 (1 << 0) + +#endif /* __FTTMR010_H */ diff --git a/include/faraday/ftwdt010_wdt.h b/include/faraday/ftwdt010_wdt.h new file mode 100644 index 000000000..31ca76811 --- /dev/null +++ b/include/faraday/ftwdt010_wdt.h @@ -0,0 +1,106 @@ +/* + * Watchdog driver for the FTWDT010 Watch Dog Driver + * + * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com) + * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu> + * Based on SoftDog driver by Alan Cox <alan@redhat.com> + * + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * 27/11/2004 Initial release, Faraday. + * 12/01/2011 Port to u-boot, Macpaul Lin. + */ + +#ifndef __FTWDT010_H +#define __FTWDT010_H + +struct ftwdt010_wdt { + unsigned int wdcounter; /* Counter Reg - 0x00 */ + unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */ + unsigned int wdrestart; /* Counter Restart Reg - 0x08 */ + unsigned int wdcr; /* Control Reg - 0x0c */ + unsigned int wdstatus; /* Status Reg - 0x10 */ + unsigned int wdclear; /* Timer Clear - 0x14 */ + unsigned int wdintrlen; /* Interrupt Length - 0x18 */ +}; + +/* + * WDLOAD - Counter Auto Reload Register + * The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default. + * Which means in a 66MHz system, the period of Watch Dog timer reset is + * one second. + */ +#define FTWDT010_WDLOAD(x) ((x) & 0xffffffff) + +/* + * WDRESTART - Watch Dog Timer Counter Restart Register + * If writing 0x5AB9 to WDRESTART register, Watch Dog timer will + * automatically reload WDLOAD to WDCOUNTER and restart counting. + */ +#define FTWDT010_WDRESTART_MAGIC 0x5AB9 + +/* WDCR - Watch Dog Timer Control Register */ +#define FTWDT010_WDCR_ENABLE (1 << 0) +#define FTWDT010_WDCR_RST (1 << 1) +#define FTWDT010_WDCR_INTR (1 << 2) +/* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */ +#define FTWDT010_WDCR_EXT (1 << 3) +/* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK. + * The clock source PCLK cannot be gated when system sleeps, even if + * WDCLOCK bit is turned on. + * + * Faraday's Watch Dog timer can be driven by an external clock. The + * programmer just needs to write one to WdCR[WdClock] bit. + * + * Note: There is a limitation between EXTCLK and PCLK: + * EXTCLK cycle time / PCLK cycle time > 2. + * If the system does not need an external clock, + * just keep WdCR[WdClock] bit in its default value. + */ +#define FTWDT010_WDCR_CLOCK (1 << 4) + +/* + * WDSTATUS - Watch Dog Timer Status Register + * This bit is set when the counter reaches Zero + */ +#define FTWDT010_WDSTATUS(x) ((x) & 0x1) + +/* + * WDCLEAR - Watch Dog Timer Clear Register + * Writing one to this register will clear WDSTATUS. + */ +#define FTWDT010_WDCLEAR (1 << 0) + +/* + * WDINTRLEN - Watch Dog Timer Interrupt Length + * This register controls the duration length of wd_rst, wd_intr and wd_ext. + * The default value is 0xFF. + */ +#define FTWDT010_WDINTRLEN(x) ((x) & 0xff) + +/* + * Variable timeout should be set in ms. + * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms. + * WDLOAD = timeout * TIMEOUT_FACTOR. + */ +#define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */ + +void ftwdt010_wdt_reset(void); +void ftwdt010_wdt_disable(void); + +#endif /* __FTWDT010_H */ diff --git a/include/flash.h b/include/flash.h index 1b6821a0e..0ca70d9c9 100644 --- a/include/flash.h +++ b/include/flash.h @@ -92,6 +92,7 @@ typedef unsigned long flash_sect_t; /* Prototypes */ extern unsigned long flash_init (void); +extern void flash_protect_default(void); extern void flash_print_info (flash_info_t *); extern int flash_erase (flash_info_t *, int, int); extern int flash_sect_erase (ulong addr_first, ulong addr_last); diff --git a/include/fsl_diu_fb.h b/include/fsl_diu_fb.h index 87443e10c..4c89f4b8b 100644 --- a/include/fsl_diu_fb.h +++ b/include/fsl_diu_fb.h @@ -1,6 +1,7 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. - * York Sun <yorksun@freescale.com> + * Copyright 2007, 2011 Freescale Semiconductor, Inc. + * Authors: York Sun <yorksun@freescale.com> + * Timur Tabi <timur@freescale.com> * * FSL DIU Framebuffer driver * @@ -23,38 +24,8 @@ * MA 02111-1307 USA */ -struct fb_var_screeninfo { - unsigned int xres; /* visible resolution */ - unsigned int yres; +int fsl_diu_init(int xres, u32 pixel_format, int gamma_fix); - unsigned int bits_per_pixel; /* guess what */ - - /* Timing: All values in pixclocks, except pixclock (of course) */ - unsigned int pixclock; /* pixel clock in ps (pico seconds) */ - unsigned int left_margin; /* time from sync to picture */ - unsigned int right_margin; /* time from picture to sync */ - unsigned int upper_margin; /* time from sync to picture */ - unsigned int lower_margin; - unsigned int hsync_len; /* length of horizontal sync */ - unsigned int vsync_len; /* length of vertical sync */ - unsigned int sync; /* see FB_SYNC_* */ - unsigned int vmode; /* see FB_VMODE_* */ - unsigned int rotate; /* angle we rotate counter clockwise */ -}; - -struct fb_info { - struct fb_var_screeninfo var; /* Current var */ - unsigned long smem_start; /* Start of frame buffer mem */ - /* (physical address) */ - unsigned int smem_len; /* Length of frame buffer mem */ - unsigned int type; /* see FB_TYPE_* */ - unsigned int line_length; /* length of a line in bytes */ - - char *screen_base; - unsigned long screen_size; -}; - - -extern char *fsl_fb_open(struct fb_info **info); -int fsl_diu_init(int xres, unsigned int pixel_format, int gamma_fix); -int platform_diu_init(unsigned int *xres, unsigned int *yres); +/* Prototypes for external board-specific functions */ +int platform_diu_init(unsigned int xres, unsigned int yres, const char *port); +void diu_set_pixel_clock(unsigned int pixclock); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 477bbd792..8418bf7f4 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -2,7 +2,7 @@ * FSL SD/MMC Defines *------------------------------------------------------------------- * - * Copyright 2007-2008,2010 Freescale Semiconductor, Inc + * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -135,8 +135,21 @@ #define WML 0x2e044 #define WML_WRITE 0x00010000 +#ifdef CONFIG_FSL_SDHC_V2_3 +#define WML_RD_WML_MAX 0x80 +#define WML_WR_WML_MAX 0x80 +#define WML_RD_WML_MAX_VAL 0x0 +#define WML_WR_WML_MAX_VAL 0x0 +#define WML_RD_WML_MASK 0x7f +#define WML_WR_WML_MASK 0x7f0000 +#else +#define WML_RD_WML_MAX 0x10 +#define WML_WR_WML_MAX 0x80 +#define WML_RD_WML_MAX_VAL 0x10 +#define WML_WR_WML_MAX_VAL 0x80 #define WML_RD_WML_MASK 0xff #define WML_WR_WML_MASK 0xff0000 +#endif #define BLKATTR 0x2e004 #define BLKATTR_CNT(x) ((x & 0xffff) << 16) diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h new file mode 100644 index 000000000..17ca79c90 --- /dev/null +++ b/include/fsl_mdio.h @@ -0,0 +1,62 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Jun-jie Zhang <b18070@freescale.com> + * Mingkai Hu <Mingkai.hu@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __FSL_PHY_H__ +#define __FSL_PHY_H__ + +#include <net.h> +#include <miiphy.h> +#include <asm/fsl_enet.h> + +/* PHY register offsets */ +#define PHY_EXT_PAGE_ACCESS 0x1f + +/* MII Management Configuration Register */ +#define MIIMCFG_RESET_MGMT 0x80000000 +#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007 +#define MIIMCFG_INIT_VALUE 0x00000003 + +/* MII Management Command Register */ +#define MIIMCOM_READ_CYCLE 0x00000001 +#define MIIMCOM_SCAN_CYCLE 0x00000002 + +/* MII Management Address Register */ +#define MIIMADD_PHY_ADDR_SHIFT 8 + +/* MII Management Indicator Register */ +#define MIIMIND_BUSY 0x00000001 +#define MIIMIND_NOTVALID 0x00000004 + +void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr, + int dev_addr, int reg, int value); +int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, + int dev_addr, int regnum); +int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum); +int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, + u16 value); + +struct fsl_pq_mdio_info { + struct tsec_mii_mng *regs; + char *name; +}; +int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info); + +#endif /* __FSL_PHY_H__ */ + diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 1fccd27cc..c0b1b5c3d 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -50,6 +50,9 @@ typedef struct ihs_osd { u16 features; u16 control; u16 xy_size; + u16 xy_scale; + u16 x_pos; + u16 y_pos; } ihs_osd_t; #ifdef CONFIG_IO @@ -79,7 +82,7 @@ typedef struct ihs_fpga { u16 reserved_2[93]; /* 0x0044 */ u16 reflection_high; /* 0x00fe */ ihs_osd_t osd; /* 0x0100 */ - u16 reserved_3[892]; /* 0x0108 */ + u16 reserved_3[88]; /* 0x010e */ u16 videomem; /* 0x0800 */ } ihs_fpga_t; #endif @@ -94,13 +97,13 @@ typedef struct ihs_fpga { u16 extended_interrupt; /* 0x001c */ u16 reserved_1[9]; /* 0x001e */ ihs_i2c_t i2c; /* 0x0030 */ - u16 reserved_2[35]; /* 0x0038 */ - u16 reflection_high; /* 0x007e */ - u16 reserved_3[15]; /* 0x0080 */ + u16 reserved_2[16]; /* 0x0038 */ + u16 mpc3w_control; /* 0x0058 */ + u16 reserved_3[34]; /* 0x005a */ u16 videocontrol; /* 0x009e */ u16 reserved_4[176]; /* 0x00a0 */ ihs_osd_t osd; /* 0x0200 */ - u16 reserved_5[764]; /* 0x0208 */ + u16 reserved_5[761]; /* 0x020e */ u16 videomem; /* 0x0800 */ } ihs_fpga_t; #endif diff --git a/include/i2c.h b/include/i2c.h index cd23c8ac1..8ceb4c852 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -108,9 +108,7 @@ * repeatedly to change the speed and slave addresses. */ void i2c_init(int speed, int slaveaddr); -#ifdef CONFIG_SYS_I2C_INIT_BOARD void i2c_init_board(void); -#endif #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT void i2c_board_late_init(void); #endif diff --git a/include/ide.h b/include/ide.h index 6a1b7ae84..8ecc9dd3a 100644 --- a/include/ide.h +++ b/include/ide.h @@ -52,9 +52,16 @@ typedef ulong lbaint_t; void ide_init(void); ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer); -ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, void *buffer); +ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, const void *buffer); #if defined(CONFIG_OF_IDE_FIXUP) int ide_device_present(int dev); #endif + +#if defined(CONFIG_IDE_AHB) +unsigned char ide_read_register(int dev, unsigned int port); +void ide_write_register(int dev, unsigned int port, unsigned char val); +void ide_read_data(int dev, ulong *sect_buf, int words); +void ide_write_data(int dev, ulong *sect_buf, int words); +#endif #endif /* _IDE_H */ diff --git a/include/image.h b/include/image.h index 005e0d24e..c31e862d3 100644 --- a/include/image.h +++ b/include/image.h @@ -336,8 +336,8 @@ int boot_get_ramdisk (int argc, char * const argv[], bootm_headers_t *images, #ifdef CONFIG_OF_LIBFDT int boot_get_fdt (int flag, int argc, char * const argv[], bootm_headers_t *images, char **of_flat_tree, ulong *of_size); -int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base, - char **of_flat_tree, ulong *of_size); +void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob); +int boot_relocate_fdt (struct lmb *lmb, char **of_flat_tree, ulong *of_size); #endif #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH @@ -345,11 +345,10 @@ int boot_ramdisk_high (struct lmb *lmb, ulong rd_data, ulong rd_len, ulong *initrd_start, ulong *initrd_end); #endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */ #ifdef CONFIG_SYS_BOOT_GET_CMDLINE -int boot_get_cmdline (struct lmb *lmb, ulong *cmd_start, ulong *cmd_end, - ulong bootmap_base); +int boot_get_cmdline (struct lmb *lmb, ulong *cmd_start, ulong *cmd_end); #endif /* CONFIG_SYS_BOOT_GET_CMDLINE */ #ifdef CONFIG_SYS_BOOT_GET_KBD -int boot_get_kbd (struct lmb *lmb, bd_t **kbd, ulong bootmap_base); +int boot_get_kbd (struct lmb *lmb, bd_t **kbd); #endif /* CONFIG_SYS_BOOT_GET_KBD */ #endif /* !USE_HOSTCC */ @@ -453,6 +452,7 @@ int image_check_dcrc (const image_header_t *hdr); int getenv_yesno (char *var); ulong getenv_bootm_low(void); phys_size_t getenv_bootm_size(void); +phys_size_t getenv_bootm_mapsize(void); void memmove_wd (void *to, void *from, size_t len, ulong chunksz); #endif diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h new file mode 100644 index 000000000..fcb20fe10 --- /dev/null +++ b/include/linux/ethtool.h @@ -0,0 +1,721 @@ +/* + * ethtool.h: Defines for Linux ethtool. + * + * Copyright (C) 1998 David S. Miller (davem@redhat.com) + * Copyright 2001 Jeff Garzik <jgarzik@pobox.com> + * Portions Copyright 2001 Sun Microsystems (thockin@sun.com) + * Portions Copyright 2002 Intel (eli.kupermann@intel.com, + * christopher.leech@intel.com, + * scott.feldman@intel.com) + * Portions Copyright (C) Sun Microsystems 2008 + */ + +#ifndef _LINUX_ETHTOOL_H +#define _LINUX_ETHTOOL_H + +#include <linux/types.h> + +/* This should work for both 32 and 64 bit userland. */ +struct ethtool_cmd { + __u32 cmd; + __u32 supported; /* Features this interface supports */ + __u32 advertising; /* Features this interface advertises */ + __u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */ + __u8 duplex; /* Duplex, half or full */ + __u8 port; /* Which connector port */ + __u8 phy_address; + __u8 transceiver; /* Which transceiver to use */ + __u8 autoneg; /* Enable or disable autonegotiation */ + __u8 mdio_support; + __u32 maxtxpkt; /* Tx pkts before generating tx int */ + __u32 maxrxpkt; /* Rx pkts before generating rx int */ + __u16 speed_hi; + __u8 eth_tp_mdix; + __u8 reserved2; + __u32 lp_advertising; /* Features the link partner advertises */ + __u32 reserved[2]; +}; + +static inline void ethtool_cmd_speed_set(struct ethtool_cmd *ep, + __u32 speed) +{ + + ep->speed = (__u16)speed; + ep->speed_hi = (__u16)(speed >> 16); +} + +static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep) +{ + return (ep->speed_hi << 16) | ep->speed; +} + +#define ETHTOOL_FWVERS_LEN 32 +#define ETHTOOL_BUSINFO_LEN 32 +/* these strings are set to whatever the driver author decides... */ +struct ethtool_drvinfo { + __u32 cmd; + char driver[32]; /* driver short name, "tulip", "eepro100" */ + char version[32]; /* driver version string */ + char fw_version[ETHTOOL_FWVERS_LEN]; /* firmware version string */ + char bus_info[ETHTOOL_BUSINFO_LEN]; /* Bus info for this IF. */ + /* For PCI devices, use pci_name(pci_dev). */ + char reserved1[32]; + char reserved2[12]; + /* + * Some struct members below are filled in + * using ops->get_sset_count(). Obtaining + * this info from ethtool_drvinfo is now + * deprecated; Use ETHTOOL_GSSET_INFO + * instead. + */ + __u32 n_priv_flags; /* number of flags valid in ETHTOOL_GPFLAGS */ + __u32 n_stats; /* number of u64's from ETHTOOL_GSTATS */ + __u32 testinfo_len; + __u32 eedump_len; /* Size of data from ETHTOOL_GEEPROM (bytes) */ + __u32 regdump_len; /* Size of data from ETHTOOL_GREGS (bytes) */ +}; + +#define SOPASS_MAX 6 +/* wake-on-lan settings */ +struct ethtool_wolinfo { + __u32 cmd; + __u32 supported; + __u32 wolopts; + __u8 sopass[SOPASS_MAX]; /* SecureOn(tm) password */ +}; + +/* for passing single values */ +struct ethtool_value { + __u32 cmd; + __u32 data; +}; + +/* for passing big chunks of data */ +struct ethtool_regs { + __u32 cmd; + __u32 version; /* driver-specific, indicates different chips/revs */ + __u32 len; /* bytes */ + __u8 data[0]; +}; + +/* for passing EEPROM chunks */ +struct ethtool_eeprom { + __u32 cmd; + __u32 magic; + __u32 offset; /* in bytes */ + __u32 len; /* in bytes */ + __u8 data[0]; +}; + +/* for configuring coalescing parameters of chip */ +struct ethtool_coalesce { + __u32 cmd; /* ETHTOOL_{G,S}COALESCE */ + + /* How many usecs to delay an RX interrupt after + * a packet arrives. If 0, only rx_max_coalesced_frames + * is used. + */ + __u32 rx_coalesce_usecs; + + /* How many packets to delay an RX interrupt after + * a packet arrives. If 0, only rx_coalesce_usecs is + * used. It is illegal to set both usecs and max frames + * to zero as this would cause RX interrupts to never be + * generated. + */ + __u32 rx_max_coalesced_frames; + + /* Same as above two parameters, except that these values + * apply while an IRQ is being serviced by the host. Not + * all cards support this feature and the values are ignored + * in that case. + */ + __u32 rx_coalesce_usecs_irq; + __u32 rx_max_coalesced_frames_irq; + + /* How many usecs to delay a TX interrupt after + * a packet is sent. If 0, only tx_max_coalesced_frames + * is used. + */ + __u32 tx_coalesce_usecs; + + /* How many packets to delay a TX interrupt after + * a packet is sent. If 0, only tx_coalesce_usecs is + * used. It is illegal to set both usecs and max frames + * to zero as this would cause TX interrupts to never be + * generated. + */ + __u32 tx_max_coalesced_frames; + + /* Same as above two parameters, except that these values + * apply while an IRQ is being serviced by the host. Not + * all cards support this feature and the values are ignored + * in that case. + */ + __u32 tx_coalesce_usecs_irq; + __u32 tx_max_coalesced_frames_irq; + + /* How many usecs to delay in-memory statistics + * block updates. Some drivers do not have an in-memory + * statistic block, and in such cases this value is ignored. + * This value must not be zero. + */ + __u32 stats_block_coalesce_usecs; + + /* Adaptive RX/TX coalescing is an algorithm implemented by + * some drivers to improve latency under low packet rates and + * improve throughput under high packet rates. Some drivers + * only implement one of RX or TX adaptive coalescing. Anything + * not implemented by the driver causes these values to be + * silently ignored. + */ + __u32 use_adaptive_rx_coalesce; + __u32 use_adaptive_tx_coalesce; + + /* When the packet rate (measured in packets per second) + * is below pkt_rate_low, the {rx,tx}_*_low parameters are + * used. + */ + __u32 pkt_rate_low; + __u32 rx_coalesce_usecs_low; + __u32 rx_max_coalesced_frames_low; + __u32 tx_coalesce_usecs_low; + __u32 tx_max_coalesced_frames_low; + + /* When the packet rate is below pkt_rate_high but above + * pkt_rate_low (both measured in packets per second) the + * normal {rx,tx}_* coalescing parameters are used. + */ + + /* When the packet rate is (measured in packets per second) + * is above pkt_rate_high, the {rx,tx}_*_high parameters are + * used. + */ + __u32 pkt_rate_high; + __u32 rx_coalesce_usecs_high; + __u32 rx_max_coalesced_frames_high; + __u32 tx_coalesce_usecs_high; + __u32 tx_max_coalesced_frames_high; + + /* How often to do adaptive coalescing packet rate sampling, + * measured in seconds. Must not be zero. + */ + __u32 rate_sample_interval; +}; + +/* for configuring RX/TX ring parameters */ +struct ethtool_ringparam { + __u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */ + + /* Read only attributes. These indicate the maximum number + * of pending RX/TX ring entries the driver will allow the + * user to set. + */ + __u32 rx_max_pending; + __u32 rx_mini_max_pending; + __u32 rx_jumbo_max_pending; + __u32 tx_max_pending; + + /* Values changeable by the user. The valid values are + * in the range 1 to the "*_max_pending" counterpart above. + */ + __u32 rx_pending; + __u32 rx_mini_pending; + __u32 rx_jumbo_pending; + __u32 tx_pending; +}; + +/* for configuring link flow control parameters */ +struct ethtool_pauseparam { + __u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */ + + /* If the link is being auto-negotiated (via ethtool_cmd.autoneg + * being true) the user may set 'autonet' here non-zero to have the + * pause parameters be auto-negotiated too. In such a case, the + * {rx,tx}_pause values below determine what capabilities are + * advertised. + * + * If 'autoneg' is zero or the link is not being auto-negotiated, + * then {rx,tx}_pause force the driver to use/not-use pause + * flow control. + */ + __u32 autoneg; + __u32 rx_pause; + __u32 tx_pause; +}; + +#define ETH_GSTRING_LEN 32 +enum ethtool_stringset { + ETH_SS_TEST = 0, + ETH_SS_STATS, + ETH_SS_PRIV_FLAGS, + ETH_SS_NTUPLE_FILTERS, + ETH_SS_FEATURES, +}; + +/* for passing string sets for data tagging */ +struct ethtool_gstrings { + __u32 cmd; /* ETHTOOL_GSTRINGS */ + __u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/ + __u32 len; /* number of strings in the string set */ + __u8 data[0]; +}; + +struct ethtool_sset_info { + __u32 cmd; /* ETHTOOL_GSSET_INFO */ + __u32 reserved; + __u64 sset_mask; /* input: each bit selects an sset to query */ + /* output: each bit a returned sset */ + __u32 data[0]; /* ETH_SS_xxx count, in order, based on bits + in sset_mask. One bit implies one + __u32, two bits implies two + __u32's, etc. */ +}; + +enum ethtool_test_flags { + ETH_TEST_FL_OFFLINE = (1 << 0), /* online / offline */ + ETH_TEST_FL_FAILED = (1 << 1), /* test passed / failed */ +}; + +/* for requesting NIC test and getting results*/ +struct ethtool_test { + __u32 cmd; /* ETHTOOL_TEST */ + __u32 flags; /* ETH_TEST_FL_xxx */ + __u32 reserved; + __u32 len; /* result length, in number of u64 elements */ + __u64 data[0]; +}; + +/* for dumping NIC-specific statistics */ +struct ethtool_stats { + __u32 cmd; /* ETHTOOL_GSTATS */ + __u32 n_stats; /* number of u64's being returned */ + __u64 data[0]; +}; + +struct ethtool_perm_addr { + __u32 cmd; /* ETHTOOL_GPERMADDR */ + __u32 size; + __u8 data[0]; +}; + +/* boolean flags controlling per-interface behavior characteristics. + * When reading, the flag indicates whether or not a certain behavior + * is enabled/present. When writing, the flag indicates whether + * or not the driver should turn on (set) or off (clear) a behavior. + * + * Some behaviors may read-only (unconditionally absent or present). + * If such is the case, return EINVAL in the set-flags operation if the + * flag differs from the read-only value. + */ +enum ethtool_flags { + ETH_FLAG_TXVLAN = (1 << 7), /* TX VLAN offload enabled */ + ETH_FLAG_RXVLAN = (1 << 8), /* RX VLAN offload enabled */ + ETH_FLAG_LRO = (1 << 15), /* LRO is enabled */ + ETH_FLAG_NTUPLE = (1 << 27), /* N-tuple filters enabled */ + ETH_FLAG_RXHASH = (1 << 28), +}; + +/* The following structures are for supporting RX network flow + * classification and RX n-tuple configuration. Note, all multibyte + * fields, e.g., ip4src, ip4dst, psrc, pdst, spi, etc. are expected to + * be in network byte order. + */ + +/** + * struct ethtool_tcpip4_spec - flow specification for TCP/IPv4 etc. + * @ip4src: Source host + * @ip4dst: Destination host + * @psrc: Source port + * @pdst: Destination port + * @tos: Type-of-service + * + * This can be used to specify a TCP/IPv4, UDP/IPv4 or SCTP/IPv4 flow. + */ +struct ethtool_tcpip4_spec { + __be32 ip4src; + __be32 ip4dst; + __be16 psrc; + __be16 pdst; + __u8 tos; +}; + +/** + * struct ethtool_ah_espip4_spec - flow specification for IPsec/IPv4 + * @ip4src: Source host + * @ip4dst: Destination host + * @spi: Security parameters index + * @tos: Type-of-service + * + * This can be used to specify an IPsec transport or tunnel over IPv4. + */ +struct ethtool_ah_espip4_spec { + __be32 ip4src; + __be32 ip4dst; + __be32 spi; + __u8 tos; +}; + +#define ETH_RX_NFC_IP4 1 + +/** + * struct ethtool_usrip4_spec - general flow specification for IPv4 + * @ip4src: Source host + * @ip4dst: Destination host + * @l4_4_bytes: First 4 bytes of transport (layer 4) header + * @tos: Type-of-service + * @ip_ver: Value must be %ETH_RX_NFC_IP4; mask must be 0 + * @proto: Transport protocol number; mask must be 0 + */ +struct ethtool_usrip4_spec { + __be32 ip4src; + __be32 ip4dst; + __be32 l4_4_bytes; + __u8 tos; + __u8 ip_ver; + __u8 proto; +}; + + +/** + * struct ethtool_rxfh_indir - command to get or set RX flow hash indirection + * @cmd: Specific command number - %ETHTOOL_GRXFHINDIR or %ETHTOOL_SRXFHINDIR + * @size: On entry, the array size of the user buffer. On return from + * %ETHTOOL_GRXFHINDIR, the array size of the hardware indirection table. + * @ring_index: RX ring/queue index for each hash value + */ +struct ethtool_rxfh_indir { + __u32 cmd; + __u32 size; + __u32 ring_index[0]; +}; + +#define ETHTOOL_FLASH_MAX_FILENAME 128 +enum ethtool_flash_op_type { + ETHTOOL_FLASH_ALL_REGIONS = 0, +}; + +/* for passing firmware flashing related parameters */ +struct ethtool_flash { + __u32 cmd; + __u32 region; + char data[ETHTOOL_FLASH_MAX_FILENAME]; +}; + +/* for returning and changing feature sets */ + +/** + * struct ethtool_get_features_block - block with state of 32 features + * @available: mask of changeable features + * @requested: mask of features requested to be enabled if possible + * @active: mask of currently enabled features + * @never_changed: mask of features not changeable for any device + */ +struct ethtool_get_features_block { + __u32 available; + __u32 requested; + __u32 active; + __u32 never_changed; +}; + +/** + * struct ethtool_gfeatures - command to get state of device's features + * @cmd: command number = %ETHTOOL_GFEATURES + * @size: in: number of elements in the features[] array; + * out: number of elements in features[] needed to hold all features + * @features: state of features + */ +struct ethtool_gfeatures { + __u32 cmd; + __u32 size; + struct ethtool_get_features_block features[0]; +}; + +/** + * struct ethtool_set_features_block - block with request for 32 features + * @valid: mask of features to be changed + * @requested: values of features to be changed + */ +struct ethtool_set_features_block { + __u32 valid; + __u32 requested; +}; + +/** + * struct ethtool_sfeatures - command to request change in device's features + * @cmd: command number = %ETHTOOL_SFEATURES + * @size: array size of the features[] array + * @features: feature change masks + */ +struct ethtool_sfeatures { + __u32 cmd; + __u32 size; + struct ethtool_set_features_block features[0]; +}; + +/* + * %ETHTOOL_SFEATURES changes features present in features[].valid to the + * values of corresponding bits in features[].requested. Bits in .requested + * not set in .valid or not changeable are ignored. + * + * Returns %EINVAL when .valid contains undefined or never-changable bits + * or size is not equal to required number of features words (32-bit blocks). + * Returns >= 0 if request was completed; bits set in the value mean: + * %ETHTOOL_F_UNSUPPORTED - there were bits set in .valid that are not + * changeable (not present in %ETHTOOL_GFEATURES' features[].available) + * those bits were ignored. + * %ETHTOOL_F_WISH - some or all changes requested were recorded but the + * resulting state of bits masked by .valid is not equal to .requested. + * Probably there are other device-specific constraints on some features + * in the set. When %ETHTOOL_F_UNSUPPORTED is set, .valid is considered + * here as though ignored bits were cleared. + * %ETHTOOL_F_COMPAT - some or all changes requested were made by calling + * compatibility functions. Requested offload state cannot be properly + * managed by kernel. + * + * Meaning of bits in the masks are obtained by %ETHTOOL_GSSET_INFO (number of + * bits in the arrays - always multiple of 32) and %ETHTOOL_GSTRINGS commands + * for ETH_SS_FEATURES string set. First entry in the table corresponds to least + * significant bit in features[0] fields. Empty strings mark undefined features. + */ +enum ethtool_sfeatures_retval_bits { + ETHTOOL_F_UNSUPPORTED__BIT, + ETHTOOL_F_WISH__BIT, + ETHTOOL_F_COMPAT__BIT, +}; + +#define ETHTOOL_F_UNSUPPORTED (1 << ETHTOOL_F_UNSUPPORTED__BIT) +#define ETHTOOL_F_WISH (1 << ETHTOOL_F_WISH__BIT) +#define ETHTOOL_F_COMPAT (1 << ETHTOOL_F_COMPAT__BIT) + +/* CMDs currently supported */ +#define ETHTOOL_GSET 0x00000001 /* Get settings. */ +#define ETHTOOL_SSET 0x00000002 /* Set settings. */ +#define ETHTOOL_GDRVINFO 0x00000003 /* Get driver info. */ +#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers. */ +#define ETHTOOL_GWOL 0x00000005 /* Get wake-on-lan options. */ +#define ETHTOOL_SWOL 0x00000006 /* Set wake-on-lan options. */ +#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */ +#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level. */ +#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation. */ +/* Get link status for host, i.e. whether the interface *and* the + * physical port (if there is one) are up (ethtool_value). */ +#define ETHTOOL_GLINK 0x0000000a +#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */ +#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data. */ +#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */ +#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */ +#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */ +#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters. */ +#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */ +#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */ +#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */ +#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */ +#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */ +#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */ +#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable + * (ethtool_value) */ +#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable + * (ethtool_value). */ +#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test. */ +#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */ +#define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */ +#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */ +#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */ +#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */ +#define ETHTOOL_GPERMADDR 0x00000020 /* Get permanent hardware address */ +#define ETHTOOL_GUFO 0x00000021 /* Get UFO enable (ethtool_value) */ +#define ETHTOOL_SUFO 0x00000022 /* Set UFO enable (ethtool_value) */ +#define ETHTOOL_GGSO 0x00000023 /* Get GSO enable (ethtool_value) */ +#define ETHTOOL_SGSO 0x00000024 /* Set GSO enable (ethtool_value) */ +#define ETHTOOL_GFLAGS 0x00000025 /* Get flags bitmap(ethtool_value) */ +#define ETHTOOL_SFLAGS 0x00000026 /* Set flags bitmap(ethtool_value) */ +#define ETHTOOL_GPFLAGS 0x00000027 /* Get driver-private flags bitmap */ +#define ETHTOOL_SPFLAGS 0x00000028 /* Set driver-private flags bitmap */ + +#define ETHTOOL_GRXFH 0x00000029 /* Get RX flow hash configuration */ +#define ETHTOOL_SRXFH 0x0000002a /* Set RX flow hash configuration */ +#define ETHTOOL_GGRO 0x0000002b /* Get GRO enable (ethtool_value) */ +#define ETHTOOL_SGRO 0x0000002c /* Set GRO enable (ethtool_value) */ +#define ETHTOOL_GRXRINGS 0x0000002d /* Get RX rings available for LB */ +#define ETHTOOL_GRXCLSRLCNT 0x0000002e /* Get RX class rule count */ +#define ETHTOOL_GRXCLSRULE 0x0000002f /* Get RX classification rule */ +#define ETHTOOL_GRXCLSRLALL 0x00000030 /* Get all RX classification rule */ +#define ETHTOOL_SRXCLSRLDEL 0x00000031 /* Delete RX classification rule */ +#define ETHTOOL_SRXCLSRLINS 0x00000032 /* Insert RX classification rule */ +#define ETHTOOL_FLASHDEV 0x00000033 /* Flash firmware to device */ +#define ETHTOOL_RESET 0x00000034 /* Reset hardware */ +#define ETHTOOL_SRXNTUPLE 0x00000035 /* Add an n-tuple filter to device */ +#define ETHTOOL_GRXNTUPLE 0x00000036 /* Get n-tuple filters from device */ +#define ETHTOOL_GSSET_INFO 0x00000037 /* Get string set info */ +#define ETHTOOL_GRXFHINDIR 0x00000038 /* Get RX flow hash indir'n table */ +#define ETHTOOL_SRXFHINDIR 0x00000039 /* Set RX flow hash indir'n table */ + +#define ETHTOOL_GFEATURES 0x0000003a /* Get device offload settings */ +#define ETHTOOL_SFEATURES 0x0000003b /* Change device offload settings */ + +/* compatibility with older code */ +#define SPARC_ETH_GSET ETHTOOL_GSET +#define SPARC_ETH_SSET ETHTOOL_SSET + +/* Indicates what features are supported by the interface. */ +#define SUPPORTED_10baseT_Half (1 << 0) +#define SUPPORTED_10baseT_Full (1 << 1) +#define SUPPORTED_100baseT_Half (1 << 2) +#define SUPPORTED_100baseT_Full (1 << 3) +#define SUPPORTED_1000baseT_Half (1 << 4) +#define SUPPORTED_1000baseT_Full (1 << 5) +#define SUPPORTED_Autoneg (1 << 6) +#define SUPPORTED_TP (1 << 7) +#define SUPPORTED_AUI (1 << 8) +#define SUPPORTED_MII (1 << 9) +#define SUPPORTED_FIBRE (1 << 10) +#define SUPPORTED_BNC (1 << 11) +#define SUPPORTED_10000baseT_Full (1 << 12) +#define SUPPORTED_Pause (1 << 13) +#define SUPPORTED_Asym_Pause (1 << 14) +#define SUPPORTED_2500baseX_Full (1 << 15) +#define SUPPORTED_Backplane (1 << 16) +#define SUPPORTED_1000baseKX_Full (1 << 17) +#define SUPPORTED_10000baseKX4_Full (1 << 18) +#define SUPPORTED_10000baseKR_Full (1 << 19) +#define SUPPORTED_10000baseR_FEC (1 << 20) + +/* Indicates what features are advertised by the interface. */ +#define ADVERTISED_10baseT_Half (1 << 0) +#define ADVERTISED_10baseT_Full (1 << 1) +#define ADVERTISED_100baseT_Half (1 << 2) +#define ADVERTISED_100baseT_Full (1 << 3) +#define ADVERTISED_1000baseT_Half (1 << 4) +#define ADVERTISED_1000baseT_Full (1 << 5) +#define ADVERTISED_Autoneg (1 << 6) +#define ADVERTISED_TP (1 << 7) +#define ADVERTISED_AUI (1 << 8) +#define ADVERTISED_MII (1 << 9) +#define ADVERTISED_FIBRE (1 << 10) +#define ADVERTISED_BNC (1 << 11) +#define ADVERTISED_10000baseT_Full (1 << 12) +#define ADVERTISED_Pause (1 << 13) +#define ADVERTISED_Asym_Pause (1 << 14) +#define ADVERTISED_2500baseX_Full (1 << 15) +#define ADVERTISED_Backplane (1 << 16) +#define ADVERTISED_1000baseKX_Full (1 << 17) +#define ADVERTISED_10000baseKX4_Full (1 << 18) +#define ADVERTISED_10000baseKR_Full (1 << 19) +#define ADVERTISED_10000baseR_FEC (1 << 20) + +/* The following are all involved in forcing a particular link + * mode for the device for setting things. When getting the + * devices settings, these indicate the current mode and whether + * it was foced up into this mode or autonegotiated. + */ + +/* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */ +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_10000 10000 + +/* Duplex, half or full. */ +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 + +/* Which connector port. */ +#define PORT_TP 0x00 +#define PORT_AUI 0x01 +#define PORT_MII 0x02 +#define PORT_FIBRE 0x03 +#define PORT_BNC 0x04 +#define PORT_DA 0x05 +#define PORT_NONE 0xef +#define PORT_OTHER 0xff + +/* Which transceiver to use. */ +#define XCVR_INTERNAL 0x00 +#define XCVR_EXTERNAL 0x01 +#define XCVR_DUMMY1 0x02 +#define XCVR_DUMMY2 0x03 +#define XCVR_DUMMY3 0x04 + +/* Enable or disable autonegotiation. If this is set to enable, + * the forced link modes above are completely ignored. + */ +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 + +/* Mode MDI or MDI-X */ +#define ETH_TP_MDI_INVALID 0x00 +#define ETH_TP_MDI 0x01 +#define ETH_TP_MDI_X 0x02 + +/* Wake-On-Lan options. */ +#define WAKE_PHY (1 << 0) +#define WAKE_UCAST (1 << 1) +#define WAKE_MCAST (1 << 2) +#define WAKE_BCAST (1 << 3) +#define WAKE_ARP (1 << 4) +#define WAKE_MAGIC (1 << 5) +#define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */ + +/* L2-L4 network traffic flow types */ +#define TCP_V4_FLOW 0x01 /* hash or spec (tcp_ip4_spec) */ +#define UDP_V4_FLOW 0x02 /* hash or spec (udp_ip4_spec) */ +#define SCTP_V4_FLOW 0x03 /* hash or spec (sctp_ip4_spec) */ +#define AH_ESP_V4_FLOW 0x04 /* hash only */ +#define TCP_V6_FLOW 0x05 /* hash only */ +#define UDP_V6_FLOW 0x06 /* hash only */ +#define SCTP_V6_FLOW 0x07 /* hash only */ +#define AH_ESP_V6_FLOW 0x08 /* hash only */ +#define AH_V4_FLOW 0x09 /* hash or spec (ah_ip4_spec) */ +#define ESP_V4_FLOW 0x0a /* hash or spec (esp_ip4_spec) */ +#define AH_V6_FLOW 0x0b /* hash only */ +#define ESP_V6_FLOW 0x0c /* hash only */ +#define IP_USER_FLOW 0x0d /* spec only (usr_ip4_spec) */ +#define IPV4_FLOW 0x10 /* hash only */ +#define IPV6_FLOW 0x11 /* hash only */ +#define ETHER_FLOW 0x12 /* spec only (ether_spec) */ + +/* L3-L4 network traffic flow hash options */ +#define RXH_L2DA (1 << 1) +#define RXH_VLAN (1 << 2) +#define RXH_L3_PROTO (1 << 3) +#define RXH_IP_SRC (1 << 4) +#define RXH_IP_DST (1 << 5) +#define RXH_L4_B_0_1 (1 << 6) /* src port in case of TCP/UDP/SCTP */ +#define RXH_L4_B_2_3 (1 << 7) /* dst port in case of TCP/UDP/SCTP */ +#define RXH_DISCARD (1 << 31) + +#define RX_CLS_FLOW_DISC 0xffffffffffffffffULL + +/* Reset flags */ +/* The reset() operation must clear the flags for the components which + * were actually reset. On successful return, the flags indicate the + * components which were not reset, either because they do not exist + * in the hardware or because they cannot be reset independently. The + * driver must never reset any components that were not requested. + */ +enum ethtool_reset_flags { + /* These flags represent components dedicated to the interface + * the command is addressed to. Shift any flag left by + * ETH_RESET_SHARED_SHIFT to reset a shared component of the + * same type. + */ + ETH_RESET_MGMT = 1 << 0, /* Management processor */ + ETH_RESET_IRQ = 1 << 1, /* Interrupt requester */ + ETH_RESET_DMA = 1 << 2, /* DMA engine */ + ETH_RESET_FILTER = 1 << 3, /* Filtering/flow direction */ + ETH_RESET_OFFLOAD = 1 << 4, /* Protocol offload */ + ETH_RESET_MAC = 1 << 5, /* Media access controller */ + ETH_RESET_PHY = 1 << 6, /* Transceiver/PHY */ + ETH_RESET_RAM = 1 << 7, /* RAM shared between + * multiple components */ + + ETH_RESET_DEDICATED = 0x0000ffff, /* All components dedicated to + * this interface */ + ETH_RESET_ALL = 0xffffffff, /* All components used by this + * interface, even if shared */ +}; +#define ETH_RESET_SHARED_SHIFT 16 + +#endif /* _LINUX_ETHTOOL_H */ diff --git a/include/linux/mdio.h b/include/linux/mdio.h new file mode 100644 index 000000000..022d77214 --- /dev/null +++ b/include/linux/mdio.h @@ -0,0 +1,278 @@ +/* + * linux/mdio.h: definitions for MDIO (clause 45) transceivers + * Copyright 2006-2009 Solarflare Communications Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation, incorporated herein by reference. + */ + +#ifndef __LINUX_MDIO_H__ +#define __LINUX_MDIO_H__ + +#include <linux/mii.h> + +/* MDIO Manageable Devices (MMDs). */ +#define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/ + * Physical Medium Dependent */ +#define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */ +#define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */ +#define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */ +#define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */ +#define MDIO_MMD_TC 6 /* Transmission Convergence */ +#define MDIO_MMD_AN 7 /* Auto-Negotiation */ +#define MDIO_MMD_C22EXT 29 /* Clause 22 extension */ +#define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ +#define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ + +/* Generic MDIO registers. */ +#define MDIO_CTRL1 MII_BMCR +#define MDIO_STAT1 MII_BMSR +#define MDIO_DEVID1 MII_PHYSID1 +#define MDIO_DEVID2 MII_PHYSID2 +#define MDIO_SPEED 4 /* Speed ability */ +#define MDIO_DEVS1 5 /* Devices in package */ +#define MDIO_DEVS2 6 +#define MDIO_CTRL2 7 /* 10G control 2 */ +#define MDIO_STAT2 8 /* 10G status 2 */ +#define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */ +#define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */ +#define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */ +#define MDIO_PKGID1 14 /* Package identifier */ +#define MDIO_PKGID2 15 +#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */ +#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */ +#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */ + +/* Media-dependent registers. */ +#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ +#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ +#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A. + * Lanes B-D are numbered 134-136. */ +#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */ +#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */ +#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */ +#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */ +#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */ +#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */ +#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */ + +/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ +#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ +#define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */ +#define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */ +#define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */ +#define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */ +#define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */ + +/* Control register 1. */ +/* Enable extended speed selection */ +#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100) +/* All speed selection bits */ +#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c) +#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX +#define MDIO_CTRL1_LPOWER BMCR_PDOWN +#define MDIO_CTRL1_RESET BMCR_RESET +#define MDIO_PMA_CTRL1_LOOPBACK 0x0001 +#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000 +#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100 +#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK +#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK +#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART +#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE +#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */ + +/* 10 Gb/s */ +#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) +/* 10PASS-TS/2BASE-TL */ +#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) + +/* Status register 1. */ +#define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */ +#define MDIO_STAT1_LSTATUS BMSR_LSTATUS +#define MDIO_STAT1_FAULT 0x0080 /* Fault */ +#define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */ +#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE +#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT +#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE +#define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */ +#define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */ + +/* Speed register. */ +#define MDIO_SPEED_10G 0x0001 /* 10G capable */ +#define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */ +#define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */ +#define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */ +#define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */ +#define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */ +#define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */ + +/* Device present registers. */ +#define MDIO_DEVS_PRESENT(devad) (1 << (devad)) +#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD) +#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS) +#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS) +#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS) +#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS) +#define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC) +#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN) +#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT) +#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1) +#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2) + + +/* Control register 2. */ +#define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */ +#define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */ +#define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */ +#define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */ +#define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */ +#define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */ +#define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */ +#define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */ +#define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */ +#define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */ +#define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */ +#define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */ +#define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */ +#define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */ +#define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */ +#define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */ +#define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */ +#define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */ +#define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */ +#define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */ +#define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */ +#define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */ + +/* Status register 2. */ +#define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */ +#define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */ +#define MDIO_STAT2_DEVPRST 0xc000 /* Device present */ +#define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */ +#define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */ +#define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */ +#define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */ +#define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */ +#define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */ +#define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */ +#define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */ +#define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */ +#define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */ +#define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */ +#define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ +#define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ +#define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */ +#define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */ +#define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */ +#define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ +#define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ + +/* Transmit disable register. */ +#define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */ +#define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */ +#define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */ +#define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */ +#define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */ + +/* Receive signal detect register. */ +#define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */ +#define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */ +#define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */ +#define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */ +#define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */ + +/* Extended abilities register. */ +#define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */ +#define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */ +#define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */ +#define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */ +#define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */ +#define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */ +#define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */ +#define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */ +#define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */ + +/* PHY XGXS lane state register. */ +#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001 +#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002 +#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004 +#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008 +#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000 + +/* PMA 10GBASE-T pair swap & polarity */ +#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */ +#define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */ +#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */ +#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */ +#define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */ +#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */ + +/* PMA 10GBASE-T TX power register. */ +#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */ + +/* PMA 10GBASE-T SNR registers. */ +/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */ +#define MDIO_PMA_10GBT_SNR_BIAS 0x8000 +#define MDIO_PMA_10GBT_SNR_MAX 127 + +/* PMA 10GBASE-R FEC ability register. */ +#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */ +#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */ + +/* PCS 10GBASE-R/-T status register 1. */ +#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */ + +/* PCS 10GBASE-R/-T status register 2. */ +#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff +#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 + +/* AN 10GBASE-T control register. */ +#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */ + +/* AN 10GBASE-T status register. */ +#define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */ +#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */ +#define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */ +#define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */ +#define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */ +#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */ +#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */ + +/* AN EEE Advertisement register. */ +#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */ +#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */ + +/* LASI RX_ALARM control/status registers. */ +#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */ +#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */ +#define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */ +#define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */ +#define MDIO_PMA_LASI_RX_WISLFLT 0x0200 /* WIS local fault */ + +/* LASI TX_ALARM control/status registers. */ +#define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */ +#define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */ +#define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */ +#define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 /* Laser output power fault */ +#define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 /* Laser temperature fault */ +#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 /* Laser bias current fault */ + +/* LASI control/status registers. */ +#define MDIO_PMA_LASI_LSALARM 0x0001 /* LS_ALARM enable/status */ +#define MDIO_PMA_LASI_TXALARM 0x0002 /* TX_ALARM enable/status */ +#define MDIO_PMA_LASI_RXALARM 0x0004 /* RX_ALARM enable/status */ + +/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */ + +#define MDIO_PHY_ID_C45 0x8000 +#define MDIO_PHY_ID_PRTAD 0x03e0 +#define MDIO_PHY_ID_DEVAD 0x001f +#define MDIO_PHY_ID_C45_MASK \ + (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD) + +#define MDIO_PRTAD_NONE (-1) +#define MDIO_DEVAD_NONE (-1) +#define MDIO_EMULATE_C22 4 + +#endif /* __LINUX_MDIO_H__ */ diff --git a/include/miiphy.h b/include/miiphy.h index 42dc12715..7e70cf81e 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -34,35 +34,52 @@ #ifndef _miiphy_h_ #define _miiphy_h_ +#include <common.h> #include <linux/mii.h> +#include <linux/list.h> #include <net.h> +#include <phy.h> -int miiphy_read (const char *devname, unsigned char addr, unsigned char reg, +struct legacy_mii_dev { + int (*read)(const char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); + int (*write)(const char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +}; + +int miiphy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value); -int miiphy_write (const char *devname, unsigned char addr, unsigned char reg, +int miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value); -int miiphy_info (const char *devname, unsigned char addr, unsigned int *oui, +int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui, unsigned char *model, unsigned char *rev); -int miiphy_reset (const char *devname, unsigned char addr); -int miiphy_speed (const char *devname, unsigned char addr); -int miiphy_duplex (const char *devname, unsigned char addr); -int miiphy_is_1000base_x (const char *devname, unsigned char addr); +int miiphy_reset(const char *devname, unsigned char addr); +int miiphy_speed(const char *devname, unsigned char addr); +int miiphy_duplex(const char *devname, unsigned char addr); +int miiphy_is_1000base_x(const char *devname, unsigned char addr); #ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -int miiphy_link (const char *devname, unsigned char addr); +int miiphy_link(const char *devname, unsigned char addr); #endif -void miiphy_init (void); +void miiphy_init(void); -void miiphy_register (const char *devname, - int (*read) (const char *devname, unsigned char addr, +void miiphy_register(const char *devname, + int (*read)(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value), - int (*write) (const char *devname, unsigned char addr, + int (*write)(const char *devname, unsigned char addr, unsigned char reg, unsigned short value)); -int miiphy_set_current_dev (const char *devname); -const char *miiphy_get_current_dev (void); +int miiphy_set_current_dev(const char *devname); +const char *miiphy_get_current_dev(void); +struct mii_dev *mdio_get_current_dev(void); +struct mii_dev *miiphy_get_dev_by_name(const char *devname); +struct phy_device *mdio_phydev_for_ethname(const char *devname); + +void miiphy_listdev(void); -void miiphy_listdev (void); +struct mii_dev *mdio_alloc(void); +int mdio_register(struct mii_dev *bus); +void mdio_list_devices(void); #ifdef CONFIG_BITBANGMII @@ -85,10 +102,10 @@ struct bb_miiphy_bus { extern struct bb_miiphy_bus bb_miiphy_buses[]; extern int bb_miiphy_buses_num; -void bb_miiphy_init (void); -int bb_miiphy_read (const char *devname, unsigned char addr, +void bb_miiphy_init(void); +int bb_miiphy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value); -int bb_miiphy_write (const char *devname, unsigned char addr, +int bb_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value); #endif diff --git a/include/mmc.h b/include/mmc.h index fcd0fd1de..f7f228698 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -14,7 +14,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -44,6 +44,7 @@ #define MMC_MODE_HS_52MHz 0x010 #define MMC_MODE_4BIT 0x100 #define MMC_MODE_8BIT 0x200 +#define MMC_MODE_SPI 0x400 #define SD_DATA_4BIT 0x00040000 @@ -75,6 +76,8 @@ #define MMC_CMD_WRITE_SINGLE_BLOCK 24 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 #define MMC_CMD_APP_CMD 55 +#define MMC_CMD_SPI_READ_OCR 58 +#define MMC_CMD_SPI_CRC_ON_OFF 59 #define SD_CMD_SEND_RELATIVE_ADDR 3 #define SD_CMD_SWITCH_FUNC 6 @@ -91,8 +94,14 @@ #define MMC_HS_TIMING 0x00000100 #define MMC_HS_52MHZ 0x2 -#define OCR_BUSY 0x80000000 -#define OCR_HCS 0x40000000 +#define OCR_BUSY 0x80000000 +#define OCR_HCS 0x40000000 +#define OCR_VOLTAGE_MASK 0x007FFF80 +#define OCR_ACCESS_MODE 0x60000000 + +#define MMC_STATUS_MASK (~0x0206BF7F) +#define MMC_STATUS_RDY_FOR_DATA (1 << 8) +#define MMC_STATUS_CURR_STATE (0xf << 9) #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ @@ -138,12 +147,12 @@ * EXT_CSD field definitions */ -#define EXT_CSD_CMD_SET_NORMAL (1<<0) -#define EXT_CSD_CMD_SET_SECURE (1<<1) -#define EXT_CSD_CMD_SET_CPSECURE (1<<2) +#define EXT_CSD_CMD_SET_NORMAL (1 << 0) +#define EXT_CSD_CMD_SET_SECURE (1 << 1) +#define EXT_CSD_CMD_SET_CPSECURE (1 << 2) -#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ -#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ @@ -153,21 +162,21 @@ #define R1_APP_CMD (1 << 5) #define MMC_RSP_PRESENT (1 << 0) -#define MMC_RSP_136 (1 << 1) /* 136 bit response */ -#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ -#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ -#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ -#define MMC_RSP_NONE (0) -#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ MMC_RSP_BUSY) -#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) -#define MMC_RSP_R3 (MMC_RSP_PRESENT) -#define MMC_RSP_R4 (MMC_RSP_PRESENT) -#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) struct mmc_cid { @@ -274,9 +283,7 @@ struct mmc { struct mmc_cmd *cmd, struct mmc_data *data); void (*set_ios)(struct mmc *mmc); int (*init)(struct mmc *mmc); -#ifdef CONFIG_MMC_MBLOCK uint b_max; -#endif }; int mmc_register(struct mmc *mmc); @@ -291,6 +298,8 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc); #ifdef CONFIG_GENERIC_MMC int atmel_mci_init(void *regs); +#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI) +struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); #else int mmc_legacy_init(int verbose); #endif diff --git a/include/pci_ids.h b/include/pci_ids.h index cb8398d2c..02a6c6e07 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1853,6 +1853,7 @@ #define PCI_DEVICE_ID_INTEL_82573E 0x108B #define PCI_DEVICE_ID_INTEL_82573E_IAMT 0x108C #define PCI_DEVICE_ID_INTEL_82573L 0x109A +#define PCI_DEVICE_ID_INTEL_82574L 0x10D3 #define PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3 0x10B5 #define PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT 0x1096 #define PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT 0x1098 diff --git a/include/phy.h b/include/phy.h new file mode 100644 index 000000000..d5817bf19 --- /dev/null +++ b/include/phy.h @@ -0,0 +1,229 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Andy Fleming <afleming@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h + */ + +#ifndef _PHY_H +#define _PHY_H + +#include <linux/list.h> +#include <linux/mii.h> +#include <linux/ethtool.h> +#include <linux/mdio.h> + +#define PHY_MAX_ADDR 32 + +#define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ + SUPPORTED_10baseT_Full | \ + SUPPORTED_100baseT_Half | \ + SUPPORTED_100baseT_Full | \ + SUPPORTED_Autoneg | \ + SUPPORTED_TP | \ + SUPPORTED_MII) + +#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ + SUPPORTED_1000baseT_Half | \ + SUPPORTED_1000baseT_Full) + +#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ + SUPPORTED_10000baseT_Full) + +#define PHY_ANEG_TIMEOUT 4000 + + +typedef enum { + PHY_INTERFACE_MODE_MII, + PHY_INTERFACE_MODE_GMII, + PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_TBI, + PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_RGMII, + PHY_INTERFACE_MODE_RGMII_ID, + PHY_INTERFACE_MODE_RGMII_RXID, + PHY_INTERFACE_MODE_RGMII_TXID, + PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_NONE /* Must be last */ +} phy_interface_t; + +static const char *phy_interface_strings[] = { + [PHY_INTERFACE_MODE_MII] = "mii", + [PHY_INTERFACE_MODE_GMII] = "gmii", + [PHY_INTERFACE_MODE_SGMII] = "sgmii", + [PHY_INTERFACE_MODE_TBI] = "tbi", + [PHY_INTERFACE_MODE_RMII] = "rmii", + [PHY_INTERFACE_MODE_RGMII] = "rgmii", + [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", + [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", + [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", + [PHY_INTERFACE_MODE_RTBI] = "rtbi", + [PHY_INTERFACE_MODE_XGMII] = "xgmii", + [PHY_INTERFACE_MODE_NONE] = "", +}; + +static inline const char *phy_string_for_interface(phy_interface_t i) +{ + /* Default to unknown */ + if (i > PHY_INTERFACE_MODE_NONE) + i = PHY_INTERFACE_MODE_NONE; + + return phy_interface_strings[i]; +} + + +struct phy_device; + +#define MDIO_NAME_LEN 32 + +struct mii_dev { + struct list_head link; + char name[MDIO_NAME_LEN]; + void *priv; + int (*read)(struct mii_dev *bus, int addr, int devad, int reg); + int (*write)(struct mii_dev *bus, int addr, int devad, int reg, + u16 val); + int (*reset)(struct mii_dev *bus); + struct phy_device *phymap[PHY_MAX_ADDR]; + u32 phy_mask; +}; + +/* struct phy_driver: a structure which defines PHY behavior + * + * uid will contain a number which represents the PHY. During + * startup, the driver will poll the PHY to find out what its + * UID--as defined by registers 2 and 3--is. The 32-bit result + * gotten from the PHY will be masked to + * discard any bits which may change based on revision numbers + * unimportant to functionality + * + */ +struct phy_driver { + char *name; + unsigned int uid; + unsigned int mask; + unsigned int mmds; + + u32 features; + + /* Called to do any driver startup necessities */ + /* Will be called during phy_connect */ + int (*probe)(struct phy_device *phydev); + + /* Called to configure the PHY, and modify the controller + * based on the results. Should be called after phy_connect */ + int (*config)(struct phy_device *phydev); + + /* Called when starting up the controller */ + int (*startup)(struct phy_device *phydev); + + /* Called when bringing down the controller */ + int (*shutdown)(struct phy_device *phydev); + + struct list_head list; +}; + +struct phy_device { + /* Information about the PHY type */ + /* And management functions */ + struct mii_dev *bus; + struct phy_driver *drv; + void *priv; + + struct eth_device *dev; + + /* forced speed & duplex (no autoneg) + * partner speed & duplex & pause (autoneg) + */ + int speed; + int duplex; + + /* The most recently read link state */ + int link; + int port; + phy_interface_t interface; + + u32 advertising; + u32 supported; + u32 mmds; + + int autoneg; + int addr; + int pause; + int asym_pause; + u32 phy_id; + u32 flags; +}; + +static inline int phy_read(struct phy_device *phydev, int devad, int regnum) +{ + struct mii_dev *bus = phydev->bus; + + return bus->read(bus, phydev->addr, devad, regnum); +} + +static inline int phy_write(struct phy_device *phydev, int devad, int regnum, + u16 val) +{ + struct mii_dev *bus = phydev->bus; + + return bus->write(bus, phydev->addr, devad, regnum, val); +} + +#ifdef CONFIG_PHYLIB_10G +extern struct phy_driver gen10g_driver; + +/* For now, XGMII is the only 10G interface */ +static inline int is_10g_interface(phy_interface_t interface) +{ + return interface == PHY_INTERFACE_MODE_XGMII; +} + +#endif + +int phy_init(void); +int phy_reset(struct phy_device *phydev); +struct phy_device *phy_connect(struct mii_dev *bus, int addr, + struct eth_device *dev, + phy_interface_t interface); +int phy_startup(struct phy_device *phydev); +int phy_config(struct phy_device *phydev); +int phy_shutdown(struct phy_device *phydev); +int phy_register(struct phy_driver *drv); +int genphy_config_aneg(struct phy_device *phydev); +int genphy_update_link(struct phy_device *phydev); +int genphy_config(struct phy_device *phydev); +int genphy_startup(struct phy_device *phydev); +int genphy_shutdown(struct phy_device *phydev); +int gen10g_config(struct phy_device *phydev); +int gen10g_startup(struct phy_device *phydev); +int gen10g_shutdown(struct phy_device *phydev); +int gen10g_discover_mmds(struct phy_device *phydev); + +int phy_atheros_init(void); +int phy_broadcom_init(void); +int phy_davicom_init(void); +int phy_lxt_init(void); +int phy_marvell_init(void); +int phy_micrel_init(void); +int phy_natsemi_init(void); +int phy_realtek_init(void); +int phy_teranetics_init(void); +int phy_vitesse_init(void); +#endif diff --git a/include/search.h b/include/search.h index a7c129377..c827d4dbe 100644 --- a/include/search.h +++ b/include/search.h @@ -80,6 +80,12 @@ extern int hsearch_r(ENTRY __item, ACTION __action, ENTRY ** __retval, */ extern int hmatch_r(const char *__match, int __last_idx, ENTRY ** __retval, struct hsearch_data *__htab); +/* + * Search for an entry whose key or data contains `MATCH'. Otherwise, + * Same semantics as hsearch_r(). + */ +extern int hstrstr_r(const char *__match, int __last_idx, ENTRY ** __retval, + struct hsearch_data *__htab); /* Search and delete entry matching ITEM.key in internal hash table. */ extern int hdelete_r(const char *__key, struct hsearch_data *__htab); diff --git a/include/spi.h b/include/spi.h index 320e50e52..60e85db9a 100644 --- a/include/spi.h +++ b/include/spi.h @@ -26,13 +26,6 @@ /* Controller-specific definitions: */ -/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ -#ifdef CONFIG_MPC8XXX_SPI -# ifndef CONFIG_HARD_SPI -# define CONFIG_HARD_SPI -# endif -#endif - /* SPI mode flags */ #define SPI_CPHA 0x01 /* clock phase */ #define SPI_CPOL 0x02 /* clock polarity */ @@ -176,6 +169,14 @@ void spi_cs_activate(struct spi_slave *slave); void spi_cs_deactivate(struct spi_slave *slave); /*----------------------------------------------------------------------- + * Set transfer speed. + * This sets a new speed to be applied for next spi_xfer(). + * slave: The SPI slave + * hz: The transfer speed + */ +void spi_set_speed(struct spi_slave *slave, uint hz); + +/*----------------------------------------------------------------------- * Write 8 bits, then read 8 bits. * slave: The SPI slave we're communicating with * byte: Byte to be written diff --git a/include/spi_flash.h b/include/spi_flash.h index 1f8ba2987..a384071fb 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -26,11 +26,6 @@ #include <spi.h> #include <linux/types.h> -struct spi_flash_region { - unsigned int count; - unsigned int size; -}; - struct spi_flash { struct spi_slave *spi; @@ -38,6 +33,8 @@ struct spi_flash { u32 size; + u32 sector_size; + int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf); int (*write)(struct spi_flash *flash, u32 offset, diff --git a/include/tsec.h b/include/tsec.h index d56ec2cd0..f0f3d4d59 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -7,7 +7,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc. + * Copyright 2004, 2007, 2009, 2011 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * maintained by Xianghua Xiao (x.xiao@motorola.com) * author Andy Fleming @@ -19,30 +19,36 @@ #include <net.h> #include <config.h> +#include <phy.h> +#include <asm/fsl_enet.h> #define TSEC_SIZE 0x01000 #define TSEC_MDIO_OFFSET 0x01000 +#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520) + +#define DEFAULT_MII_NAME "FSL_MDIO" + #define STD_TSEC_INFO(num) \ { \ .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ - .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \ - .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \ + .miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \ + (num - 1) * TSEC_MDIO_OFFSET), \ .devname = CONFIG_TSEC##num##_NAME, \ .phyaddr = TSEC##num##_PHY_ADDR, \ - .flags = TSEC##num##_FLAGS \ + .flags = TSEC##num##_FLAGS, \ + .mii_devname = DEFAULT_MII_NAME \ } #define SET_STD_TSEC_INFO(x, num) \ { \ x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ - x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \ - x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \ + x.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \ + (num - 1) * TSEC_MDIO_OFFSET); \ x.devname = CONFIG_TSEC##num##_NAME; \ x.phyaddr = TSEC##num##_PHY_ADDR; \ x.flags = TSEC##num##_FLAGS;\ + x.mii_devname = DEFAULT_MII_NAME;\ } #define MAC_ADDR_LEN 6 @@ -51,8 +57,6 @@ #define TSEC_TIMEOUT 1000 #define TOUT_LOOP 1000000 -#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ - /* TBI register addresses */ #define TBI_CR 0x00 #define TBI_SR 0x01 @@ -96,204 +100,14 @@ #define ECNTRL_INIT_SETTINGS 0x00001000 #define ECNTRL_TBI_MODE 0x00000020 +#define ECNTRL_REDUCED_MODE 0x00000010 #define ECNTRL_R100 0x00000008 +#define ECNTRL_REDUCED_MII_MODE 0x00000004 #define ECNTRL_SGMII_MODE 0x00000002 -#define miim_end -2 -#define miim_read -1 - #ifndef CONFIG_SYS_TBIPA_VALUE #define CONFIG_SYS_TBIPA_VALUE 0x1f #endif -#define MIIMCFG_INIT_VALUE 0x00000003 -#define MIIMCFG_RESET 0x80000000 - -#define MIIMIND_BUSY 0x00000001 -#define MIIMIND_NOTVALID 0x00000004 - -#define MIIM_CONTROL 0x00 -#define MIIM_CONTROL_RESET 0x00009140 -#define MIIM_CONTROL_INIT 0x00001140 -#define MIIM_CONTROL_RESTART 0x00001340 -#define MIIM_ANEN 0x00001000 - -#define MIIM_CR 0x00 -#define MIIM_CR_RST 0x00008000 -#define MIIM_CR_INIT 0x00001000 - -#define MIIM_STATUS 0x1 -#define MIIM_STATUS_AN_DONE 0x00000020 -#define MIIM_STATUS_LINK 0x0004 - -#define MIIM_PHYIR1 0x2 -#define MIIM_PHYIR2 0x3 - -#define MIIM_ANAR 0x4 -#define MIIM_ANAR_INIT 0x1e1 - -#define MIIM_TBI_ANLPBPA 0x5 -#define MIIM_TBI_ANLPBPA_HALF 0x00000040 -#define MIIM_TBI_ANLPBPA_FULL 0x00000020 - -#define MIIM_TBI_ANEX 0x6 -#define MIIM_TBI_ANEX_NP 0x00000004 -#define MIIM_TBI_ANEX_PRX 0x00000002 - -#define MIIM_GBIT_CONTROL 0x9 -#define MIIM_GBIT_CONTROL_INIT 0xe00 - -#define MIIM_EXT_PAGE_ACCESS 0x1f - -/* Broadcom BCM54xx -- taken from linux sungem_phy */ -#define MIIM_BCM54xx_AUXCNTL 0x18 -#define MIIM_BCM54xx_AUXCNTL_ENCODE(val) ((val & 0x7) << 12)|(val & 0x7) -#define MIIM_BCM54xx_AUXSTATUS 0x19 -#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 -#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 - -#define MIIM_BCM54XX_SHD 0x1c /* 0x1c shadow registers */ -#define MIIM_BCM54XX_SHD_WRITE 0x8000 -#define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) -#define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) -#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \ - (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \ - MIIM_BCM54XX_SHD_DATA(data)) - -#define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ -#define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ -#define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ -#define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ - -/* Cicada Auxiliary Control/Status Register */ -#define MIIM_CIS8201_AUX_CONSTAT 0x1c -#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 -#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020 -#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018 -#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010 -#define MIIM_CIS8201_AUXCONSTAT_100 0x0008 - -/* Cicada Extended Control Register 1 */ -#define MIIM_CIS8201_EXT_CON1 0x17 -#define MIIM_CIS8201_EXTCON1_INIT 0x0000 - -/* Cicada 8204 Extended PHY Control Register 1 */ -#define MIIM_CIS8204_EPHY_CON 0x17 -#define MIIM_CIS8204_EPHYCON_INIT 0x0006 -#define MIIM_CIS8204_EPHYCON_RGMII 0x1100 - -/* Cicada 8204 Serial LED Control Register */ -#define MIIM_CIS8204_SLED_CON 0x1b -#define MIIM_CIS8204_SLEDCON_INIT 0x1115 - -#define MIIM_GBIT_CON 0x09 -#define MIIM_GBIT_CON_ADVERT 0x0e00 - -/* Entry for Vitesse VSC8244 regs starts here */ -/* Vitesse VSC8244 Auxiliary Control/Status Register */ -#define MIIM_VSC8244_AUX_CONSTAT 0x1c -#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 -#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 -#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 -#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 -#define MIIM_VSC8244_AUXCONSTAT_100 0x0008 -#define MIIM_CONTROL_INIT_LOOPBACK 0x4000 - -/* Vitesse VSC8244 Extended PHY Control Register 1 */ -#define MIIM_VSC8244_EPHY_CON 0x17 -#define MIIM_VSC8244_EPHYCON_INIT 0x0006 - -/* Vitesse VSC8244 Serial LED Control Register */ -#define MIIM_VSC8244_LED_CON 0x1b -#define MIIM_VSC8244_LEDCON_INIT 0xF011 - -/* Entry for Vitesse VSC8601 regs starts here (Not complete) */ -/* Vitesse VSC8601 Extended PHY Control Register 1 */ -#define MIIM_VSC8601_EPHY_CON 0x17 -#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120 -#define MIIM_VSC8601_SKEW_CTRL 0x1c - -/* 88E1011 PHY Status Register */ -#define MIIM_88E1011_PHY_STATUS 0x11 -#define MIIM_88E1011_PHYSTAT_SPEED 0xc000 -#define MIIM_88E1011_PHYSTAT_GBIT 0x8000 -#define MIIM_88E1011_PHYSTAT_100 0x4000 -#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 -#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 -#define MIIM_88E1011_PHYSTAT_LINK 0x0400 - -#define MIIM_88E1011_PHY_SCR 0x10 -#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 - -/* 88E1111 PHY LED Control Register */ -#define MIIM_88E1111_PHY_LED_CONTROL 24 -#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 -#define MIIM_88E1111_PHY_LED_COMBINE 0x411C - -/* 88E1121 PHY LED Control Register */ -#define MIIM_88E1121_PHY_LED_CTRL 16 -#define MIIM_88E1121_PHY_LED_PAGE 3 -#define MIIM_88E1121_PHY_LED_DEF 0x0030 - -/* 88E1121 PHY IRQ Enable/Status Register */ -#define MIIM_88E1121_PHY_IRQ_EN 18 -#define MIIM_88E1121_PHY_IRQ_STATUS 19 - -#define MIIM_88E1121_PHY_PAGE 22 - -/* 88E1145 Extended PHY Specific Control Register */ -#define MIIM_88E1145_PHY_EXT_CR 20 -#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 -#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 - -#define MIIM_88E1145_PHY_PAGE 29 -#define MIIM_88E1145_PHY_CAL_OV 30 - -/* RTL8211B PHY Status Register */ -#define MIIM_RTL8211B_PHY_STATUS 0x11 -#define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000 -#define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000 -#define MIIM_RTL8211B_PHYSTAT_100 0x4000 -#define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000 -#define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800 -#define MIIM_RTL8211B_PHYSTAT_LINK 0x0400 - -/* DM9161 Control register values */ -#define MIIM_DM9161_CR_STOP 0x0400 -#define MIIM_DM9161_CR_RSTAN 0x1200 - -#define MIIM_DM9161_SCR 0x10 -#define MIIM_DM9161_SCR_INIT 0x0610 - -/* DM9161 Specified Configuration and Status Register */ -#define MIIM_DM9161_SCSR 0x11 -#define MIIM_DM9161_SCSR_100F 0x8000 -#define MIIM_DM9161_SCSR_100H 0x4000 -#define MIIM_DM9161_SCSR_10F 0x2000 -#define MIIM_DM9161_SCSR_10H 0x1000 - -/* DM9161 10BT Configuration/Status */ -#define MIIM_DM9161_10BTCSR 0x12 -#define MIIM_DM9161_10BTCSR_INIT 0x7800 - -/* LXT971 Status 2 registers */ -#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ -#define MIIM_LXT971_SR2_SPEED_MASK 0x4200 -#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ -#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ -#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ -#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ - -/* DP83865 Control register values */ -#define MIIM_DP83865_CR_INIT 0x9200 - -/* DP83865 Link and Auto-Neg Status Register */ -#define MIIM_DP83865_LANR 0x11 -#define MIIM_DP83865_SPD_MASK 0x0018 -#define MIIM_DP83865_SPD_1000 0x0010 -#define MIIM_DP83865_SPD_100 0x0008 -#define MIIM_DP83865_DPX_FULL 0x0002 - -#define MIIM_READ_COMMAND 0x00000001 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN @@ -467,22 +281,6 @@ typedef struct tsec_hash_regs uint res2[24]; } tsec_hash_t; -typedef struct tsec_mdio { - uint res1[4]; - uint ieventm; - uint imaskm; - uint res2; - uint emapm; - uint res3[320]; - uint miimcfg; /* MII Management: Configuration */ - uint miimcom; /* MII Management: Command */ - uint miimadd; /* MII Management: Address */ - uint miimcon; /* MII Management: Control */ - uint miimstat; /* MII Management: Status */ - uint miimind; /* MII Management: Indicators */ - uint res4[690]; -} tsec_mdio_t; - typedef struct tsec { /* General Control and Status Registers (0x2_n000) */ @@ -578,79 +376,29 @@ typedef struct tsec uint resc00[256]; } tsec_t; -#define TSEC_GIGABIT (1) +#define TSEC_GIGABIT (1 << 0) -/* This flag currently only has - * meaning if we're using the eTSEC */ +/* These flags currently only have meaning if we're using the eTSEC */ #define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */ #define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */ -#define TSEC_FIBER (1 << 3) /* PHY uses fiber, eg 1000 Base-X */ struct tsec_private { - volatile tsec_t *regs; - volatile tsec_mdio_t *phyregs; - volatile tsec_mdio_t *phyregs_sgmii; - struct phy_info *phyinfo; + tsec_t *regs; + struct tsec_mii_mng *phyregs_sgmii; + struct phy_device *phydev; + phy_interface_t interface; + struct mii_dev *bus; uint phyaddr; + char mii_devname[16]; u32 flags; - uint link; - uint duplexity; - uint speed; -}; - - -/* - * struct phy_cmd: A command for reading or writing a PHY register - * - * mii_reg: The register to read or write - * - * mii_data: For writes, the value to put in the register. - * A value of -1 indicates this is a read. - * - * funct: A function pointer which is invoked for each command. - * For reads, this function will be passed the value read - * from the PHY, and process it. - * For writes, the result of this function will be written - * to the PHY register - */ -struct phy_cmd { - uint mii_reg; - uint mii_data; - uint (*funct) (uint mii_reg, struct tsec_private * priv); -}; - -/* struct phy_info: a structure which defines attributes for a PHY - * - * id will contain a number which represents the PHY. During - * startup, the driver will poll the PHY to find out what its - * UID--as defined by registers 2 and 3--is. The 32-bit result - * gotten from the PHY will be shifted right by "shift" bits to - * discard any bits which may change based on revision numbers - * unimportant to functionality - * - * The struct phy_cmd entries represent pointers to an arrays of - * commands which tell the driver what to do to the PHY. - */ -struct phy_info { - uint id; - char *name; - uint shift; - /* Called to configure the PHY, and modify the controller - * based on the results */ - struct phy_cmd *config; - - /* Called when starting up the controller */ - struct phy_cmd *startup; - - /* Called when bringing down the controller */ - struct phy_cmd *shutdown; }; struct tsec_info_struct { tsec_t *regs; - tsec_mdio_t *miiregs; - tsec_mdio_t *miiregs_sgmii; + struct tsec_mii_mng *miiregs_sgmii; char *devname; + char *mii_devname; + phy_interface_t interface; unsigned int phyaddr; u32 flags; }; |