diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/405gp_enet.h | 57 | ||||
| -rw-r--r-- | include/configs/PPChameleonEVB.h | 4 | ||||
| -rw-r--r-- | include/ppc405.h | 8 |
3 files changed, 65 insertions, 4 deletions
diff --git a/include/405gp_enet.h b/include/405gp_enet.h index 224452106..88ac4add9 100644 --- a/include/405gp_enet.h +++ b/include/405gp_enet.h @@ -35,7 +35,8 @@ +----------------------------------------------------------------------------*/ #ifndef _enetemac_h_ #define _enetemac_h_ - +#include <net.h> +#include <405_mal.h> /*-----------------------------------------------------------------------------+ | General enternet defines. 802 frames are not supported. @@ -235,6 +236,60 @@ struct arp_entry { /* all the errors we care about */ #define EMAC_RX_ERRORS 0x03FF +#define NUM_RX_BUFF PKTBUFSRX +#define NUM_TX_BUFF 1 + +#define MAX_ERR_LOG 10 +typedef struct emac_stats_st{ /* Statistic Block */ + int data_len_err; + int rx_frames; + int rx; + int rx_prot_err; + int int_err; + int pkts_tx; + int pkts_rx; + int pkts_handled; + short tx_err_log[MAX_ERR_LOG]; + short rx_err_log[MAX_ERR_LOG]; +} EMAC_STATS_ST, *EMAC_STATS_PST; + +/* Structure containing variables used by the shared code (440gx_enet.c) */ +typedef struct emac_440gx_hw_st { + uint32_t hw_addr; /* EMAC offset */ + uint32_t tah_addr; /* TAH offset */ + uint32_t phy_id; + uint32_t phy_addr; + uint32_t original_fc; + uint32_t txcw; + uint32_t autoneg_failed; + uint32_t emac_ier; + volatile mal_desc_t *tx; + volatile mal_desc_t *rx; + bd_t *bis; /* for eth_init upon mal error */ + mal_desc_t *alloc_tx_buf; + mal_desc_t *alloc_rx_buf; + char *txbuf_ptr; + uint16_t devnum; + int get_link_status; + int tbi_compatibility_en; + int tbi_compatibility_on; + int fc_send_xon; + int report_tx_early; + int first_init; + int tx_err_index; + int rx_err_index; + int rx_slot; /* MAL Receive Slot */ + int rx_i_index; /* Receive Interrupt Queue Index */ + int rx_u_index; /* Receive User Queue Index */ + int tx_slot; /* MAL Transmit Slot */ + int tx_i_index; /* Transmit Interrupt Queue Index */ + int tx_u_index; /* Transmit User Queue Index */ + int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */ + int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */ + int is_receiving; /* sync with eth interrupt */ + int print_speed; /* print speed message upon start */ + EMAC_STATS_ST stats; +} EMAC_405_HW_ST, *EMAC_405_HW_PST; /*-----------------------------------------------------------------------------+ | Function prototypes for device table. diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index c9e52e2a4..0c9b6dd7e 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -77,10 +77,12 @@ #undef CONFIG_EXT_PHY +#define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ #ifndef CONFIG_EXT_PHY -#define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_PHY_ADDR 0 /* EMAC0 PHY address */ +#define CONFIG_PHY1_ADDR 1 /* EMAC1 PHY address */ #else #define CONFIG_PHY_ADDR 2 /* PHY address */ #endif diff --git a/include/ppc405.h b/include/ppc405.h index 29e6ffd0d..64317b0e4 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -132,9 +132,10 @@ #define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */ #define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */ #define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */ -#define UIC_ENET 0x00010000 /* Ethernet */ +#define UIC_ENET 0x00010000 /* Ethernet0 */ +#define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */ +#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */ #define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */ -#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error */ #define UIC_PCI_PM 0x00002000 /* PCI Power Management */ #define UIC_EXT0 0x00000040 /* External interrupt 0 */ #define UIC_EXT1 0x00000020 /* External interrupt 1 */ @@ -582,8 +583,11 @@ #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ /*----------------------------------------------------------------------------- | IIC Register Offsets |