diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/MPC8260ADS.h | 9 | ||||
| -rw-r--r-- | include/configs/MPC8266ADS.h | 411 | ||||
| -rw-r--r-- | include/configs/TOP860.h | 439 | ||||
| -rw-r--r-- | include/configs/W7OLMC.h | 2 | ||||
| -rw-r--r-- | include/configs/W7OLMG.h | 2 | ||||
| -rw-r--r-- | include/configs/lubbock.h | 18 | ||||
| -rw-r--r-- | include/spd.h | 78 | ||||
| -rw-r--r-- | include/spd_sdram.h | 6 |
8 files changed, 955 insertions, 10 deletions
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index b4d8406aa..7968c8b2b 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -99,8 +99,17 @@ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) +#define CONFIG_SPD_ADDR 0x50 +#endif + +#ifndef CONFIG_SDRAM_PBI +#define CONFIG_SDRAM_PBI 1 /* By default, use page-based interleaving */ +#endif +#ifndef CONFIG_8260_CLKIN #define CONFIG_8260_CLKIN 66666666 /* in Hz */ +#endif #define CONFIG_BAUDRATE 115200 #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h new file mode 100644 index 000000000..e72ce0a78 --- /dev/null +++ b/include/configs/MPC8266ADS.h @@ -0,0 +1,411 @@ +/* + * (C) Copyright 2001 + * Stuart Hughes <stuarth@lineo.com> + * This file is based on similar values for other boards found in other + * U-Boot config files, and some that I found in the mpc8260ads manual. + * + * Note: my board is a PILOT rev. + * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Config header file for a MPC8260ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */ + +#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ + +/* allow serial and ethaddr to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ + +#if (CONFIG_ETHER_INDEX == 2) + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers (see 28-13) + * - Half duplex + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR 0 + +#endif /* CONFIG_ETHER_INDEX */ + +/* other options */ +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_EEPROM_ADDR_LEN 1 + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 + + +#define CONFIG_8260_CLKIN 66666666 /* in Hz */ +#define CONFIG_BAUDRATE 115200 + + +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_VFD | \ + CFG_CMD_USB ) ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/ram rw" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#endif + +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + /* for versions < 2.4.5-pre5 */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_FLASH_BASE 0xff800000 +#define FLASH_BASE 0xff800000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ +#define CFG_FLASH_SIZE 8 +#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ + +#undef CFG_FLASH_CHECKSUM + +/* this is stuff came out of the Motorola docs */ +/* Only change this if you also change the Hardware configuration Word */ +#define CFG_DEFAULT_IMMR 0x0F010000 + +/* +#define CFG_IMMR 0x04700000 +#define CFG_BCSR 0x04500000 +*/ + +/* Set IMMR to 0xF0000000 or above to boot Linux */ +#define CFG_IMMR 0xF0000000 +#define CFG_BCSR 0x04500000 + +/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes + */ +/*#define CONFIG_VERY_BIG_RAM 1*/ + +/* What should be the base address of SDRAM DIMM and how big is + * it (in Mbytes)? This will normally auto-configure via the SPD. +*/ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 + +#define SDRAM_SPD_ADDR 0x50 + + +/*----------------------------------------------------------------------- + * BR2,BR3 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR2,OR3 - Option Register + * Ref: Section 10.3.2 on page 10-16 + *----------------------------------------------------------------------- + */ + +/* Bank 2,3 - SDRAM DIMM + */ + +/* The BR2 is configured as follows: + * + * - Base address of 0x00000000 + * - 64 bit port size (60x bus only) + * - Data errors checking is disabled + * - Read and write access + * - SDRAM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_BR3_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +/* With a 64 MB DIMM, the OR2 is configured as follows: + * + * - 64 MB + * - 4 internal banks per device + * - Row start address bit is A8 with PSDMR[PBI] = 0 + * - 12 row address lines + * - Back-to-back page mode + * - Internal bank interleaving within save device enabled + */ +#if (CFG_SDRAM_SIZE == 64) +#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A8 |\ + ORxS_NUMR_12) +#elif (CFG_SDRAM_SIZE == 16) +#define CFG_OR2_PRELIM (0xFF000CA0) +#else +#error "INVALID SDRAM CONFIGURATION" +#endif + +/*----------------------------------------------------------------------- + * PSDMR - 60x Bus SDRAM Mode Register + * Ref: Section 10.3.3 on page 10-21 + *----------------------------------------------------------------------- + */ + +#if (CFG_SDRAM_SIZE == 64) +/* With a 64 MB DIMM, the PSDMR is configured as follows: + * + * - Bank Based Interleaving, + * - Refresh Enable, + * - Address Multiplexing where A5 is output on A14 pin + * (A6 on A15, and so on), + * - use address pins A14-A16 as bank select, + * - A9 is output on SDA10 during an ACTIVATE command, + * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, + * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command + * is 3 clocks, + * - earliest timing for READ/WRITE command after ACTIVATE command is + * 2 clocks, + * - earliest timing for PRECHARGE after last data was read is 1 clock, + * - earliest timing for PRECHARGE after last data was written is 1 clock, + * - CAS Latency is 2. + */ +#define CFG_PSDMR (PSDMR_RFEN |\ + PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) +#elif (CFG_SDRAM_SIZE == 16) +/* With a 16 MB DIMM, the PSDMR is configured as follows: + * + * configuration parameters found in Motorola documentation + */ +#define CFG_PSDMR (0x016EB452) +#else +#error "INVALID SDRAM CONFIGURATION" +#endif + + +#define RS232EN_1 0x02000002 +#define RS232EN_2 0x01000001 +#define FETHIEN 0x08000008 +#define FETH_RST 0x04000004 + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* 0x0EA28205 */ +/*#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ + ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\ + ( HRCW_BMS | HRCW_APPC10 ) |\ + ( HRCW_MODCK_H0101 ) \ + ) +*/ + +/* This value should actually be situated in the first 256 bytes of the FLASH + which on the standard MPC8266ADS board is at address 0xFF800000 + The linker script places it at 0xFFF00000 instead. + + It still works, however, as long as the ADS board jumper JP3 is set to + position 2-3 so the board is using the BCSR as Hardware Configuration Word + + If you want to use the one defined here instead, ust copy the first 256 bytes from + 0xfff00000 to 0xff800000 (for 8MB flash) + + - Rune + + */ +#define CFG_HRCW_MASTER 0x0cb23645 + +/* no slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#ifndef CFG_RAMBOOT +# define CFG_ENV_IS_IN_FLASH 1 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +# define CFG_ENV_SECT_SIZE 0x40000 +#else +# define CFG_ENV_IS_IN_NVRAM 1 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +# define CFG_ENV_SIZE 0x200 +#endif /* CFG_RAMBOOT */ + + +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) + +#define CFG_HID2 0 + +#define CFG_SYPCR 0xFFFFFFC3 +#define CFG_BCR 0x100C0000 +#define CFG_SIUMCR 0x0A200000 +#define CFG_SCCR 0x00000000 +#define CFG_BR0_PRELIM 0xFF801801 +#define CFG_OR0_PRELIM 0xFF800836 +#define CFG_BR1_PRELIM 0x04501801 +#define CFG_OR1_PRELIM 0xFFFF8010 + +#define CFG_RMR 0 +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) +#define CFG_RCCR 0 +/*#define CFG_PSDMR 0x016EB452*/ +#define CFG_MPTPR 0x00001900 +#define CFG_PSRT 0x00000021 + +#define CFG_RESET_ADDRESS 0x04400000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h new file mode 100644 index 000000000..f902685b3 --- /dev/null +++ b/include/configs/TOP860.h @@ -0,0 +1,439 @@ +/* + * (C) Copyright 2003 + * EMK Elektronik GmbH <www.emk-elektronik.de> + * Reinhard Meyer <r.meyer@emk-elektronik.de> + * + * Configuation settings for the TOP860 board. + * + * ----------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * TOP860 is a simple module:
+ * 16-bit wide FLASH on CS0 (2MB or more)
+ * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
+ * FEC with Am79C874 100-Base-T and Fiber Optic
+ * Ports available, but we choose SMC1 for Console
+ * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set + * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
+ *
+ * This config has been copied from MBX.h / MBX860T.h
+ */ +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +/*----------------------------------------------------------------------- + * CPU and BOARD type + */ +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ +#define CONFIG_MPC860T 1 /* even better... an FEC! */ +#define CONFIG_TOP860 1 /* ...on a TOP860 module */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_IDENT_STRING " EMK TOP860"
+ +/*----------------------------------------------------------------------- + * CLOCK settings + */ +#define CONFIG_SYSCLK 49152000
+#define CFG_XTAL 32768
+#define CONFIG_EBDF 1
+#define CONFIG_COM 3
+#define CONFIG_RTC_MPC8xx
+
+/*----------------------------------------------------------------------- + * Physical memory map as defined by EMK + */ +#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register */ +#define CFG_FLASH_BASE 0x80000000 /* FLASH in final mapping */
+#define CFG_DRAM_BASE 0x00000000 /* DRAM in final mapping */
+#define CFG_FLASH_MAX 0x00400000 /* max FLASH to expect */
+#define CFG_DRAM_MAX 0x01000000 /* max DRAM to expect */
+
+/*----------------------------------------------------------------------- + * derived values + */ +#define CFG_MF (CONFIG_SYSCLK/CFG_XTAL)
+#define CFG_CPUCLOCK CONFIG_SYSCLK
+#define CFG_BRGCLOCK CONFIG_SYSCLK
+#define CFG_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF)
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK
+
+/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +
+#define CFG_FLASH_CFI
+ +/*----------------------------------------------------------------------- + * Command interpreter + */ +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#define CONFIG_BAUDRATE 9600 +
+/* + * Allow partial commands to be matched to uniqueness. + */ +#define CFG_MATCH_PARTIAL_CMD + +/* + * List of available monitor commands. Use the system default list + * plus add some of the "non-standard" commands back in. + * See ./cmd_confdefs.h + */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_MII | \ + CFG_CMD_BEDBUG \ + ) + +#define CONFIG_AUTOSCRIPT 1
+#define CFG_LOADS_BAUD_CHANGE 1
+#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +
+#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */ +
+#ifdef CFG_HUSH_PARSER + #define CFG_PROMPT_HUSH_PS2 "> " +#endif +
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/*----------------------------------------------------------------------- + * Memory Test Command + */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +
+/*----------------------------------------------------------------------- + * Environment handler + * only the first 6k in EEPROM are available for user. Of that we use 256b + */ +#define CONFIG_SOFT_I2C
+#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ +#define CFG_ENV_OFFSET 0x1000 +#define CFG_ENV_SIZE 0x0700
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_FACT_OFFSET 0x1800 +#define CFG_FACT_SIZE 0x0800
+#define CFG_I2C_FACT_ADDR 0x57
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_SIZE 0x2000 +#define CFG_I2C_SPEED 100000 +#define CFG_I2C_SLAVE 0xFE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MISC_INIT_R
+
+#if defined (CONFIG_SOFT_I2C)
+#define SDA 0x00010
+#define SCL 0x00020
+#define DIR immr->im_cpm.cp_pbdir
+#define DAT immr->im_cpm.cp_pbdat
+#define PAR immr->im_cpm.cp_pbpar
+#define ODR immr->im_cpm.cp_pbodr
+#define I2C_INIT {PAR&=~(SDA|SCL);ODR&=~(SDA|SCL);DAT|=(SDA|SCL);DIR|=(SDA|SCL);}
+#define I2C_READ ((DAT&SDA)?1:0)
+#define I2C_SDA(x) {if(x)DAT|=SDA;else DAT&=~SDA;}
+#define I2C_SCL(x) {if(x)DAT|=SCL;else DAT&=~SCL;}
+#define I2C_DELAY {udelay(5);}
+#define I2C_ACTIVE {DIR|=SDA;}
+#define I2C_TRISTATE {DIR&=~SDA;}
+#endif + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/*----------------------------------------------------------------------- + * defines we need to get FEC running + */
+#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ +#define FEC_ENET 1 /* eth.c needs it that way... */
+#define CFG_DISCOVER_PHY 1 +#define CONFIG_MII 1 +#define CONFIG_PHY_ADDR 31 +
+/*----------------------------------------------------------------------- + * adresses + */
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +
+/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x80000000 +
+/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ +#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) +#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/* Interrupt level assignments. +*/ +#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*----------------------------------------------------------------------- + * Debug Enable Register + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 /* used in start.S */ + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
+ * 12 MF calculated Multiplication factor
+ * 4 0 0000
+ * 1 SPLSS 0 System PLL lock status sticky
+ * 1 TEXPS 1 Timer expired status
+ * 1 0 0
+ * 1 TMIST 0 Timers interrupt status
+ * 1 0 0
+ * 1 CSRC 0 Clock source (0=DFNH, 1=DFNL)
+ * 2 LPM 00 Low-power modes
+ * 1 CSR 0 Checkstop reset enable
+ * 1 LOLRE 0 Loss-of-lock reset enable
+ * 1 FIOPD 0 Force I/O pull down
+ * 5 0 00000
+ */ +#define CFG_PLPRCR (PLPRCR_TEXPS | ((CFG_MF-1)<<20)) +
+/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * set up SYPCR:
+ * 16 SWTC 0xffff Software watchdog timer count
+ * 8 BMT 0xff Bus monitor timing
+ * 1 BME 1 Bus monitor enable
+ * 3 0 000
+ * 1 SWF 1 Software watchdog freeze
+ * 1 SWE 0/1 Software watchdog enable
+ * 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET)
+ * 1 SWP 0/1 Software watchdog prescale (1=/2048)
+ */ +#if defined (CONFIG_WATCHDOG) + #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else + #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * set up SIUMCR
+ * 1 EARB 0 External arbitration
+ * 3 EARP 000 External arbitration request priority
+ * 4 0 0000
+ * 1 DSHW 0 Data show cycles
+ * 2 DBGC 00 Debug pin configuration
+ * 2 DBPC 00 Debug port pins configuration
+ * 1 0 0
+ * 1 FRC 0 FRZ pin configuration
+ * 1 DLK 0 Debug register lock
+ * 1 OPAR 0 Odd parity
+ * 1 PNCS 0 Parity enable for non memory controller regions
+ * 1 DPC 0 Data parity pins configuration
+ * 1 MPRE 0 Multiprocessor reservation enable
+ * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
+ * 1 AEME 0 Async external master enable
+ * 1 SEME 0 Sync external master enable
+ * 1 BSC 0 Byte strobe configuration
+ * 1 GB5E 0 GPL_B5 enable
+ * 1 B2DD 0 Bank 2 double drive
+ * 1 B3DD 0 Bank 3 double drive
+ * 4 0 0000
+ */ +#define CFG_SIUMCR (SIUMCR_MLRC11) +
+/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * set up SCCR (System Clock and Reset Control Register)
+ * 1 0 0
+ * 2 COM 11 Clock output module (00=full, 01=half, 11=off)
+ * 3 0 000
+ * 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2)
+ * 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512)
+ * 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK)
+ * 1 CRQEN 0 CPM request enable
+ * 1 PRQEN 0 Power management request enable
+ * 2 0 00
+ * 2 EBDF xx External bus division factor
+ * 2 0 00
+ * 2 DFSYNC 00 Division factor for SYNCLK
+ * 2 DFBRG 00 Division factor for BRGCLK
+ * 3 DFNL 000 Division factor low frequency
+ * 3 DFNH 000 Division factor high frequency
+ * 5 0 00000
+ */ +#define SCCR_MASK 0 +#if CONFIG_EBDF
+ #define CFG_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01) +#else
+ #define CFG_SCCR (SCCR_COM11 | SCCR_TBS) +#endif
+ +/*----------------------------------------------------------------------- + * Chip Select 0 - FLASH + *----------------------------------------------------------------------- + * Preliminary Values + */ +/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR) +#define CFG_OR0_PRELIM (-CFG_FLASH_MAX | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V ) +
+/*----------------------------------------------------------------------- + * misc + *----------------------------------------------------------------------- + * + */ +/* + * Set the autoboot delay in seconds. A delay of -1 disables autoboot + */ +#define CONFIG_BOOTDELAY 5 + +/* + * Pass the clock frequency to the Linux kernel in units of MHz + */ +#define CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_PREBOOT \ + "echo;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "bootm" + +/* + * BOOTP options + */ +#undef CONFIG_BOOTP_MASK
+#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE \ + )
+
+ +/* + * Set default IP stuff just to get bootstrap entries into the + * environment so that we can autoscript the full default environment. + */ +#define CONFIG_ETHADDR 9a:52:63:15:85:25 +#define CONFIG_SERVERIP 10.0.4.200 +#define CONFIG_IPADDR 10.0.4.111 +
+/*----------------------------------------------------------------------- + * Defaults for Autoscript + */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_TFTP_LOADADDR 0x00100000 +
+/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +
+#endif /* __CONFIG_H */ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 1b867e056..b5610c950 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -81,7 +81,7 @@ #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ #define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ - +#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ /* * Miscellaneous configurable options */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 0c06e9181..89373b904 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -87,7 +87,7 @@ #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ #define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ - +#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ /* * Miscellaneous configurable options */ diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 187c33f29..87282acc3 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -70,12 +70,13 @@ #include <cmd_confdefs.h> #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" #define CONFIG_ETHADDR 08:00:3e:26:0a:5b #define CONFIG_NETMASK 255.255.0.0 #define CONFIG_IPADDR 192.168.0.21 #define CONFIG_SERVERIP 192.168.0.250 -#define CONFIG_BOOTCOMMAND "FIXME" +#define CONFIG_BOOTCOMMAND "bootm 40000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" +#define CONFIG_CMDLINE_TAG #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ @@ -100,7 +101,7 @@ #define CFG_LOAD_ADDR 0xa8000000 /* default load address */ #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ +#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } @@ -130,8 +131,10 @@ #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ #define CFG_DRAM_BASE 0xa0000000 #define CFG_DRAM_SIZE 0x04000000 @@ -168,8 +171,7 @@ #define CFG_MSC1_VAL 0x3FF1A441 #define CFG_MSC2_VAL 0x7FF17FF1 #define CFG_MDCNFG_VAL 0x00001AC9 -#define CFG_MDREFR_VAL 0x000BC018 -#define CFG_MDREFR_VAL_100 0x00018018 +#define CFG_MDREFR_VAL 0x00018018 #define CFG_MDMRS_VAL 0x00000000 /* @@ -193,8 +195,8 @@ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ /* FIXME */ #define CFG_ENV_IS_IN_FLASH 1 diff --git a/include/spd.h b/include/spd.h new file mode 100644 index 000000000..1ad4d801f --- /dev/null +++ b/include/spd.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2003 Arabella Software Ltd. + * Yuli Barcohen <yuli@arabellasw.com> + * + * Serial Presence Detect (SPD) EEPROM format according to the + * Intel's PC SDRAM Serial Presence Detect (SPD) Specification, + * revision 1.2B, November 1999 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _SPD_H_ +#define _SPD_H_ + +typedef struct spd_eeprom_s { + unsigned char info_size; /* # of bytes written into serial memory */ + unsigned char chip_size; /* Total # of bytes of SPD memory device */ + unsigned char mem_type; /* Fundamental memory type (FPM, EDO, SDRAM...) */ + unsigned char nrow_addr; /* # of Row Addresses on this assembly */ + unsigned char ncol_addr; /* # of Column Addresses on this assembly */ + unsigned char nrows; /* # of Module Rows on this assembly */ + unsigned char dataw_lsb; /* Data Width of this assembly */ + unsigned char dataw_msb; /* ... Data Width continuation */ + unsigned char voltage; /* Voltage interface standard of this assembly */ + unsigned char clk_cycle; /* SDRAM Cycle time at CL=X */ + unsigned char clk_access; /* SDRAM Access from Clock at CL=X */ + unsigned char config; /* DIMM Configuration type (non-parity, ECC) */ + unsigned char refresh; /* Refresh Rate/Type */ + unsigned char primw; /* Primary SDRAM Width */ + unsigned char ecw; /* Error Checking SDRAM width */ + unsigned char min_delay; /* Min Clock Delay for Back to Back Random Address */ + unsigned char burstl; /* Burst Lengths Supported */ + unsigned char nbanks; /* # of Banks on Each SDRAM Device */ + unsigned char cas_lat; /* CAS# Latencies Supported */ + unsigned char cs_lat; /* CS# Latency */ + unsigned char write_lat; /* Write Latency (also called Write Recovery time) */ + unsigned char mod_attr; /* SDRAM Module Attributes */ + unsigned char dev_attr; /* SDRAM Device Attributes */ + unsigned char clk_cycle2; /* Min SDRAM Cycle time at CL=X-1 */ + unsigned char clk_access2; /* SDRAM Access from Clock at CL=X-1 */ + unsigned char clk_cycle3; /* Min SDRAM Cycle time at CL=X-2 */ + unsigned char clk_access3; /* Max SDRAM Access from Clock at CL=X-2 */ + unsigned char trp; /* Min Row Precharge Time (tRP) */ + unsigned char trrd; /* Min Row Active to Row Active (tRRD) */ + unsigned char trcd; /* Min RAS to CAS Delay (tRCD) */ + unsigned char tras; /* Minimum RAS Pulse Width (tRAS) */ + unsigned char row_dens; /* Density of each row on module */ + unsigned char ca_setup; /* Command and Address signal input setup time */ + unsigned char ca_hold; /* Command and Address signal input hold time */ + unsigned char data_setup; /* Data signal input setup time */ + unsigned char data_hold; /* Data signal input hold time */ + unsigned char sset[26]; /* Superset Information (may be used in future) */ + unsigned char spd_rev; /* SPD Data Revision Code */ + unsigned char cksum; /* Checksum for bytes 0-62 */ + unsigned char mid[8]; /* Manufacturer's JEDEC ID code per JEP-108E */ + unsigned char mloc; /* Manufacturing Location */ + unsigned char mpart[18]; /* Manufacturer's Part Number */ + unsigned char rev[2]; /* Revision Code */ + unsigned char mdate[2]; /* Manufacturing Date */ + unsigned char sernum[4]; /* Assembly Serial Number */ + unsigned char mspec[27]; /* Manufacturer Specific Data */ + unsigned char freq; /* Intel specification frequency */ + unsigned char intel_cas; /* Intel Specification CAS# Latency support */ +} spd_eeprom_t; + +#endif /* _SPD_H_ */ diff --git a/include/spd_sdram.h b/include/spd_sdram.h new file mode 100644 index 000000000..feb1bbd4c --- /dev/null +++ b/include/spd_sdram.h @@ -0,0 +1,6 @@ +#ifndef _SPD_SDRAM_H_ +#define _SPD_SDRAM_H_ + +long int spd_sdram(int(read_spd)(uint addr)); + +#endif |