diff options
Diffstat (limited to 'include')
156 files changed, 1547 insertions, 757 deletions
diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index 4a03cecb5..69a217487 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -66,43 +66,6 @@ #define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */ #define L2CR_L2IP 0x00000001 /* global invalidate in progress */ -/*---------------------------------------------------------------- - * BAT settings. Look in config_<BOARD>.h for the actual setup - */ - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 -#define BATU_INVALID 0x00000000 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 -#define BATL_NO_ACCESS 0x00000000 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -#define BATL_PP_NO_ACCESS BATL_PP_00 -#define BATL_PP_RO BATL_PP_01 -#define BATL_PP_RW BATL_PP_10 - #ifndef __ASSEMBLY__ /* cpu ids we detect */ typedef enum __cpu_t { diff --git a/include/api_public.h b/include/api_public.h index d3164f69c..5940d81fd 100644 --- a/include/api_public.h +++ b/include/api_public.h @@ -57,6 +57,7 @@ #define API_ENOMEM 3 /* no memory */ #define API_EBUSY 4 /* busy, occupied etc. */ #define API_EIO 5 /* I/O error */ +#define API_ESYSC 6 /* syscall error */ typedef int (*scp_t)(int, int *, ...); diff --git a/include/asm-arm/arch-omap3/omap_gpmc.h b/include/asm-arm/arch-omap3/omap_gpmc.h index 4edf61175..bd22bce83 100644 --- a/include/asm-arm/arch-omap3/omap_gpmc.h +++ b/include/asm-arm/arch-omap3/omap_gpmc.h @@ -81,4 +81,3 @@ #endif #endif /* __ASM_ARCH_OMAP_GPMC_H */ - diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h deleted file mode 100644 index 85e144b68..000000000 --- a/include/asm-arm/arch-pxa/mmc.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * linux/drivers/mmc/mmc_pxa.h - * - * Author: Vladimir Shebordaev, Igor Oblakov - * Copyright: MontaVista Software Inc. - * - * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __MMC_PXA_P_H__ -#define __MMC_PXA_P_H__ - -/* PXA-250 MMC controller registers */ - -/* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (0x0001UL) -#define MMC_STRPCL_START_CLK (0x0002UL) - -/* MMC_STAT */ -#define MMC_STAT_END_CMD_RES (0x0001UL << 13) -#define MMC_STAT_PRG_DONE (0x0001UL << 12) -#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) -#define MMC_STAT_CLK_EN (0x0001UL << 8) -#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) -#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) -#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4) -#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) -#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) -#define MMC_STAT_READ_TIME_OUT (0x0001UL) - -#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\ - |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\ - |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR) - -/* MMC_CLKRT */ -#define MMC_CLKRT_20MHZ (0x0000UL) -#define MMC_CLKRT_10MHZ (0x0001UL) -#define MMC_CLKRT_5MHZ (0x0002UL) -#define MMC_CLKRT_2_5MHZ (0x0003UL) -#define MMC_CLKRT_1_25MHZ (0x0004UL) -#define MMC_CLKRT_0_625MHZ (0x0005UL) -#define MMC_CLKRT_0_3125MHZ (0x0006UL) - -/* MMC_SPI */ -#define MMC_SPI_DISABLE (0x00UL) -#define MMC_SPI_EN (0x01UL) -#define MMC_SPI_CS_EN (0x01UL << 2) -#define MMC_SPI_CS_ADDRESS (0x01UL << 3) -#define MMC_SPI_CRC_ON (0x01UL << 1) - -/* MMC_CMDAT */ -#define MMC_CMDAT_SD_4DAT (0x0001UL << 8) -#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) -#define MMC_CMDAT_INIT (0x0001UL << 6) -#define MMC_CMDAT_BUSY (0x0001UL << 5) -#define MMC_CMDAT_BCR (0x0003UL << 5) -#define MMC_CMDAT_STREAM (0x0001UL << 4) -#define MMC_CMDAT_BLOCK (0x0000UL << 4) -#define MMC_CMDAT_WRITE (0x0001UL << 3) -#define MMC_CMDAT_READ (0x0000UL << 3) -#define MMC_CMDAT_DATA_EN (0x0001UL << 2) -#define MMC_CMDAT_R0 (0) -#define MMC_CMDAT_R1 (0x0001UL) -#define MMC_CMDAT_R2 (0x0002UL) -#define MMC_CMDAT_R3 (0x0003UL) - -/* MMC_RESTO */ -#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ - -/* MMC_RDTO */ -#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ - -/* MMC_BLKLEN */ -#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ - -/* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) -#define MMC_PRTBUF_BUF_FULL (0x00UL ) - -/* MMC_I_MASK */ -#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_MASK_STOP_CMD (0x01UL << 3) -#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) -#define MMC_I_MASK_PRG_DONE (0x01UL << 1) -#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL) -#define MMC_I_MASK_ALL (0x07fUL) - - -/* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_REG_STOP_CMD (0x01UL << 3) -#define MMC_I_REG_END_CMD_RES (0x01UL << 2) -#define MMC_I_REG_PRG_DONE (0x01UL << 1) -#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) -#define MMC_I_REG_ALL (0x007fUL) - -/* MMC_CMD */ -#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ -#define CMD(x) (x) - -#define MMC_DEFAULT_RCA 1 - -#define MMC_BLOCK_SIZE 512 -#define MMC_MAX_BLOCK_SIZE 512 - -#define MMC_R1_IDLE_STATE 0x01 -#define MMC_R1_ERASE_STATE 0x02 -#define MMC_R1_ILLEGAL_CMD 0x04 -#define MMC_R1_COM_CRC_ERR 0x08 -#define MMC_R1_ERASE_SEQ_ERR 0x01 -#define MMC_R1_ADDR_ERR 0x02 -#define MMC_R1_PARAM_ERR 0x04 - -#define MMC_R1B_WP_ERASE_SKIP 0x0002 -#define MMC_R1B_ERR 0x0004 -#define MMC_R1B_CC_ERR 0x0008 -#define MMC_R1B_CARD_ECC_ERR 0x0010 -#define MMC_R1B_WP_VIOLATION 0x0020 -#define MMC_R1B_ERASE_PARAM 0x0040 -#define MMC_R1B_OOR 0x0080 -#define MMC_R1B_IDLE_STATE 0x0100 -#define MMC_R1B_ERASE_RESET 0x0200 -#define MMC_R1B_ILLEGAL_CMD 0x0400 -#define MMC_R1B_COM_CRC_ERR 0x0800 -#define MMC_R1B_ERASE_SEQ_ERR 0x1000 -#define MMC_R1B_ADDR_ERR 0x2000 -#define MMC_R1B_PARAM_ERR 0x4000 - -typedef struct mmc_cid -{ -/* FIXME: BYTE_ORDER */ - uchar year:4, - month:4; - uchar sn[3]; - uchar fwrev:4, - hwrev:4; - uchar name[6]; - uchar id[3]; -} mmc_cid_t; - -typedef struct mmc_csd -{ - uint8_t csd_structure:2, - spec_ver:4, - rsvd1:2; - uint8_t taac; - uint8_t nsac; - uint8_t tran_speed; - uint16_t ccc:12, - read_bl_len:4; - uint64_t read_bl_partial:1, - write_blk_misalign:1, - read_blk_misalign:1, - dsr_imp:1, - rsvd2:2, - c_size:12, - vdd_r_curr_min:3, - vdd_r_curr_max:3, - vdd_w_curr_min:3, - vdd_w_curr_max:3, - c_size_mult:3, - erase_blk_en:1, - sector_size:7, - wp_grp_size:7, - wp_grp_enable:1, - default_ecc:2, - r2w_factor:3, - write_bl_len:4, - write_bl_partial:1, - rsvd3:4, - content_prot_app:1; - uint8_t file_format_grp:1, - copy:1, - perm_write_protect:1, - tmp_write_protect:1, - file_format:2, - ecc:2; -} mmc_csd_t; - -#endif /* __MMC_PXA_P_H__ */ diff --git a/include/asm-arm/arch-lpc2292/mmc.h b/include/asm-arm/config.h index e664a5f67..049c44eaf 100644 --- a/include/asm-arm/arch-lpc2292/mmc.h +++ b/include/asm-arm/config.h @@ -1,6 +1,5 @@ /* - * A dummy header file for use with the LPC2292 port to keep the - * compiler happy. + * Copyright 2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -9,14 +8,17 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * */ -#ifndef _MMC_ARM_TDM_H_ -#define _MMC_ARM_TDM_H_ -#endif /* _MMC_ARM_TDM_H_ */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h deleted file mode 100644 index 9caba9168..000000000 --- a/include/asm-avr32/arch-at32ap700x/mmc.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_MMC_H -#define __ASM_AVR32_MMC_H - -struct mmc_cid { - unsigned long psn; - unsigned short oid; - unsigned char mid; - unsigned char prv; - unsigned char mdt; - char pnm[7]; -}; - -struct mmc_csd -{ - u8 csd_structure:2, - spec_vers:4, - rsvd1:2; - u8 taac; - u8 nsac; - u8 tran_speed; - u16 ccc:12, - read_bl_len:4; - u64 read_bl_partial:1, - write_blk_misalign:1, - read_blk_misalign:1, - dsr_imp:1, - rsvd2:2, - c_size:12, - vdd_r_curr_min:3, - vdd_r_curr_max:3, - vdd_w_curr_min:3, - vdd_w_curr_max:3, - c_size_mult:3, - sector_size:5, - erase_grp_size:5, - wp_grp_size:5, - wp_grp_enable:1, - default_ecc:2, - r2w_factor:3, - write_bl_len:4, - write_bl_partial:1, - rsvd3:5; - u8 file_format_grp:1, - copy:1, - perm_write_protect:1, - tmp_write_protect:1, - file_format:2, - ecc:2; - u8 crc:7; - u8 one:1; -}; - -#define R1_ILLEGAL_COMMAND (1 << 22) -#define R1_APP_CMD (1 << 5) - -#endif /* __ASM_AVR32_MMC_H */ diff --git a/include/asm-avr32/config.h b/include/asm-avr32/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-avr32/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-blackfin/blackfin-config-pre.h b/include/asm-blackfin/blackfin-config-pre.h index a1fae5c9a..9df01ad25 100644 --- a/include/asm-blackfin/blackfin-config-pre.h +++ b/include/asm-blackfin/blackfin-config-pre.h @@ -60,4 +60,13 @@ static inline const char *get_bfin_boot_mode(int bfin_boot) } #endif +/* Define the default SPI CS used when booting out of SPI */ +#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \ + defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \ + defined(__ADSPBF51x__) +# define BFIN_BOOT_SPI_SSEL 2 +#else +# define BFIN_BOOT_SPI_SSEL 1 +#endif + #endif diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-blackfin/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h index 7c5127eca..035e8d835 100644 --- a/include/asm-blackfin/mach-bf527/anomaly.h +++ b/include/asm-blackfin/mach-bf527/anomaly.h @@ -7,82 +7,154 @@ */ /* This file shoule be up to date with: - * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List + * - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ +#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) +# define ANOMALY_BF526 1 +#else +# define ANOMALY_BF526 0 +#endif +#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__) +# define ANOMALY_BF527 1 +#else +# define ANOMALY_BF527 0 +#endif + /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) +#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ +#define ANOMALY_05000310 (1) +/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ +#define ANOMALY_05000313 (__SILICON_REVISION__ < 2) /* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (1) +#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (1) +#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ -#define ANOMALY_05000341 (1) +#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ -#define ANOMALY_05000342 (1) +#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* USB Calibration Value Is Not Initialized */ -#define ANOMALY_05000346 (1) +#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* USB Calibration Value to use */ +#define ANOMALY_05000346_value 0xE510 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (1) +#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Security Features Are Not Functional */ -#define ANOMALY_05000348 (__SILICON_REVISION__ < 1) +#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1) +/* bfrom_SysControl() Firmware Function Performs Improper System Reset */ +#define ANOMALY_05000353 (ANOMALY_BF526) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (1) +#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) +#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Incorrect Revision Number in DSPID Register */ -#define ANOMALY_05000364 (__SILICON_REVISION__ > 0) +#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) -/* New Feature: Higher Default CCLK Rate */ -#define ANOMALY_05000368 (1) +/* Incorrect Default CSEL Value in PLL_DIV */ +#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) +#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Authentication Fails To Initiate */ -#define ANOMALY_05000376 (__SILICON_REVISION__ > 0) +#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Data Read From L3 Memory by USB DMA May be Corrupted */ -#define ANOMALY_05000380 (1) -/* USB Full-speed Mode not Fully Tested */ -#define ANOMALY_05000381 (1) -/* New Feature: Boot from OTP Memory */ -#define ANOMALY_05000385 (1) -/* New Feature: bfrom_SysControl() Routine */ -#define ANOMALY_05000386 (1) -/* New Feature: Programmable Preboot Settings */ -#define ANOMALY_05000387 (1) +#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* 8-Bit NAND Flash Boot Mode Not Functional */ +#define ANOMALY_05000382 (__SILICON_REVISION__ < 2) +/* Host Must Not Read Back During Host DMA Boot */ +#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Boot from OTP Memory Not Functional */ +#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* bfrom_SysControl() Firmware Routine Not Functional */ +#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Programmable Preboot Settings Not Functional */ +#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* CRC32 Checksum Support Not Functional */ +#define ANOMALY_05000388 (__SILICON_REVISION__ < 2) /* Reset Vector Must Not Be in SDRAM Memory Space */ -#define ANOMALY_05000389 (1) -/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */ -#define ANOMALY_05000392 (1) -/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000393 (1) -/* New Feature: Log Buffer Functionality */ -#define ANOMALY_05000394 (1) -/* New Feature: Hook Routine Functionality */ -#define ANOMALY_05000395 (1) -/* New Feature: Header Indirect Bit */ -#define ANOMALY_05000396 (1) -/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */ -#define ANOMALY_05000397 (1) -/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */ -#define ANOMALY_05000398 (1) -/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */ -#define ANOMALY_05000399 (1) +#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Log Buffer Not Functional */ +#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Hook Routine Not Functional */ +#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Header Indirect Bit Not Functional */ +#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ +#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ +#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ +#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ -#define ANOMALY_05000401 (1) +#define ANOMALY_05000401 (__SILICON_REVISION__ < 2) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (__SILICON_REVISION__ < 2) +/* Lockbox SESR Disallows Certain User Interrupts */ +#define ANOMALY_05000404 (__SILICON_REVISION__ < 2) +/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ +#define ANOMALY_05000405 (1) +/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ +#define ANOMALY_05000407 (__SILICON_REVISION__ < 2) +/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ +#define ANOMALY_05000408 (1) +/* Lockbox firmware leaves MDMA0 channel enabled */ +#define ANOMALY_05000409 (__SILICON_REVISION__ < 2) +/* Incorrect Default Internal Voltage Regulator Setting */ +#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ +#define ANOMALY_05000411 (__SILICON_REVISION__ < 2) +/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ +#define ANOMALY_05000414 (__SILICON_REVISION__ < 2) +/* DEB2_URGENT Bit Not Functional */ +#define ANOMALY_05000415 (__SILICON_REVISION__ < 2) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ +#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ +#define ANOMALY_05000418 (__SILICON_REVISION__ < 2) +/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ +#define ANOMALY_05000420 (__SILICON_REVISION__ < 2) +/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ +#define ANOMALY_05000421 (1) +/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ +#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) +/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ +#define ANOMALY_05000423 (__SILICON_REVISION__ < 2) +/* Internal Voltage Regulator Not Trimmed */ +#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ +#define ANOMALY_05000425 (__SILICON_REVISION__ < 2) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */ +#define ANOMALY_05000426 (1) +/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ +#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) +/* Software System Reset Corrupts PLL_LOCKCNT Register */ +#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) +/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ +#define ANOMALY_05000432 (ANOMALY_BF526) +/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ +#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -95,10 +167,12 @@ #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) +#define ANOMALY_05000285 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) +#define ANOMALY_05000312 (0) #define ANOMALY_05000323 (0) -#define ANOMALY_05000353 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000412 (0) #endif diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index 7c34c3813..0d3a03429 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List + * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -97,11 +97,11 @@ /* UART STB Bit Incorrectly Affects Receiver Setting */ #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ -#define ANOMALY_05000233 (__SILICON_REVISION__ < 4) +#define ANOMALY_05000233 (__SILICON_REVISION__ < 6) /* Incorrect Revision Number in DSPID Register */ #define ANOMALY_05000234 (__SILICON_REVISION__ == 4) /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ -#define ANOMALY_05000242 (__SILICON_REVISION__ < 4) +#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ @@ -131,7 +131,7 @@ /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) +#define ANOMALY_05000265 (1) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ #define ANOMALY_05000269 (__SILICON_REVISION__ < 5) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ @@ -141,23 +141,23 @@ /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) /* Writes to Synchronous SDRAM Memory May Be Lost */ -#define ANOMALY_05000273 (1) +#define ANOMALY_05000273 (__SILICON_REVISION__ < 6) /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ #define ANOMALY_05000276 (1) /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (1) +#define ANOMALY_05000277 (__SILICON_REVISION__ < 6) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ -#define ANOMALY_05000278 (1) +#define ANOMALY_05000278 (__SILICON_REVISION__ < 6) /* False Hardware Error Exception When ISR Context Is Not Restored */ -#define ANOMALY_05000281 (1) +#define ANOMALY_05000281 (__SILICON_REVISION__ < 6) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ -#define ANOMALY_05000282 (1) +#define ANOMALY_05000282 (__SILICON_REVISION__ < 6) /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ -#define ANOMALY_05000283 (1) +#define ANOMALY_05000283 (__SILICON_REVISION__ < 6) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ -#define ANOMALY_05000288 (1) +#define ANOMALY_05000288 (__SILICON_REVISION__ < 6) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (1) +#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) /* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ @@ -169,30 +169,37 @@ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ -#define ANOMALY_05000311 (1) +#define ANOMALY_05000311 (__SILICON_REVISION__ < 6) /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) +#define ANOMALY_05000312 (__SILICON_REVISION__ < 6) /* PPI Is Level-Sensitive on First Transfer */ -#define ANOMALY_05000313 (1) +#define ANOMALY_05000313 (__SILICON_REVISION__ < 6) /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ -#define ANOMALY_05000315 (1) +#define ANOMALY_05000315 (__SILICON_REVISION__ < 6) /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ -#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) +#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) +#define ANOMALY_05000357 (__SILICON_REVISION__ < 6) /* UART Break Signal Issues */ #define ANOMALY_05000363 (__SILICON_REVISION__ < 5) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) +#define ANOMALY_05000371 (__SILICON_REVISION__ < 6) /* PPI Does Not Start Properly In Specific Mode */ -#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5) +#define ANOMALY_05000400 (__SILICON_REVISION__ == 5) /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) +#define ANOMALY_05000402 (__SILICON_REVISION__ == 5) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) - +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ +#define ANOMALY_05000425 (1) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ +#define ANOMALY_05000426 (1) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* These anomalies have been "phased" out of analog.com anomaly sheets and are * here to show running on older silicon just isn't feasible. @@ -271,5 +278,9 @@ #define ANOMALY_05000266 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (1) +#define ANOMALY_05000386 (1) +#define ANOMALY_05000412 (0) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000435 (0) #endif diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index 8d7f30579..9cb39121d 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List + * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -148,6 +148,14 @@ #define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ +#define ANOMALY_05000425 (1) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ +#define ANOMALY_05000426 (1) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -160,5 +168,9 @@ #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000386 (1) +#define ANOMALY_05000412 (0) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000435 (0) #endif diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 1dc75ef1a..3b5430999 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision F, 06/11/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List + * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -36,7 +36,7 @@ /* TWI Slave Boot Mode Is Not Functional */ #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) /* External FIFO Boot Mode Is Not Functional */ -#define ANOMALY_05000325 (__SILICON_REVISION__ < 1) +#define ANOMALY_05000325 (__SILICON_REVISION__ < 2) /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) /* Incorrect Access of OTP_STATUS During otp_write() Function */ @@ -61,6 +61,8 @@ #define ANOMALY_05000344 (__SILICON_REVISION__ < 1) /* USB Calibration Value Is Not Intialized */ #define ANOMALY_05000346 (__SILICON_REVISION__ < 1) +/* USB Calibration Value to use */ +#define ANOMALY_05000346_value 0x5411 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ #define ANOMALY_05000347 (__SILICON_REVISION__ < 1) /* Data Lost when Core Reads SDH Data FIFO */ @@ -68,7 +70,7 @@ /* PLL Status Register Is Inaccurate */ #define ANOMALY_05000351 (__SILICON_REVISION__ < 1) /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ -#define ANOMALY_05000353 (1) +#define ANOMALY_05000353 (__SILICON_REVISION__ < 2) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (__SILICON_REVISION__ < 1) /* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ @@ -86,13 +88,13 @@ /* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ #define ANOMALY_05000370 (__SILICON_REVISION__ < 1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) +#define ANOMALY_05000371 (__SILICON_REVISION__ < 2) /* USB DP/DM Data Pins May Lose State When Entering Hibernate */ #define ANOMALY_05000372 (__SILICON_REVISION__ < 1) /* Mobile DDR Operation Not Functional */ #define ANOMALY_05000377 (1) /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ -#define ANOMALY_05000378 (1) +#define ANOMALY_05000378 (__SILICON_REVISION__ < 2) /* 16-Bit NAND FLASH Boot Mode Is Not Functional */ #define ANOMALY_05000379 (1) /* 8-Bit NAND Flash Boot Mode Not Functional */ @@ -126,25 +128,37 @@ /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ #define ANOMALY_05000397 (__SILICON_REVISION__ < 1) /* Lockbox SESR Disallows Certain User Interrupts */ -#define ANOMALY_05000404 (1) +#define ANOMALY_05000404 (__SILICON_REVISION__ < 2) /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ #define ANOMALY_05000405 (1) /* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */ -#define ANOMALY_05000406 (1) +#define ANOMALY_05000406 (__SILICON_REVISION__ < 2) /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ -#define ANOMALY_05000407 (1) +#define ANOMALY_05000407 (__SILICON_REVISION__ < 2) /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ #define ANOMALY_05000408 (1) /* Lockbox firmware leaves MDMA0 channel enabled */ -#define ANOMALY_05000409 (1) +#define ANOMALY_05000409 (__SILICON_REVISION__ < 2) /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ -#define ANOMALY_05000411 (1) -/* FIFO Boot Mode Is Not Functional */ -#define ANOMALY_05000412 (1) +#define ANOMALY_05000411 (__SILICON_REVISION__ < 2) /* NAND Boot Mode Not Compatible With Some NAND Flash Devices */ -#define ANOMALY_05000413 (1) +#define ANOMALY_05000413 (__SILICON_REVISION__ < 2) /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ -#define ANOMALY_05000414 (1) +#define ANOMALY_05000414 (__SILICON_REVISION__ < 2) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ +#define ANOMALY_05000425 (1) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */ +#define ANOMALY_05000426 (1) +/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ +#define ANOMALY_05000427 (__SILICON_REVISION__ < 2) +/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */ +#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) +/* Software System Reset Corrupts PLL_LOCKCNT Register */ +#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -161,5 +175,8 @@ #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000363 (0) +#define ANOMALY_05000412 (0) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000435 (0) #endif diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h index e9c4ca878..1a9e17562 100644 --- a/include/asm-blackfin/mach-bf561/anomaly.h +++ b/include/asm-blackfin/mach-bf561/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List + * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -264,6 +264,18 @@ #define ANOMALY_05000371 (1) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) +/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ +#define ANOMALY_05000412 (1) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ +#define ANOMALY_05000425 (1) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ +#define ANOMALY_05000426 (1) +/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */ +#define ANOMALY_05000428 (__SILICON_REVISION__ > 3) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000158 (0) @@ -271,5 +283,8 @@ #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000353 (1) +#define ANOMALY_05000386 (1) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000435 (0) #endif diff --git a/include/asm-i386/config.h b/include/asm-i386/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-i386/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-m68k/config.h b/include/asm-m68k/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-m68k/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h index 787761689..d25261bcd 100644 --- a/include/asm-m68k/m5271.h +++ b/include/asm-m68k/m5271.h @@ -37,8 +37,27 @@ #define MCF_FMPLL_SYNCR 0x120000 #define MCF_FMPLL_SYNSR 0x120004 + #define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24) +#define MCF_SYNCR_MFD_4X 0x00000000 +#define MCF_SYNCR_MFD_6X 0x01000000 +#define MCF_SYNCR_MFD_8X 0x02000000 +#define MCF_SYNCR_MFD_10X 0x03000000 +#define MCF_SYNCR_MFD_12X 0x04000000 +#define MCF_SYNCR_MFD_14X 0x05000000 +#define MCF_SYNCR_MFD_16X 0x06000000 +#define MCF_SYNCR_MFD_18X 0x07000000 + #define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19) +#define MCF_SYNCR_RFD_DIV1 0x00000000 +#define MCF_SYNCR_RFD_DIV2 0x00080000 +#define MCF_SYNCR_RFD_DIV4 0x00100000 +#define MCF_SYNCR_RFD_DIV8 0x00180000 +#define MCF_SYNCR_RFD_DIV16 0x00200000 +#define MCF_SYNCR_RFD_DIV32 0x00280000 +#define MCF_SYNCR_RFD_DIV64 0x00300000 +#define MCF_SYNCR_RFD_DIV128 0x00380000 + #define MCF_FMPLL_SYNSR_LOCK 0x8 #define MCF_WTM_WCR 0x140000 @@ -50,17 +69,79 @@ #define MCF_RCM_RCR_FRCRSTOUT 0x40 #define MCF_RCM_RCR_SOFTRST 0x80 +#define MCF_GPIO_PODR_ADDR 0x100000 +#define MCF_GPIO_PODR_DATAH 0x100001 +#define MCF_GPIO_PODR_DATAL 0x100002 +#define MCF_GPIO_PODR_BUSCTL 0x100003 +#define MCF_GPIO_PODR_BS 0x100004 +#define MCF_GPIO_PODR_CS 0x100005 +#define MCF_GPIO_PODR_SDRAM 0x100006 +#define MCF_GPIO_PODR_FECI2C 0x100007 +#define MCF_GPIO_PODR_UARTH 0x100008 +#define MCF_GPIO_PODR_UARTL 0x100009 +#define MCF_GPIO_PODR_QSPI 0x10000A +#define MCF_GPIO_PODR_TIMER 0x10000B + +#define MCF_GPIO_PDDR_ADDR 0x100010 +#define MCF_GPIO_PDDR_DATAH 0x100011 +#define MCF_GPIO_PDDR_DATAL 0x100012 +#define MCF_GPIO_PDDR_BUSCTL 0x100013 +#define MCF_GPIO_PDDR_BS 0x100014 +#define MCF_GPIO_PDDR_CS 0x100015 +#define MCF_GPIO_PDDR_SDRAM 0x100016 +#define MCF_GPIO_PDDR_FECI2C 0x100017 +#define MCF_GPIO_PDDR_UARTH 0x100018 +#define MCF_GPIO_PDDR_UARTL 0x100019 +#define MCF_GPIO_PDDR_QSPI 0x10001A +#define MCF_GPIO_PDDR_TIMER 0x10001B + +#define MCF_GPIO_PPDSDR_ADDR 0x100020 +#define MCF_GPIO_PPDSDR_DATAH 0x100021 +#define MCF_GPIO_PPDSDR_DATAL 0x100022 +#define MCF_GPIO_PPDSDR_BUSCTL 0x100023 +#define MCF_GPIO_PPDSDR_BS 0x100024 +#define MCF_GPIO_PPDSDR_CS 0x100025 +#define MCF_GPIO_PPDSDR_SDRAM 0x100026 +#define MCF_GPIO_PPDSDR_FECI2C 0x100027 +#define MCF_GPIO_PPDSDR_UARTH 0x100028 +#define MCF_GPIO_PPDSDR_UARTL 0x100029 +#define MCF_GPIO_PPDSDR_QSPI 0x10002A +#define MCF_GPIO_PPDSDR_TIMER 0x10002B + +#define MCF_GPIO_PCLRR_ADDR 0x100030 +#define MCF_GPIO_PCLRR_DATAH 0x100031 +#define MCF_GPIO_PCLRR_DATAL 0x100032 +#define MCF_GPIO_PCLRR_BUSCTL 0x100033 +#define MCF_GPIO_PCLRR_BS 0x100034 +#define MCF_GPIO_PCLRR_CS 0x100035 +#define MCF_GPIO_PCLRR_SDRAM 0x100036 +#define MCF_GPIO_PCLRR_FECI2C 0x100037 +#define MCF_GPIO_PCLRR_UARTH 0x100038 +#define MCF_GPIO_PCLRR_UARTL 0x100039 +#define MCF_GPIO_PCLRR_QSPI 0x10003A +#define MCF_GPIO_PCLRR_TIMER 0x10003B + #define MCF_GPIO_PAR_AD 0x100040 +#define MCF_GPIO_PAR_BUSCTL 0x100042 +#define MCF_GPIO_PAR_BS 0x100044 #define MCF_GPIO_PAR_CS 0x100045 #define MCF_GPIO_PAR_SDRAM 0x100046 #define MCF_GPIO_PAR_FECI2C 0x100047 #define MCF_GPIO_PAR_UART 0x100048 +#define MCF_GPIO_PAR_QSPI 0x10004A +#define MCF_GPIO_PAR_TIMER 0x10004C + +#define MCF_DSCR_EIM 0x100050 +#define MCF_DCSR_FEC12C 0x100052 +#define MCF_DCSR_UART 0x100053 +#define MCF_DCSR_QSPI 0x100054 +#define MCF_DCSR_TIMER 0x100055 #define MCF_CCM_CIR 0x11000A #define MCF_CCM_CIR_PRN_MASK 0x3F #define MCF_CCM_CIR_PIN_LEN 6 -#define MCF_CCM_CIR_PIN_MCF5270 0x2e -#define MCF_CCM_CIR_PIN_MCF5271 0x80 +#define MCF_CCM_CIR_PIN_MCF5270 0x002e +#define MCF_CCM_CIR_PIN_MCF5271 0x0032 #define MCF_GPIO_AD_ADDR23 0x80 #define MCF_GPIO_AD_ADDR22 0x40 diff --git a/include/asm-microblaze/config.h b/include/asm-microblaze/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-microblaze/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-mips/config.h b/include/asm-mips/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-mips/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-nios/config.h b/include/asm-nios/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-nios/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-nios2/config.h b/include/asm-nios2/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-nios2/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h new file mode 100644 index 000000000..275a7c828 --- /dev/null +++ b/include/asm-ppc/config.h @@ -0,0 +1,32 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#ifndef CONFIG_MAX_MEM_MAPPED +#if defined(CONFIG_4xx) || defined(CONFIG_E500) +#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#else +#define CONFIG_MAX_MEM_MAPPED (256 << 20) +#endif +#endif + +#endif diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index 05db0de8f..bfef4dfd6 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -88,39 +88,4 @@ #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */ #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */ - -/* BAT (block address translation */ -#define BATU_BEPI_MSK 0xfffe0000 -#define BATU_BL_MSK 0x00001ffc - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 - -#define BATL_BRPN_MSK 0xfffe0000 -#define BATL_WIMG_MSK 0x00000078 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - #endif /* __E300_H__ */ diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index b213af35e..6e3b2559c 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -51,6 +51,23 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define FSL_DDR_BANK_INTERLEAVING 0x2 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 +/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration + */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_BI 0x00000001 + /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { struct { diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h index 5bba08d44..e06a1a6e0 100644 --- a/include/asm-ppc/fsl_law.h +++ b/include/asm-ppc/fsl_law.h @@ -42,7 +42,7 @@ enum law_trgt_if { #ifndef CONFIG_MPC8641 LAW_TRGT_IF_PCIE_1 = 0x02, #endif -#ifndef CONFIG_MPC8572 +#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) LAW_TRGT_IF_PCIE_3 = 0x03, #endif LAW_TRGT_IF_LBC = 0x04, @@ -61,7 +61,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI #endif -#ifdef CONFIG_MPC8572 +#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI #endif diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index cd9094519..808786985 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -415,7 +415,25 @@ typedef struct ioctrl512x { * IIM */ typedef struct iim512x { - u8 fixme[0x1000]; + u32 stat; /* IIM status register */ + u32 statm; /* IIM status IRQ mask */ + u32 err; /* IIM errors register */ + u32 emask; /* IIM error IRQ mask */ + u32 fctl; /* IIM fuse control register */ + u32 ua; /* IIM upper address register */ + u32 la; /* IIM lower address register */ + u32 sdat; /* IIM explicit sense data */ + u8 res0[0x08]; + u32 prg_p; /* IIM program protection register */ + u8 res1[0x10]; + u32 divide; /* IIM divide factor register */ + u8 res2[0x7c0]; + u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */ + u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */ + u8 res3[0x380]; + u32 fbac1; /* IIM fuse bank 1 protection */ + u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */ + u8 res4[0x380]; } iim512x_t; /* @@ -451,7 +469,34 @@ typedef struct lpc512x { * PATA */ typedef struct pata512x { - u8 fixme[0x100]; + /* LOCAL Registers */ + u32 pata_time1; /* Time register 1: PIO and tx timing parameter */ + u32 pata_time2; /* Time register 2: PIO timing parameter */ + u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */ + u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */ + u32 pata_time5; /* Time register 5: UDMA timing parameter */ + u32 pata_time6; /* Time register 6: UDMA timing parameter */ + u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */ + u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */ + u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/ + u32 pata_ata_control; /* ATA Interface control register */ + u32 pata_irq_pending; /* Interrupt pending register (READONLY) */ + u32 pata_irq_enable; /* Interrupt enable register */ + u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/ + u32 pata_fifo_alarm; /* fifo alarm threshold */ + u32 res1[0x1A]; + /* DRIVE Registers */ + u32 pata_drive_data; /* drive data register*/ + u32 pata_drive_features;/* drive features register */ + u32 pata_drive_sectcnt; /* drive sector count register */ + u32 pata_drive_sectnum; /* drive sector number register */ + u32 pata_drive_cyllow; /* drive cylinder low register */ + u32 pata_drive_cylhigh; /* drive cylinder high register */ + u32 pata_drive_dev_head;/* drive device head register */ + u32 pata_drive_command; /* write = drive command, read = drive status reg */ + u32 res2[0x06]; + u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */ + u32 res3[0x09]; } pata512x_t; /* diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 77c09db6b..7b847f802 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -895,4 +895,6 @@ typedef struct immap { } immap_t; #endif +#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) +#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index e5046bef3..7b97fe0bd 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -58,7 +58,23 @@ typedef struct ccsr_local_ecm { uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ char res19[4]; uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */ + char res19_8a[20]; + uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ + char res19_8b[4]; + uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ + char res19_9a[20]; + uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ + char res19_9b[4]; + uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ + char res19_10a[20]; + uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */ + char res19_10b[4]; + uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */ + char res19_11a[20]; + uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */ + char res19_11b[4]; + uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */ + char res20[652]; uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */ char res21[12]; uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */ @@ -119,7 +135,12 @@ typedef struct ccsr_ddr { uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */ uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */ uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */ - char res8_1b[2672]; + char res8_1b[2456]; + uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */ + uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */ + uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */ + uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */ + char res8_1c[200]; uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ char res8_2[512]; @@ -1593,6 +1614,9 @@ typedef struct ccsr_gur { uint gpindr; /* 0xe0050 - General-purpose input data register */ char res5[12]; uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ +#define MPC85xx_PMUXCR_SD_DATA 0x80000000 +#define MPC85xx_PMUXCR_SDHC_CD 0x40000000 +#define MPC85xx_PMUXCR_SDHC_WP 0x20000000 char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ #define MPC85xx_DEVDISR_PCI1 0x80000000 diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index df28c0f2c..470385ffd 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -1289,22 +1289,35 @@ typedef struct ccsr_gur { uint powmgtcsr; /* 0xe0080 - Power management status and control register */ char res8[12]; uint mcpsumr; /* 0xe0090 - Machine check summary register */ - char res9[12]; + uint rstrscr; /* 0xe0094 - Reset request status and control register */ + char res9[8]; uint pvr; /* 0xe00a0 - Processor version register */ uint svr; /* 0xe00a4 - System version register */ - char res10a[1880]; + char res10a[8]; + uint rstcr; /* 0xe00b0 - Reset control register */ +#define MPC86xx_RSTCR_HRST_REQ 0x00000002 + char res10b[1868]; uint clkdvdr; /* 0xe0800 - Clock Divide register */ - char res10b[1532]; + char res10c[796]; + uint ddr1clkdr; /* 0xe0b20 - DDRC1 Clock Disable register */ + char res10d[4]; + uint ddr2clkdr; /* 0xe0b28 - DDRC2 Clock Disable register */ + char res10e[724]; uint clkocr; /* 0xe0e00 - Clock out select register */ char res11[12]; uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ char res12[12]; uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ - int res13[57]; - uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ - int res14[6]; - uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ - char res15[216]; + char res13a[224]; + uint srds1cr0; /* 0xe0f04 - SerDes1 control register 0 */ + char res13b[4]; + uint srds1cr1; /* 0xe0f08 - SerDes1 control register 1 */ + char res14[24]; + uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ + char res15a[24]; + uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */ + uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */ + char res16[184]; } ccsr_gur_t; /* diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 6d942d083..fa92b90c3 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -138,6 +138,10 @@ typedef struct _MMU_context { extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ extern void _tlbia(void); /* invalidate all TLB entries */ +#ifdef CONFIG_ADDR_MAP +extern void init_addr_map(void); +#endif + typedef enum { IBAT0 = 0, IBAT1, IBAT2, IBAT3, DBAT0, DBAT1, DBAT2, DBAT3, @@ -153,25 +157,64 @@ extern void print_bats(void); #endif /* __ASSEMBLY__ */ -/* Block size masks */ -#define BL_128K 0x000 -#define BL_256K 0x001 -#define BL_512K 0x003 -#define BL_1M 0x007 -#define BL_2M 0x00F -#define BL_4M 0x01F -#define BL_8M 0x03F -#define BL_16M 0x07F -#define BL_32M 0x0FF -#define BL_64M 0x1FF -#define BL_128M 0x3FF -#define BL_256M 0x7FF +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 +#define BATU_INVALID 0x00000000 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_NO_ACCESS 0x00000000 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#define BATL_PP_NO_ACCESS BATL_PP_00 +#define BATL_PP_RO BATL_PP_01 +#define BATL_PP_RW BATL_PP_10 + +/* BAT Block size values */ +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc + +/* Block lengths for processors that support extended block length */ +#ifdef HID0_XBSEN +#define BATU_BL_512M 0x00003ffc +#define BATU_BL_1G 0x00007ffc +#define BATU_BL_2G 0x0000fffc +#define BATU_BL_4G 0x0001fffc +#define BATU_BL_MAX BATU_BL_4G +#else +#define BATU_BL_MAX BATU_BL_256M +#endif /* BAT Access Protection */ #define BPP_XX 0x00 /* No access */ #define BPP_RX 0x01 /* Read only */ #define BPP_RW 0x02 /* Read/write */ +/* Macros to get values from BATs, once data is in the BAT register format */ +#define BATU_VALID(x) (x & 0x3) +#define BATU_VADDR(x) (x & 0xfffe0000) +#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \ + | ((x & 0x0e00ULL) << 24) \ + | ((x & 0x04ULL) << 30))) +#define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17)) + /* Used to set up SDR1 register */ #define HASH_TABLE_SIZE_64K 0x00010000 #define HASH_TABLE_SIZE_128K 0x00020000 @@ -431,9 +474,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn, extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); -#ifdef CONFIG_ADDR_MAP -extern void init_addr_map(void); -#endif + extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 98faced36..992a3d221 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -566,6 +566,8 @@ #define SDRAM_RDCC_RSAE_MASK 0x00000001 #define SDRAM_RDCC_RSAE_DISABLE 0x00000001 #define SDRAM_RDCC_RSAE_ENABLE 0x00000000 +#define SDRAM_RDCC_RDSS_ENCODE(n) ((((u32)(n))&0x03)<<30) +#define SDRAM_RDCC_RDSS_DECODE(n) ((((u32)(n))>>30)&0x03) /* * SDRAM Read Feedback Delay Control Register diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index e07e5d3be..5b29de0fd 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -451,6 +451,8 @@ #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ +#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ +#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ @@ -777,6 +779,13 @@ #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ +/* e600 core PVR fields */ + +#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ +#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ +#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ +#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ + /* Processor Version Numbers */ #define PVR_403GA 0x00200000 @@ -857,7 +866,6 @@ #define PVR_85xx_REV2 (PVR_85xx | 0x0020) #define PVR_86xx 0x80040000 -#define PVR_86xx_REV1 (PVR_86xx | 0x0010) #define PVR_VIRTEX5 0x7ff21912 @@ -949,6 +957,8 @@ #define SVR_8568_E 0x807D00 #define SVR_8572 0x80E000 #define SVR_8572_E 0x80E800 +#define SVR_P2020 0x80E200 +#define SVR_P2020_E 0x80EA00 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 diff --git a/include/asm-sh/config.h b/include/asm-sh/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-sh/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-sparc/config.h b/include/asm-sparc/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-sparc/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index d771696fe..205dd1f65 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -33,7 +33,7 @@ #define CONFIG_CMD_ECHO /* echo arguments */ #define CONFIG_CMD_EEPROM /* EEPROM read/write support */ #define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */ -#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_FDC /* Floppy Disk Support */ diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h index b556706c7..366760289 100644 --- a/include/config_cmd_default.h +++ b/include/config_cmd_default.h @@ -21,11 +21,13 @@ #define CONFIG_CMD_BOOTD /* bootd */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_ECHO /* echo arguments */ -#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_FLASH /* flinfo, erase, protect */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ #define CONFIG_CMD_IMI /* iminfo */ +#ifndef CONFIG_SYS_NO_FLASH #define CONFIG_CMD_IMLS /* List all found images */ +#endif #define CONFIG_CMD_ITEST /* Integer (and string) test */ #define CONFIG_CMD_LOADB /* loadb */ #define CONFIG_CMD_LOADS /* loads */ diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 28be8dd62..bced118e3 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -396,10 +396,11 @@ /* * Ethernet configuration * - * Define CONFIG_FEC10MBIT to force FEC at 10MBIT + * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT */ #define CONFIG_MPC5xxx_FEC 1 -#undef CONFIG_FEC_10MBIT +#define CONFIG_MPC5xxx_FEC_MII100 +#undef CONFIG_MPC5xxx_MII10 #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index f1608e145..527c84650 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -86,7 +86,7 @@ #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_CONSOLE #define CONFIG_CMD_ASKENV #define CONFIG_CMD_ECHO diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 63a0d3d6a..53bd0d87c 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -170,7 +170,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_DHCP #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IRQ diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 36e1f8173..9e9a8a4ab 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -170,7 +170,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_DHCP #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IRQ diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 1b766a7dc..201e62aa0 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -114,7 +114,7 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_IRQ -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h index 1ef806796..d8312384d 100644 --- a/include/configs/FLAGADM.h +++ b/include/configs/FLAGADM.h @@ -83,7 +83,7 @@ #define CONFIG_CMD_FLASH #define CONFIG_CMD_LOADB #define CONFIG_CMD_LOADS -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_REGINFO #define CONFIG_CMD_IMMAP #define CONFIG_CMD_NET diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index f8c94ec2c..5ef0b7798 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -293,14 +293,12 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 -#if defined(CONFIG_LITE5200B) -#define CONFIG_FEC_MII100 1 -#endif /* * GPIO configuration diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 7ddeb550b..50b3ab280 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -82,7 +82,10 @@ #define CONFIG_CMD_MISC #undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADB +#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */ +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC @@ -116,7 +119,7 @@ #define CONFIG_SYS_I2C_OFFSET 0x00000300 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ #define CONFIG_BOOTFILE "u-boot.bin" #ifdef CONFIG_MCFFEC # define CONFIG_NET_RETRY_COUNT 5 @@ -128,16 +131,16 @@ # define CONFIG_OVERWRITE_ETHADDR_ONCE #endif /* FEC_ENET */ -#define CONFIG_HOSTNAME M5235EVB +#define CONFIG_HOSTNAME M5271EVB #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp $loadaddr $uboot\0" \ "upd=run load; run prog\0" \ - "prog=prot off ffe00000 ffe2ffff;" \ - "era ffe00000 ffe2ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b $loadaddr ffe00000 $filesize;" \ "save\0" \ "" @@ -159,7 +162,17 @@ #define CONFIG_SYS_MEMTEST_END 0x380000 #define CONFIG_SYS_HZ 1000000 + +/* Clock configuration + * The external oscillator is a 25.000 MHz + * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk) + * bus_clk = (cpu_clk/2) (fixed ratio) + * + * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to + * match the new clock speed. Max cpu_clk is 150 MHz. + */ #define CONFIG_SYS_CLK 100000000 +#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1) /* * Low Level Configuration Settings @@ -216,7 +229,14 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 -/* Port configuration */ -#define CONFIG_SYS_FECI2C 0xF0 +/* Chip Select 0 : Boot Flash */ +#define CONFIG_SYS_CS0_BASE 0xFFE00000 +#define CONFIG_SYS_CS0_MASK 0x001F0001 +#define CONFIG_SYS_CS0_CTRL 0x00001980 + +/* Chip Select 1 : External SRAM */ +#define CONFIG_SYS_CS1_BASE 0x30000000 +#define CONFIG_SYS_CS1_MASK 0x00070001 +#define CONFIG_SYS_CS1_CTRL 0x00001900 #endif /* _M5271EVB_H */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 58a26e117..0ef4ebaec 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -430,7 +430,7 @@ #define CONFIG_CMD_PCI #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index a04868ec6..9fa91f4f6 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -434,7 +434,7 @@ #define CONFIG_CMD_PCI #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index c6ac91a53..4eab28571 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -427,7 +427,7 @@ #define CONFIG_CMD_PCI #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index bc56e682a..ea1928eae 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -8,7 +8,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -441,7 +441,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 8e82aac7b..b3c0e2dd5 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -509,7 +509,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index fbd2457aa..bdd6b87ad 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -470,7 +470,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index c20f86aa2..f7ebdaad7 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -376,7 +376,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 0dd6ef52f..a62d805a9 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -319,6 +319,9 @@ #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 +#define CONFIG_SYS_64BIT_VSPRINTF 1 + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ @@ -494,7 +497,7 @@ extern int board_pci_host_broken(void); #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif @@ -502,6 +505,18 @@ extern int board_pci_host_broken(void); #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* * Miscellaneous configurable options */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index f281c59d3..2e31dd00a 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -481,7 +481,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index e379d5327..bbb448d55 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -72,6 +72,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + #define CONFIG_ENABLE_36BIT_PHYS 1 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ @@ -528,6 +530,18 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* * Miscellaneous configurable options */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 0d03b0b85..4aaad55b5 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -423,7 +423,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 5ac1916cb..95ea27583 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -300,7 +300,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 3f78a6e12..a41f50a17 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -457,7 +457,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index ac0a4641e..b60b3641f 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -103,6 +103,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* DDR Setup */ #define CONFIG_SYS_DDR_TLB_START 9 +#define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ @@ -403,10 +404,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 3, direct to uli, tgtid 3, Base address 8000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 #ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull #else +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ @@ -421,10 +423,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ @@ -439,10 +442,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull #else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 4bd3e0bd3..1091043c0 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -34,8 +34,6 @@ #define CONFIG_SYS_DIAG_ADDR 0xff800000 #endif -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 - /* * virtual address to be used for temporary mappings. There * should be 128k free at this VA. @@ -491,7 +489,7 @@ #define CONFIG_CMD_MII #if defined(CONFIG_SYS_RAMBOOT) -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #endif #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 5a832961c..9d661010d 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -39,13 +39,12 @@ #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ +#define CONFIG_ADDR_MAP 1 /* Use addr map */ #ifdef RUN_DIAG #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 - /* * virtual address to be used for temporary mappings. There * should be 128k free at this VA. @@ -70,6 +69,7 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ +#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ #define CONFIG_ALTIVEC 1 @@ -186,7 +186,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ | CONFIG_SYS_PHYS_ADDR_HIGH) -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | 0x00001001) /* port size 16bit */ @@ -331,14 +331,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 + +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL #else -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_VIRT #endif #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \ | CONFIG_SYS_PHYS_ADDR_HIGH) @@ -348,12 +351,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) #define _IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \ +#ifdef CONFIG_PHYS_64BIT +/* + * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT. + * This will increase the amount of PCI address space available for + * for mapping RAM. + */ +#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI1_MEM_BUS +#else +#define CONFIG_SYS_PCI2_MEM_BUS (CONFIG_SYS_PCI1_MEM_BUS \ + + CONFIG_SYS_PCI1_MEM_SIZE) +#endif +#define CONFIG_SYS_PCI2_MEM_VIRT (CONFIG_SYS_PCI1_MEM_VIRT \ + CONFIG_SYS_PCI1_MEM_SIZE) #define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \ + CONFIG_SYS_PCI1_MEM_SIZE) #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \ + CONFIG_SYS_PCI1_IO_SIZE) #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ @@ -501,7 +515,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \ +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \ | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT) @@ -635,7 +649,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_REGINFO #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #endif #if defined(CONFIG_PCI) diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h index 31b9f038b..79c20696f 100644 --- a/include/configs/MVBLUE.h +++ b/include/configs/MVBLUE.h @@ -85,7 +85,7 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IRQ diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h index b03612797..10210f040 100644 --- a/include/configs/MVS1.h +++ b/include/configs/MVS1.h @@ -92,7 +92,7 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_BOOTD #define CONFIG_CMD_RUN diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index e171f76b5..c9589bd87 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -40,7 +40,7 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/PATI.h b/include/configs/PATI.h index 9d80ce413..88e952895 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -57,7 +57,7 @@ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_FLASH #define CONFIG_CMD_LOADS -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_REGINFO #define CONFIG_CMD_BDI #define CONFIG_CMD_CONSOLE diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index 481e3354b..831a60d9a 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -137,7 +137,7 @@ */ #define CONFIG_CMD_BDI #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IRQ diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index 5b1fcff9c..522349f78 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -177,7 +177,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_DHCP #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IRQ diff --git a/include/configs/PM520.h b/include/configs/PM520.h index e250e0338..ff73ef9a2 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -279,10 +279,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 41e290d0b..3f943aa43 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -331,7 +331,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 6b4e2dd42..43c2873e3 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -330,7 +330,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/PN62.h b/include/configs/PN62.h index 2c0774fea..06c11e69b 100644 --- a/include/configs/PN62.h +++ b/include/configs/PN62.h @@ -61,7 +61,7 @@ #undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS diff --git a/include/configs/QS823.h b/include/configs/QS823.h index 4ac31b1c0..c1416cb91 100644 --- a/include/configs/QS823.h +++ b/include/configs/QS823.h @@ -211,7 +211,7 @@ #define CONFIG_CMD_BOOTD #define CONFIG_CMD_CONSOLE #define CONFIG_CMD_DATE -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IMMAP diff --git a/include/configs/QS850.h b/include/configs/QS850.h index 65f41e6a7..de74fee76 100644 --- a/include/configs/QS850.h +++ b/include/configs/QS850.h @@ -211,7 +211,7 @@ #define CONFIG_CMD_BOOTD #define CONFIG_CMD_CONSOLE #define CONFIG_CMD_DATE -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IMMAP diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 34196319c..7239f8409 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -382,7 +382,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index a616236b7..b939cfa79 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -205,6 +205,9 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} @@ -332,7 +335,7 @@ #define CONFIG_CMD_JFFS2 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h index d4154d205..4181a400e 100644 --- a/include/configs/SPD823TS.h +++ b/include/configs/SPD823TS.h @@ -67,7 +67,7 @@ #define CONFIG_CMD_IDE -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_FLASH diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 60102469c..b42d3d944 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -344,10 +344,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index 046948e74..50197f4c5 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -312,7 +312,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ +#define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */ #define CONFIG_PHY_ADDR 0x1f #define CONFIG_PHY_TYPE 0x79c874 /* diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index db7f51d4e..6850eba15 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -507,10 +507,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index ac9c94e68..582e67025 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -81,8 +81,8 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ "bootfile=tqm8260/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40200000\0" \ + "kernel_addr=400C0000\0" \ + "ramdisk_addr=40240000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 796030d06..e126dc38c 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -340,7 +340,7 @@ extern int tqm834x_num_flash_banks; #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index f5831ebaf..3b2272c23 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -41,14 +41,21 @@ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ +#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) +#define CONFIG_TQM8548 +#endif + #define CONFIG_PCI +#ifndef CONFIG_TQM8548_AG +#define CONFIG_PCI1 /* PCI/PCI-X controller */ +#endif +#ifdef CONFIG_TQM8548 +#define CONFIG_PCIE1 /* PCI Express interface */ +#endif + #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */ -#ifdef CONFIG_TQM8548 -#define CONFIG_PCI1 -#define CONFIG_PCIE1 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#endif #define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -70,7 +77,9 @@ * Warning: NAND support will likely increase the U-Boot image size * to more than 256 KB. Please adjust TEXT_BASE if necessary. */ -#undef CONFIG_NAND +#ifdef CONFIG_TQM8548_BE +#define CONFIG_NAND +#endif /* * MPC8540 and MPC8548 don't have CPM module @@ -81,7 +90,9 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#undef CONFIG_CAN_DRIVER /* CAN Driver support */ +#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) +#define CONFIG_CAN_DRIVER /* CAN Driver support */ +#endif /* * sysclk for MPC85xx @@ -135,6 +146,9 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#ifdef CONFIG_TQM8548_AG +#define CONFIG_VERY_BIG_RAM +#endif #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 @@ -604,7 +618,9 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#ifndef CONFIG_TQM8548_AG #define CONFIG_CMD_DATE +#endif #define CONFIG_CMD_EEPROM #define CONFIG_CMD_DTT #define CONFIG_CMD_MII diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 75d1985ff..9a7584807 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -268,6 +268,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_SEVENWIRE /* dummy, 7-wire FEC does not have phy address */ #define CONFIG_PHY_ADDR 0x00 diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h index 982f8d801..5f9a17f3d 100644 --- a/include/configs/VoVPN-GW.h +++ b/include/configs/VoVPN-GW.h @@ -154,7 +154,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_CONSOLE #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IMLS diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index 1df6855cc..370aae1c4 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -330,7 +330,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_I2C #define CONFIG_CMD_JFFS2 diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 3bc0fe8f6..a353a14e7 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -375,7 +375,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_DTT #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_I2C #define CONFIG_CMD_JFFS2 diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index bb3525f17..8fda3f29f 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -47,6 +47,7 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ +#undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */ /* video */ #undef CONFIG_VIDEO @@ -294,6 +295,11 @@ #endif /* + * IIM - IC Identification Module + */ +#undef CONFIG_IIM + +/* * EEPROM configuration */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ @@ -348,11 +354,20 @@ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_EEPROM #define CONFIG_CMD_DATE +#undef CONFIG_CMD_FUSE +#define CONFIG_CMD_IDE +#define CONFIG_CMD_EXT2 #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif +#if defined(CONFIG_CMD_IDE) +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION +#endif /* defined(CONFIG_CMD_IDE) */ + /* * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set @@ -489,4 +504,48 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc@80000000/serial@11300" +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for IDE not supported */ + +#define CONFIG_IDE_RESET /* reset for IDE supported */ +#define CONFIG_IDE_PREINIT + +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ + +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_BASE_ADDR MPC512X_PATA + +/* Offset for data I/O RefMan MPC5121EE Table 28-10 */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) + +/* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) + +/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ +#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) + +/* Interval between registers */ +#define CONFIG_SYS_ATA_STRIDE 4 + +#define ATA_BASE_ADDR MPC512X_PATA + +/* + * Control register bit definitions + */ +#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 +#define FSL_ATA_CTRL_ATA_RST_B 0x40000000 +#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 +#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 +#define FSL_ATA_CTRL_DMA_PENDING 0x08000000 +#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 +#define FSL_ATA_CTRL_DMA_WRITE 0x02000000 +#define FSL_ATA_CTRL_IORDY_EN 0x01000000 + #endif /* __CONFIG_H */ diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h index 9134ad1dc..c6d77e3ae 100644 --- a/include/configs/ap325rxa.h +++ b/include/configs/ap325rxa.h @@ -40,7 +40,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_NFS #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_IDE #define CONFIG_CMD_EXT2 #define CONFIG_DOS_PARTITION diff --git a/include/configs/canmb.h b/include/configs/canmb.h index ff7b6e5ca..1f275e5db 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -173,6 +173,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x0 /* * GPIO configuration: diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h index cfe6de79f..ce36a2426 100644 --- a/include/configs/cm4008.h +++ b/include/configs/cm4008.h @@ -73,7 +73,7 @@ */ #include <config_cmd_default.h> -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #define CONFIG_BOOTDELAY 0 diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h index 5454c2e5b..02cb1efd0 100644 --- a/include/configs/cm41xx.h +++ b/include/configs/cm41xx.h @@ -73,7 +73,7 @@ */ #include <config_cmd_default.h> -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #define CONFIG_BOOTDELAY 0 diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index 620ffea08..ddcc6aad4 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -65,6 +65,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x00 #define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ /* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index fa70a09f6..c3c603b42 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -69,7 +69,7 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_BDI #define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_RUN #define CONFIG_CMD_IMI diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index b9dabac98..52df16af1 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -259,6 +259,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* * Define CONFIG_FEC_10MBIT to force FEC at 10Mb */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h index a24e34a50..15635288e 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -78,7 +78,7 @@ #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_RUN #define CONFIG_CMD_ASKENV #define CONFIG_CMD_ECHO diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index a578038b5..b439c80d4 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -97,7 +97,7 @@ #undef CONFIG_CMD_BDI #undef CONFIG_CMD_BEDBUG #undef CONFIG_CMD_ELF -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_FAT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_MII diff --git a/include/configs/delta.h b/include/configs/delta.h index abb2676bc..8cbeb9a5e 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -108,7 +108,7 @@ #else -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NAND #define CONFIG_CMD_I2C diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 8f9e97245..447c7bc87 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -75,7 +75,7 @@ #define CONFIG_CMD_BOOTD /* bootd */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_ECHO /* echo arguments */ -#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_FLASH /* flinfo, erase, protect */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ #define CONFIG_CMD_IMI /* iminfo */ diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h index fc3174c63..85bf236c6 100644 --- a/include/configs/eXalion.h +++ b/include/configs/eXalion.h @@ -77,7 +77,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE #define CONFIG_CMD_FAT -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_PCI diff --git a/include/configs/gth2.h b/include/configs/gth2.h index aeede0466..b1b4842e0 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -90,7 +90,7 @@ #define CONFIG_CMD_IDE #define CONFIG_CMD_DHCP -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_FAT #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_FPGA diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index 16b06cd8b..a81527ebe 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -215,6 +215,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x00 #define CONFIG_MII 1 /* MII PHY management */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 405234cc8..e42fa6dcc 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -221,10 +221,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 #define CONFIG_MII diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 1b05b8058..45e22bfc4 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -73,7 +73,7 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_I2C #define CONFIG_CMD_IMI diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 1a70af620..5b4747a57 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -85,7 +85,7 @@ */ #define CONFIG_CMD_BDI #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_MEMORY diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 2ebe37057..9c45acf88 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -239,10 +239,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/katmai.h b/include/configs/katmai.h index ea6cf0d23..0d89594f2 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -45,7 +45,6 @@ */ #define CONFIG_PHYS_64BIT #define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) /* * Include common defines/options for all AMCC eval boards diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 4d3ccf568..26cb85439 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -234,16 +234,9 @@ * * DDR Autocalibration Method_B is the default. */ -#if 0 -/* - * Needs FIX!!! - * Disable autocalibration for now, because of the unresolved problem - * with kilauea board using 200MHz PLB/DDR2 frequency - */ #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ #undef CONFIG_PPC4xx_DDR_METHOD_A -#endif #define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 25b1c172e..b86c61d5f 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -305,7 +305,7 @@ #endif #if defined(CFG_RAMBOOT) -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/logodl.h b/include/configs/logodl.h index bb6f943ae..8644cb08a 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -69,7 +69,7 @@ */ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY #define CONFIG_CMD_RUN diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h index eab37df22..a43285051 100644 --- a/include/configs/m501sk.h +++ b/include/configs/m501sk.h @@ -154,7 +154,7 @@ #define CONFIG_CMD_IMI #define CONFIG_CMD_NFS #define CONFIG_CMD_FLASH -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_SYS_HUSH_PARSER #define CONFIG_AUTO_COMPLETE diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index e64cc3704..e5812ee8a 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -271,11 +271,12 @@ /* * Ethernet configuration */ -/*#define CONFIG_MPC5xxx_FEC 1*/ +/* #define CONFIG_MPC5xxx_FEC 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII100 */ /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 1 /* diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 7ef5bdfd9..4a93b5888 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -243,10 +243,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 #define CONFIG_UDP_CHECKSUM 1 diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 233bee002..b5d12c693 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -64,6 +64,7 @@ #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ #undef CONFIG_ETHER_NONE /* No external Ethernet */ +#define CONFIG_NET_MULTI 1 #define CONFIG_ETHER_INDEX 4 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000 diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 4c6cc9fef..ac18c8776 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -248,7 +248,7 @@ #define CONFIG_CMD_JFFS2 #if !defined(RAMENV) - #define CONFIG_CMD_ENV + #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SAVES #endif #else diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index b3f16d5e7..e6e3729a2 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -82,6 +82,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x2 #define CONFIG_PHY_TYPE 0x79c874 #define CONFIG_RESET_PHY_R 1 diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 483bc5305..a1783b200 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -163,7 +163,7 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_EEPROM #define CONFIG_CMD_FLASH -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_BSP #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h index 6ebb1e17b..86f6a934f 100644 --- a/include/configs/mpr2.h +++ b/include/configs/mpr2.h @@ -27,7 +27,7 @@ #define __MPR2_H /* Supported commands */ -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_CACHE #define CONFIG_CMD_MEMORY #define CONFIG_CMD_FLASH diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h index 520bac074..9a88ec7fa 100644 --- a/include/configs/ms7720se.h +++ b/include/configs/ms7720se.h @@ -31,7 +31,7 @@ #define CONFIG_MS7720SE 1 #define CONFIG_CMD_FLASH -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SDRAM #define CONFIG_CMD_MEMORY #define CONFIG_CMD_CACHE diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 52020047d..53ffbeef2 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -38,7 +38,7 @@ #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM #define CONFIG_CMD_MEMORY -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index af9933cad..5eed3ab66 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -40,7 +40,7 @@ #define CONFIG_CMD_DFL #define CONFIG_CMD_FLASH -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_SCIF_CONSOLE 1 #define CONFIG_BAUDRATE 38400 diff --git a/include/configs/mucmc52.h b/include/configs/mucmc52.h index 2f48a0f25..ae60cd221 100644 --- a/include/configs/mucmc52.h +++ b/include/configs/mucmc52.h @@ -225,6 +225,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x00 #define CONFIG_MII 1 /* MII PHY management */ diff --git a/include/configs/munices.h b/include/configs/munices.h index 7682faa32..fa5230f52 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -166,6 +166,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x01 #define CONFIG_MII 1 diff --git a/include/configs/netstar.h b/include/configs/netstar.h index fab22d16a..2c90265e3 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -140,7 +140,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_BOOTD #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_JFFS2 diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index bfae7b429..18e7cc2a9 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -233,10 +233,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 7c7bebac3..5ad745e64 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -198,7 +198,7 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_FAT #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_FPGA diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index b2e2a1c4a..8ca55d78e 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -245,10 +245,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 #define CONFIG_UDP_CHECKSUM 1 diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h index 577ab8ef6..0fd863568 100644 --- a/include/configs/ppmc7xx.h +++ b/include/configs/ppmc7xx.h @@ -83,7 +83,7 @@ #include <config_cmd_default.h> #define CONFIG_CMD_FLASH -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_RUN #define CONFIG_CMD_ELF #define CONFIG_CMD_NET diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index f85d5d669..72a3b5c8b 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -43,7 +43,7 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_NET #define CONFIG_CMD_PING -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NFS #define CONFIG_CMD_IDE #define CONFIG_CMD_EXT2 diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h index f88a77340..36e4c017b 100644 --- a/include/configs/rsk7203.h +++ b/include/configs/rsk7203.h @@ -37,7 +37,7 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_NFS #define CONFIG_CMD_PING -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SDRAM #define CONFIG_CMD_MEMORY #define CONFIG_CMD_CACHE diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h index d19a787e9..1cc2920b3 100644 --- a/include/configs/sbc8240.h +++ b/include/configs/sbc8240.h @@ -96,7 +96,7 @@ #define CONFIG_CMD_BSP #define CONFIG_CMD_DIAG #define CONFIG_CMD_ELF -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_PCI #define CONFIG_CMD_PING diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 0603e3c8a..f476e3ed5 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -455,7 +455,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index d4e9d7479..4fa501da5 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -380,7 +380,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index 4ea79cf33..8d7456eb6 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -40,7 +40,7 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET #define CONFIG_CMD_PING -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NFS #define CONFIG_CMD_JFFS2 diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h index ebca448ea..537ec4eca 100644 --- a/include/configs/sh7785lcr.h +++ b/include/configs/sh7785lcr.h @@ -40,7 +40,7 @@ #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM #define CONFIG_CMD_RUN -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index c61667fd0..06d6a8859 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -104,7 +104,7 @@ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_LOADS #define CONFIG_CMD_LOADB -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NAND #if defined(CONFIG_BOOT_ONENAND) #define CONFIG_CMD_ONENAND diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index ae6f45aee..0424e2978 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -322,7 +322,7 @@ #define CONFIG_CMD_I2C #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #else #define CONFIG_CMD_ELF diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index c312f1af9..2783f9e04 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -363,7 +363,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #else #define CONFIG_CMD_ELF diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h index b702de0c5..353e8db42 100644 --- a/include/configs/suzaku.h +++ b/include/configs/suzaku.h @@ -62,7 +62,7 @@ #include <config_cmd_default.h> #undef CONFIG_CMD_BDI -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_MEMORY #undef CONFIG_CMD_NET #undef CONFIG_CMD_MISC diff --git a/include/configs/uc101.h b/include/configs/uc101.h index 553eb25fb..87cb4e508 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -233,6 +233,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x00 #define CONFIG_MII 1 diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h index 6e9c27c1e..1a47aadcf 100644 --- a/include/configs/utx8245.h +++ b/include/configs/utx8245.h @@ -105,7 +105,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}" #define CONFIG_CMD_PCI #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_CONSOLE #define CONFIG_CMD_LOADS #define CONFIG_CMD_LOADB diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 0156ce1c1..fc7128e73 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -247,6 +247,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x00 #define CONFIG_MII 1 diff --git a/include/configs/versatile.h b/include/configs/versatile.h index d81242165..852becb36 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -108,7 +108,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_MEMORY #define CONFIG_CMD_FLASH -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV /* diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h index 866b72d4c..f4606102a 100644 --- a/include/configs/voiceblue.h +++ b/include/configs/voiceblue.h @@ -127,7 +127,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_BOOTD #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_JFFS2 diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index f30eca1d2..31ea4ca31 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -94,7 +94,7 @@ #ifdef TURN_ON_ETHERNET #define CONFIG_CMD_PING #else - #define CONFIG_CMD_ENV + #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NAND #undef CONFIG_CMD_NET diff --git a/include/flash.h b/include/flash.h index 6e2981c5a..8b8979e2f 100644 --- a/include/flash.h +++ b/include/flash.h @@ -33,7 +33,7 @@ typedef struct { ulong size; /* total bank size in bytes */ ushort sector_count; /* number of erase units */ ulong flash_id; /* combined device & manufacturer code */ - ulong start[CONFIG_SYS_MAX_FLASH_SECT]; /* physical sector start addresses */ + ulong start[CONFIG_SYS_MAX_FLASH_SECT]; /* virtual sector start address */ uchar protect[CONFIG_SYS_MAX_FLASH_SECT]; /* sector protection status */ #ifdef CONFIG_SYS_FLASH_CFI uchar portwidth; /* the width of the port */ @@ -124,6 +124,9 @@ extern int jedec_flash_match(flash_info_t *info, ulong base); #define CFI_CMDSET_AMD_LEGACY 0xFFF0 #endif +#if defined(CONFIG_SYS_FLASH_CFI) +extern flash_info_t *flash_get_info(ulong base); +#endif /*----------------------------------------------------------------------- * return codes from flash_write(): diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h new file mode 100644 index 000000000..0a5c5d626 --- /dev/null +++ b/include/fsl_esdhc.h @@ -0,0 +1,145 @@ +/* + * FSL SD/MMC Defines + *------------------------------------------------------------------- + * + * Copyright 2007-2008, Freescale Semiconductor, Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + *------------------------------------------------------------------- + * + */ + +#ifndef __FSL_ESDHC_H__ +#define __FSL_ESDHC_H__ + +/* FSL eSDHC-specific constants */ +#define SYSCTL 0x0002e02c +#define SYSCTL_INITA 0x08000000 +#define SYSCTL_TIMEOUT_MASK 0x000f0000 +#define SYSCTL_CLOCK_MASK 0x00000fff +#define SYSCTL_PEREN 0x00000004 +#define SYSCTL_HCKEN 0x00000002 +#define SYSCTL_IPGEN 0x00000001 + +#define IRQSTAT 0x0002e030 +#define IRQSTAT_DMAE (0x10000000) +#define IRQSTAT_AC12E (0x01000000) +#define IRQSTAT_DEBE (0x00400000) +#define IRQSTAT_DCE (0x00200000) +#define IRQSTAT_DTOE (0x00100000) +#define IRQSTAT_CIE (0x00080000) +#define IRQSTAT_CEBE (0x00040000) +#define IRQSTAT_CCE (0x00020000) +#define IRQSTAT_CTOE (0x00010000) +#define IRQSTAT_CINT (0x00000100) +#define IRQSTAT_CRM (0x00000080) +#define IRQSTAT_CINS (0x00000040) +#define IRQSTAT_BRR (0x00000020) +#define IRQSTAT_BWR (0x00000010) +#define IRQSTAT_DINT (0x00000008) +#define IRQSTAT_BGE (0x00000004) +#define IRQSTAT_TC (0x00000002) +#define IRQSTAT_CC (0x00000001) + +#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE) +#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE) + +#define IRQSTATEN 0x0002e034 +#define IRQSTATEN_DMAE (0x10000000) +#define IRQSTATEN_AC12E (0x01000000) +#define IRQSTATEN_DEBE (0x00400000) +#define IRQSTATEN_DCE (0x00200000) +#define IRQSTATEN_DTOE (0x00100000) +#define IRQSTATEN_CIE (0x00080000) +#define IRQSTATEN_CEBE (0x00040000) +#define IRQSTATEN_CCE (0x00020000) +#define IRQSTATEN_CTOE (0x00010000) +#define IRQSTATEN_CINT (0x00000100) +#define IRQSTATEN_CRM (0x00000080) +#define IRQSTATEN_CINS (0x00000040) +#define IRQSTATEN_BRR (0x00000020) +#define IRQSTATEN_BWR (0x00000010) +#define IRQSTATEN_DINT (0x00000008) +#define IRQSTATEN_BGE (0x00000004) +#define IRQSTATEN_TC (0x00000002) +#define IRQSTATEN_CC (0x00000001) + +#define PRSSTAT 0x0002e024 +#define PRSSTAT_CLSL (0x00800000) +#define PRSSTAT_WPSPL (0x00080000) +#define PRSSTAT_CDPL (0x00040000) +#define PRSSTAT_CINS (0x00010000) +#define PRSSTAT_BREN (0x00000800) +#define PRSSTAT_DLA (0x00000004) +#define PRSSTAT_CICHB (0x00000002) +#define PRSSTAT_CIDHB (0x00000001) + +#define PROCTL 0x0002e028 +#define PROCTL_INIT 0x00000020 +#define PROCTL_DTW_4 0x00000002 +#define PROCTL_DTW_8 0x00000004 + +#define CMDARG 0x0002e008 + +#define XFERTYP 0x0002e00c +#define XFERTYP_CMD(x) ((x & 0x3f) << 24) +#define XFERTYP_CMDTYP_NORMAL 0x0 +#define XFERTYP_CMDTYP_SUSPEND 0x00400000 +#define XFERTYP_CMDTYP_RESUME 0x00800000 +#define XFERTYP_CMDTYP_ABORT 0x00c00000 +#define XFERTYP_DPSEL 0x00200000 +#define XFERTYP_CICEN 0x00100000 +#define XFERTYP_CCCEN 0x00080000 +#define XFERTYP_RSPTYP_NONE 0 +#define XFERTYP_RSPTYP_136 0x00010000 +#define XFERTYP_RSPTYP_48 0x00020000 +#define XFERTYP_RSPTYP_48_BUSY 0x00030000 +#define XFERTYP_MSBSEL 0x00000020 +#define XFERTYP_DTDSEL 0x00000010 +#define XFERTYP_AC12EN 0x00000004 +#define XFERTYP_BCEN 0x00000002 +#define XFERTYP_DMAEN 0x00000001 + +#define CINS_TIMEOUT 1000 + +#define DSADDR 0x2e004 + +#define CMDRSP0 0x2e010 +#define CMDRSP1 0x2e014 +#define CMDRSP2 0x2e018 +#define CMDRSP3 0x2e01c + +#define DATPORT 0x2e020 + +#define WML 0x2e044 +#define WML_WRITE 0x00010000 + +#define BLKATTR 0x2e004 +#define BLKATTR_CNT(x) ((x & 0xffff) << 16) +#define BLKATTR_SIZE(x) (x & 0x1fff) +#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */ + +#define ESDHC_HOSTCAPBLT_VS18 0x04000000 +#define ESDHC_HOSTCAPBLT_VS30 0x02000000 +#define ESDHC_HOSTCAPBLT_VS33 0x01000000 +#define ESDHC_HOSTCAPBLT_SRS 0x00800000 +#define ESDHC_HOSTCAPBLT_DMAS 0x00400000 +#define ESDHC_HOSTCAPBLT_HSS 0x00200000 + +int fsl_esdhc_mmc_init(bd_t *bis); + +#endif /* __FSL_ESDHC_H__ */ diff --git a/include/i2c.h b/include/i2c.h index fad2d5716..f8a59a669 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -159,14 +159,7 @@ static inline u8 i2c_reg_read(u8 addr, u8 reg) printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); #endif -#ifdef CONFIG_BLACKFIN - /* This ifdef will become unneccessary in a future version of the - * blackfin I2C driver. - */ - i2c_read(addr, reg, 0, &buf, 1); -#else i2c_read(addr, reg, 1, &buf, 1); -#endif return buf; } @@ -183,14 +176,7 @@ static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) __func__, addr, reg, val); #endif -#ifdef CONFIG_BLACKFIN - /* This ifdef will become unneccessary in a future version of the - * blackfin I2C driver. - */ - i2c_write(addr, reg, 0, &val, 1); -#else i2c_write(addr, reg, 1, &val, 1); -#endif } /* diff --git a/include/image.h b/include/image.h index 4609200b8..74a124006 100644 --- a/include/image.h +++ b/include/image.h @@ -338,23 +338,23 @@ static inline uint32_t image_get_header_size (void) { \ return uimage_to_cpu (hdr->ih_##f); \ } -image_get_hdr_l (magic); -image_get_hdr_l (hcrc); -image_get_hdr_l (time); -image_get_hdr_l (size); -image_get_hdr_l (load); -image_get_hdr_l (ep); -image_get_hdr_l (dcrc); +image_get_hdr_l (magic); /* image_get_magic */ +image_get_hdr_l (hcrc); /* image_get_hcrc */ +image_get_hdr_l (time); /* image_get_time */ +image_get_hdr_l (size); /* image_get_size */ +image_get_hdr_l (load); /* image_get_load */ +image_get_hdr_l (ep); /* image_get_ep */ +image_get_hdr_l (dcrc); /* image_get_dcrc */ #define image_get_hdr_b(f) \ static inline uint8_t image_get_##f(image_header_t *hdr) \ { \ return hdr->ih_##f; \ } -image_get_hdr_b (os); -image_get_hdr_b (arch); -image_get_hdr_b (type); -image_get_hdr_b (comp); +image_get_hdr_b (os); /* image_get_os */ +image_get_hdr_b (arch); /* image_get_arch */ +image_get_hdr_b (type); /* image_get_type */ +image_get_hdr_b (comp); /* image_get_comp */ static inline char *image_get_name (image_header_t *hdr) { @@ -396,23 +396,23 @@ static inline ulong image_get_image_end (image_header_t *hdr) { \ hdr->ih_##f = cpu_to_uimage (val); \ } -image_set_hdr_l (magic); -image_set_hdr_l (hcrc); -image_set_hdr_l (time); -image_set_hdr_l (size); -image_set_hdr_l (load); -image_set_hdr_l (ep); -image_set_hdr_l (dcrc); +image_set_hdr_l (magic); /* image_set_magic */ +image_set_hdr_l (hcrc); /* image_set_hcrc */ +image_set_hdr_l (time); /* image_set_time */ +image_set_hdr_l (size); /* image_set_size */ +image_set_hdr_l (load); /* image_set_load */ +image_set_hdr_l (ep); /* image_set_ep */ +image_set_hdr_l (dcrc); /* image_set_dcrc */ #define image_set_hdr_b(f) \ static inline void image_set_##f(image_header_t *hdr, uint8_t val) \ { \ hdr->ih_##f = val; \ } -image_set_hdr_b (os); -image_set_hdr_b (arch); -image_set_hdr_b (type); -image_set_hdr_b (comp); +image_set_hdr_b (os); /* image_set_os */ +image_set_hdr_b (arch); /* image_set_arch */ +image_set_hdr_b (type); /* image_set_type */ +image_set_hdr_b (comp); /* image_set_comp */ static inline void image_set_name (image_header_t *hdr, const char *name) { diff --git a/include/mb862xx.h b/include/mb862xx.h index 1af567002..164305fbb 100644 --- a/include/mb862xx.h +++ b/include/mb862xx.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License diff --git a/include/mmc.h b/include/mmc.h index 19c76fe4c..b9b27ba18 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -1,6 +1,8 @@ /* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Copyright 2008, Freescale Semiconductor, Inc + * Andy Fleming + * + * Based (loosely) on the Linux code * * See file CREDITS for list of people who contributed to this * project. @@ -23,35 +25,255 @@ #ifndef _MMC_H_ #define _MMC_H_ -#include <asm/arch/mmc.h> -/* MMC command numbers */ +#include <linux/list.h> + +#define SD_VERSION_SD 0x20000 +#define SD_VERSION_2 (SD_VERSION_SD | 0x20) +#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10) +#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a) +#define MMC_VERSION_MMC 0x10000 +#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) +#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12) +#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14) +#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22) +#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30) +#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40) + +#define MMC_MODE_HS 0x001 +#define MMC_MODE_HS_52MHz 0x010 +#define MMC_MODE_4BIT 0x100 +#define MMC_MODE_8BIT 0x200 + +#define SD_DATA_4BIT 0x00040000 + +#define IS_SD(x) (mmc->version & SD_VERSION_SD) + +#define MMC_DATA_READ 1 +#define MMC_DATA_WRITE 2 + +#define NO_CARD_ERR -16 /* No SD/MMC card inserted */ +#define UNUSABLE_ERR -17 /* Unusable Card */ +#define COMM_ERR -18 /* Communications Error */ +#define TIMEOUT -19 + #define MMC_CMD_GO_IDLE_STATE 0 #define MMC_CMD_SEND_OP_COND 1 #define MMC_CMD_ALL_SEND_CID 2 #define MMC_CMD_SET_RELATIVE_ADDR 3 #define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SWITCH 6 #define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_EXT_CSD 8 #define MMC_CMD_SEND_CSD 9 #define MMC_CMD_SEND_CID 10 +#define MMC_CMD_STOP_TRANSMISSION 12 #define MMC_CMD_SEND_STATUS 13 #define MMC_CMD_SET_BLOCKLEN 16 #define MMC_CMD_READ_SINGLE_BLOCK 17 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 -#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_WRITE_SINGLE_BLOCK 24 +#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 #define MMC_CMD_APP_CMD 55 -/* SD Card command numbers */ #define SD_CMD_SEND_RELATIVE_ADDR 3 -#define SD_CMD_SWITCH 6 +#define SD_CMD_SWITCH_FUNC 6 #define SD_CMD_SEND_IF_COND 8 #define SD_CMD_APP_SET_BUS_WIDTH 6 #define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_SEND_SCR 51 + +/* SCR definitions in different words */ +#define SD_HIGHSPEED_BUSY 0x00020000 +#define SD_HIGHSPEED_SUPPORTED 0x00020000 + +#define MMC_HS_TIMING 0x00000100 +#define MMC_HS_52MHZ 0x2 + +#define OCR_BUSY 0x80 +#define OCR_HCS 0x40000000 + +#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ +#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ + +#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ +#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte + addressed by index which are + 1 in value field */ +#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte + addressed by index, which are + 1 in value field */ +#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ + +#define SD_SWITCH_CHECK 0 +#define SD_SWITCH_SWITCH 1 + +/* + * EXT_CSD fields + */ + +#define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_HS_TIMING 185 /* R/W */ +#define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_REV 192 /* RO */ +#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ + +/* + * EXT_CSD field definitions + */ + +#define EXT_CSD_CMD_SET_NORMAL (1<<0) +#define EXT_CSD_CMD_SET_SECURE (1<<1) +#define EXT_CSD_CMD_SET_CPSECURE (1<<2) + +#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ + +#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ + +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ + MMC_RSP_BUSY) +#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) + + +struct mmc_cid { + unsigned long psn; + unsigned short oid; + unsigned char mid; + unsigned char prv; + unsigned char mdt; + char pnm[7]; +}; + +struct mmc_csd +{ + u8 csd_structure:2, + spec_vers:4, + rsvd1:2; + u8 taac; + u8 nsac; + u8 tran_speed; + u16 ccc:12, + read_bl_len:4; + u64 read_bl_partial:1, + write_blk_misalign:1, + read_blk_misalign:1, + dsr_imp:1, + rsvd2:2, + c_size:12, + vdd_r_curr_min:3, + vdd_r_curr_max:3, + vdd_w_curr_min:3, + vdd_w_curr_max:3, + c_size_mult:3, + sector_size:5, + erase_grp_size:5, + wp_grp_size:5, + wp_grp_enable:1, + default_ecc:2, + r2w_factor:3, + write_bl_len:4, + write_bl_partial:1, + rsvd3:5; + u8 file_format_grp:1, + copy:1, + perm_write_protect:1, + tmp_write_protect:1, + file_format:2, + ecc:2; + u8 crc:7; + u8 one:1; +}; + +struct mmc_cmd { + ushort cmdidx; + uint resp_type; + uint cmdarg; + char response[18]; + uint flags; +}; + +struct mmc_data { + union { + char *dest; + const char *src; /* src buffers don't get written to */ + }; + uint flags; + uint blocks; + uint blocksize; +}; + +struct mmc { + struct list_head link; + char name[32]; + void *priv; + uint voltages; + uint version; + uint f_min; + uint f_max; + int high_capacity; + uint bus_width; + uint clock; + uint card_caps; + uint host_caps; + uint ocr; + uint scr[2]; + uint csd[4]; + char cid[16]; + ushort rca; + uint tran_speed; + uint read_bl_len; + uint write_bl_len; + u64 capacity; + block_dev_desc_t block_dev; + int (*send_cmd)(struct mmc *mmc, + struct mmc_cmd *cmd, struct mmc_data *data); + void (*set_ios)(struct mmc *mmc); + int (*init)(struct mmc *mmc); +}; -int mmc_init(int verbose); -int mmc_read(ulong src, uchar *dst, int size); -int mmc_write(uchar *src, ulong dst, int size); -int mmc2info(ulong addr); +int mmc_register(struct mmc *mmc); +int mmc_initialize(bd_t *bis); +int mmc_init(struct mmc *mmc); +int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); +struct mmc *find_mmc_device(int dev_num); +void print_mmc_devices(char separator); +#ifndef CONFIG_GENERIC_MMC +int mmc_legacy_init(int verbose); +#endif #endif /* _MMC_H_ */ diff --git a/include/mpc512x.h b/include/mpc512x.h index 05a206358..0f022939d 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -573,6 +573,31 @@ void iopin_initialize(iopin_t *,int); /* Register Offset Base */ #define MPC512X_FEC (CONFIG_SYS_IMMR + 0x02800) +#define MPC512X_PATA (CONFIG_SYS_IMMR + 0x10200) + +/* IIM control */ +#define IIM_SET_UA(bk, f) ((bk << 3) | (f >> 5)) +#define IIM_SET_LA(f, bit) (((f & 0x0000001f) << 3) | bit) +#define IIM_STAT_BUSY 0x00000080 +#define IIM_STAT_PRGD 0x00000002 +#define IIM_STAT_SNSD 0x00000001 +#define IIM_ERR_WPE 0x00000040 +#define IIM_ERR_OPE 0x00000020 +#define IIM_ERR_RPE 0x00000010 +#define IIM_ERR_WLRE 0x00000008 +#define IIM_ERR_SNSE 0x00000004 +#define IIM_ERR_PARITYE 0x00000002 +#define IIM_PRG_P_SET 0x000000aa +#define IIM_PRG_P_UNSET 0 +#define IIM_FCTL_PROG_PULSE 0x00000020 +#define IIM_FCTL_PROG 0x00000001 +#define IIM_FCTL_ESNS_N 0x00000008 +#define IIM_FBAC_FBWP 0x00000080 +#define IIM_FBAC_FBOP 0x00000040 +#define IIM_FBAC_FBRP 0x00000020 +#define IIM_FBAC_FBESP 0x00000008 +#define IIM_PROTECTION 0x000000e8 +#define IIM_FMAX 31 /* Number of I2C buses */ #define I2C_BUS_CNT 3 diff --git a/include/mpc824x.h b/include/mpc824x.h index 5aa9370b1..fca9371bd 100644 --- a/include/mpc824x.h +++ b/include/mpc824x.h @@ -451,45 +451,6 @@ #define MICR_EADDR_MASK 0x30000000 #define MICR_EADDR_SHIFT 28 -#define BATU_BEPI_MSK 0xfffe0000 -#define BATU_BL_MSK 0x00001ffc - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 - -#define BATL_BRPN_MSK 0xfffe0000 -#define BATL_WIMG_MSK 0x00000078 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -/* - * I'd attempt to do defines for the PP bits, but it's use is a bit - * too complex, see the PowerPC Operating Environment Architecture - * section in the PowerPc arch book, chapter 4. - */ - /*eumb and epic config*/ #define EPIC_FPR 0x00041000 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 191488aa8..3554fdd4e 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -266,6 +266,7 @@ /* SICRL bits - MPC837x specific */ #define SICRL_USB_A 0xC0000000 #define SICRL_USB_B 0x30000000 +#define SICRL_USB_B_SD 0x20000000 #define SICRL_UART 0x0C000000 #define SICRL_GPIO_A 0x02000000 #define SICRL_GPIO_B 0x01000000 @@ -307,10 +308,12 @@ #define SICRH_GPIO2_C 0x00002000 #define SICRH_GPIO2_D 0x00001000 #define SICRH_GPIO2_E 0x00000C00 +#define SICRH_GPIO2_E_SD 0x00000800 #define SICRH_GPIO2_F 0x00000300 #define SICRH_GPIO2_G 0x000000C0 #define SICRH_GPIO2_H 0x00000030 #define SICRH_SPI 0x00000003 +#define SICRH_SPI_SD 0x00000001 #endif /* SWCRR - System Watchdog Control Register diff --git a/include/mpc86xx.h b/include/mpc86xx.h index a6fdea352..c6f30f9fd 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -34,47 +34,6 @@ #define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ #define L2CR_L2IP 0x00000001 /* global invalidate in progress */ -/* - * BAT settings. Look in config_<BOARD>.h for the actual setup - */ - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc -#define BATU_BL_512M 0x00003ffc -#define BATU_BL_1G 0x00007ffc -#define BATU_BL_2G 0x0000fffc -#define BATU_BL_4G 0x0001fffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 -#define BATU_INVALID 0x00000000 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 -#define BATL_NO_ACCESS 0x00000000 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -#define BATL_PP_NO_ACCESS BATL_PP_00 -#define BATL_PP_RO BATL_PP_01 -#define BATL_PP_RW BATL_PP_10 - #define HID0_XBSEN 0x00000100 #define HID0_HIGH_BAT_EN 0x00800000 #define HID0_XAEN 0x00020000 diff --git a/include/net.h b/include/net.h index bbe0d4b5a..b192db193 100644 --- a/include/net.h +++ b/include/net.h @@ -109,25 +109,26 @@ struct eth_device { void *priv; }; -extern int eth_initialize(bd_t *bis); /* Initialize network subsystem */ -extern int eth_register(struct eth_device* dev);/* Register network device */ -extern void eth_try_another(int first_restart); /* Change the device */ +extern int eth_initialize(bd_t *bis); /* Initialize network subsystem */ +extern int eth_register(struct eth_device* dev);/* Register network device */ +extern void eth_try_another(int first_restart); /* Change the device */ #ifdef CONFIG_NET_MULTI -extern void eth_set_current(void); /* set nterface to ethcur var. */ +extern void eth_set_current(void); /* set nterface to ethcur var */ #endif -extern struct eth_device *eth_get_dev(void); /* get the current device MAC */ -extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */ -extern int eth_get_dev_index (void); /* get the device index */ -extern void eth_set_enetaddr(int num, char* a); /* Set new MAC address */ +extern struct eth_device *eth_get_dev(void); /* get the current device MAC */ +extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */ +extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */ +extern int eth_get_dev_index (void); /* get the device index */ +extern void eth_set_enetaddr(int num, char* a); /* Set new MAC address */ -extern int eth_init(bd_t *bis); /* Initialize the device */ -extern int eth_send(volatile void *packet, int length); /* Send a packet */ +extern int eth_init(bd_t *bis); /* Initialize the device */ +extern int eth_send(volatile void *packet, int length); /* Send a packet */ #ifdef CONFIG_API -extern int eth_receive(volatile void *packet, int length); /* Receive a packet */ +extern int eth_receive(volatile void *packet, int length); /* Receive a packet*/ #endif -extern int eth_rx(void); /* Check for received packets */ -extern void eth_halt(void); /* stop SCC */ -extern char *eth_get_name(void); /* get name of current device */ +extern int eth_rx(void); /* Check for received packets */ +extern void eth_halt(void); /* stop SCC */ +extern char *eth_get_name(void); /* get name of current device */ #ifdef CONFIG_MCAST_TFTP int eth_mcast_join( IPaddr_t mcast_addr, u8 join); diff --git a/include/netdev.h b/include/netdev.h index 5c568f3c8..2794ddd57 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License diff --git a/include/pci.h b/include/pci.h index 072273be5..d0594e316 100644 --- a/include/pci.h +++ b/include/pci.h @@ -334,7 +334,7 @@ struct pci_region { #define PCI_REGION_TYPE 0x00000001 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ -#define PCI_REGION_MEMORY 0x00000100 /* System memory */ +#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ #define PCI_REGION_RO 0x00000200 /* Read-only memory */ extern __inline__ void pci_set_region(struct pci_region *reg, @@ -454,10 +454,29 @@ extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, #define pci_bus_to_phys(dev, addr, flags) \ pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) -#define pci_phys_to_mem(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) -#define pci_mem_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) -#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) -#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) +#define pci_virt_to_bus(dev, addr, flags) \ + pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ + (virt_to_phys(addr)), (flags)) +#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ + map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ + (addr), (flags)), \ + (len), (map_flags)) + +#define pci_phys_to_mem(dev, addr) \ + pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) +#define pci_mem_to_phys(dev, addr) \ + pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) +#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) +#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) + +#define pci_virt_to_mem(dev, addr) \ + pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) +#define pci_mem_to_virt(dev, addr, len, map_flags) \ + pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) +#define pci_virt_to_io(dev, addr) \ + pci_virt_to_bus((dev), (addr), PCI_REGION_IO) +#define pci_io_to_virt(dev, addr, len, map_flags) \ + pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) extern int pci_hose_read_config_byte(struct pci_controller *hose, pci_dev_t dev, int where, u8 *val); @@ -488,6 +507,7 @@ extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, pci_dev_t dev, int where, u16 val); +extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); extern void pci_register_hose(struct pci_controller* hose); extern struct pci_controller* pci_bus_to_hose(int bus); |