diff options
Diffstat (limited to 'include/ppc405.h')
| -rw-r--r-- | include/ppc405.h | 922 |
1 files changed, 621 insertions, 301 deletions
diff --git a/include/ppc405.h b/include/ppc405.h index 0c7bf3e6d..b5ad38fc5 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -22,6 +22,12 @@ #ifndef __PPC405_H__ #define __PPC405_H__ +#ifndef CONFIG_IOP480 +#define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ +#else +#define CFG_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */ +#endif + /*--------------------------------------------------------------------- */ /* Special Purpose Registers */ /*--------------------------------------------------------------------- */ @@ -123,6 +129,40 @@ #define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */ #define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */ +#if defined(CONFIG_405EX) +#define uic0sr uicsr /* UIC status */ +#define uic0srs uicsrs /* UIC status set */ +#define uic0er uicer /* UIC enable */ +#define uic0cr uiccr /* UIC critical */ +#define uic0pr uicpr /* UIC polarity */ +#define uic0tr uictr /* UIC triggering */ +#define uic0msr uicmsr /* UIC masked status */ +#define uic0vr uicvr /* UIC vector */ +#define uic0vcr uicvcr /* UIC vector configuration*/ + +#define UIC_DCR_BASE1 0xd0 +#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */ +#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */ +#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */ +#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */ +#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */ +#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */ +#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */ +#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */ +#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/ + +#define UIC_DCR_BASE2 0xe0 +#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */ +#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */ +#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */ +#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */ +#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */ +#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */ +#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */ +#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */ +#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/ +#endif + /*-----------------------------------------------------------------------------+ | Universal interrupt controller interrupts +-----------------------------------------------------------------------------*/ @@ -166,6 +206,116 @@ #define UIC_EXT3 0x00000002 /* External interrupt 3 */ #define UIC_EXT4 0x00000001 /* External interrupt 4 */ +#elif defined(CONFIG_405EX) + +/* UIC 0 */ +#define UIC_U0 0x80000000 /* */ +#define UIC_U1 0x40000000 /* */ +#define UIC_IIC0 0x20000000 /* */ +#define UIC_PKA 0x10000000 /* */ +#define UIC_TRNG 0x08000000 /* */ +#define UIC_EBM 0x04000000 /* */ +#define UIC_BGI 0x02000000 /* */ +#define UIC_IIC1 0x01000000 /* */ +#define UIC_SPI 0x00800000 /* */ +#define UIC_EIRQ0 0x00400000 /**/ +#define UIC_MTE 0x00200000 /*MAL Tx EOB */ +#define UIC_MRE 0x00100000 /*MAL Rx EOB */ +#define UIC_DMA0 0x00080000 /* */ +#define UIC_DMA1 0x00040000 /* */ +#define UIC_DMA2 0x00020000 /* */ +#define UIC_DMA3 0x00010000 /* */ +#define UIC_PCIE0AL 0x00008000 /* */ +#define UIC_PCIE0VPD 0x00004000 /* */ +#define UIC_RPCIE0HRST 0x00002000 /* */ +#define UIC_FPCIE0HRST 0x00001000 /* */ +#define UIC_PCIE0TCR 0x00000800 /* */ +#define UIC_PCIEMSI0 0x00000400 /* */ +#define UIC_PCIEMSI1 0x00000200 /* */ +#define UIC_SECURITY 0x00000100 /* */ +#define UIC_ENET 0x00000080 /* */ +#define UIC_ENET1 0x00000040 /* */ +#define UIC_PCIEMSI2 0x00000020 /* */ +#define UIC_EIRQ4 0x00000010 /**/ +#define UIC_UIC2NC 0x00000008 /* */ +#define UIC_UIC2C 0x00000004 /* */ +#define UIC_UIC1NC 0x00000002 /* */ +#define UIC_UIC1C 0x00000001 /* */ + +#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */ +#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */ +/* UIC 1 */ +#define UIC_MS 0x80000000 /* MAL SERR */ +#define UIC_MTDE 0x40000000 /* MAL TXDE */ +#define UIC_MRDE 0x20000000 /* MAL RXDE */ +#define UIC_PCIE0BMVC0 0x10000000 /* */ +#define UIC_PCIE0DCRERR 0x08000000 /* */ +#define UIC_EBC 0x04000000 /* */ +#define UIC_NDFC 0x02000000 /* */ +#define UIC_PCEI1DCRERR 0x01000000 /* */ +#define UIC_GPTCMPT8 0x00800000 /* */ +#define UIC_GPTCMPT9 0x00400000 /* */ +#define UIC_PCIE1AL 0x00200000 /* */ +#define UIC_PCIE1VPD 0x00100000 /* */ +#define UIC_RPCE1HRST 0x00080000 /* */ +#define UIC_FPCE1HRST 0x00040000 /* */ +#define UIC_PCIE1TCR 0x00020000 /* */ +#define UIC_PCIE1VC0 0x00010000 /* */ +#define UIC_GPTCMPT3 0x00008000 /* */ +#define UIC_GPTCMPT4 0x00004000 /* */ +#define UIC_EIRQ7 0x00002000 /* */ +#define UIC_EIRQ8 0x00001000 /* */ +#define UIC_EIRQ9 0x00000800 /* */ +#define UIC_GPTCMP5 0x00000400 /* */ +#define UIC_GPTCMP6 0x00000200 /* */ +#define UIC_GPTCMP7 0x00000100 /* */ +#define UIC_SROM 0x00000080 /* SERIAL ROM*/ +#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/ +#define UIC_EIRQ2 0x00000020 /* */ +#define UIC_EIRQ5 0x00000010 /* */ +#define UIC_EIRQ6 0x00000008 /* */ +#define UIC_EMAC0WAKE 0x00000004 /* */ +#define UIC_EIRQ1 0x00000002 /* */ +#define UIC_EMAC1WAKE 0x00000001 /* */ +#define UIC_MAL_SERR UIC_MS /* MAL SERR */ +#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */ +#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */ +/* UIC 2 */ +#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/ +#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/ +#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/ +#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/ +#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/ +#define UIC_DDRMCUE 0x04000000 /* */ +#define UIC_DDRMCCE 0x02000000 /* */ +#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/ +#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/ +#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/ +#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/ +#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/ +#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/ +#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/ +#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/ +#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/ +#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/ +#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/ +#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/ +#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/ +#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/ +#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/ +#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/ +#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/ +#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/ +#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/ +#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/ +#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/ +#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/ +#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/ +#define UIC_USBWAKE 0x00000002 /* USB wakup*/ +#define UIC_USBOTG 0x00000001 /* USB OTG*/ +#define UIC_ETH0 UIC_ENET +#define UIC_ETH1 UIC_ENET1 + #else /* !defined(CONFIG_405EZ) */ #define UIC_UART0 0x80000000 /* UART 0 */ @@ -200,9 +350,6 @@ /****************************************************************************** * SDRAM Controller ******************************************************************************/ -#define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ -#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ /* values for memcfga register - indirect addressing of these regs */ #ifndef CONFIG_405EP #define mem_besra 0x00 /* bus error syndrome reg a */ @@ -256,7 +403,11 @@ /****************************************************************************** * Power Management ******************************************************************************/ +#ifdef CONFIG_405EX +#define POWERMAN_DCR_BASE 0xb0 +#else #define POWERMAN_DCR_BASE 0xb8 +#endif #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ @@ -264,9 +415,6 @@ /****************************************************************************** * Extrnal Bus Controller ******************************************************************************/ -#define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ -#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ /* values for ebccfga register - indirect addressing of these regs */ #define pb0cr 0x00 /* periph bank 0 config reg */ #define pb1cr 0x01 /* periph bank 1 config reg */ @@ -561,16 +709,6 @@ #define VCO_MIN 500 #define VCO_MAX 1000 #elif defined(CONFIG_405EZ) -/****************************************************************************** - * SDR Registers - ******************************************************************************/ -#define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */ -#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */ - -#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) -#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) - #define sdrnand0 0x4000 #define sdrultra0 0x4040 #define sdrultra1 0x4050 @@ -604,10 +742,6 @@ /****************************************************************************** * Control ******************************************************************************/ -#define CNTRL_DCR_BASE 0x0C -#define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */ -#define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */ - /* CPR Registers */ #define cprclkupd 0x020 /* CPR_CLKUPD */ #define cprpllc 0x040 /* CPR_PLLC */ @@ -619,12 +753,6 @@ #define cprmisc0 0x181 /* CPR_MISC0 */ #define cprmisc1 0x182 /* CPR_MISC1 */ -/* - * Macro for accessing the indirect CPR register - */ -#define mtcpr(reg, data) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0) -#define mfcpr(reg, data) do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0) - #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ @@ -645,252 +773,6 @@ #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ -#if 0 /* Deprecated */ -#define CNTRL_DCR_BASE 0x0f0 -#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ -#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ -#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ -#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ -#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ -#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ - -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ - -/* Bit definitions */ -#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ -#define PLLMR0_CPU_DIV_BYPASS 0x00000000 -#define PLLMR0_CPU_DIV_2 0x00100000 -#define PLLMR0_CPU_DIV_3 0x00200000 -#define PLLMR0_CPU_DIV_4 0x00300000 - -#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ -#define PLLMR0_CPU_PLB_DIV_1 0x00000000 -#define PLLMR0_CPU_PLB_DIV_2 0x00010000 -#define PLLMR0_CPU_PLB_DIV_3 0x00020000 -#define PLLMR0_CPU_PLB_DIV_4 0x00030000 - -#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ -#define PLLMR0_OPB_PLB_DIV_1 0x00000000 -#define PLLMR0_OPB_PLB_DIV_2 0x00001000 -#define PLLMR0_OPB_PLB_DIV_3 0x00002000 -#define PLLMR0_OPB_PLB_DIV_4 0x00003000 - -#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ -#define PLLMR0_EXB_PLB_DIV_2 0x00000000 -#define PLLMR0_EXB_PLB_DIV_3 0x00000100 -#define PLLMR0_EXB_PLB_DIV_4 0x00000200 -#define PLLMR0_EXB_PLB_DIV_5 0x00000300 - -#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ -#define PLLMR0_MAL_PLB_DIV_1 0x00000000 -#define PLLMR0_MAL_PLB_DIV_2 0x00000010 -#define PLLMR0_MAL_PLB_DIV_3 0x00000020 -#define PLLMR0_MAL_PLB_DIV_4 0x00000030 - -#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ -#define PLLMR0_PCI_PLB_DIV_1 0x00000000 -#define PLLMR0_PCI_PLB_DIV_2 0x00000001 -#define PLLMR0_PCI_PLB_DIV_3 0x00000002 -#define PLLMR0_PCI_PLB_DIV_4 0x00000003 - -#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ -#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ -#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ -#define PLLMR1_FBMUL_DIV_16 0x00000000 -#define PLLMR1_FBMUL_DIV_1 0x00100000 -#define PLLMR1_FBMUL_DIV_2 0x00200000 -#define PLLMR1_FBMUL_DIV_3 0x00300000 -#define PLLMR1_FBMUL_DIV_4 0x00400000 -#define PLLMR1_FBMUL_DIV_5 0x00500000 -#define PLLMR1_FBMUL_DIV_6 0x00600000 -#define PLLMR1_FBMUL_DIV_7 0x00700000 -#define PLLMR1_FBMUL_DIV_8 0x00800000 -#define PLLMR1_FBMUL_DIV_9 0x00900000 -#define PLLMR1_FBMUL_DIV_10 0x00A00000 -#define PLLMR1_FBMUL_DIV_11 0x00B00000 -#define PLLMR1_FBMUL_DIV_12 0x00C00000 -#define PLLMR1_FBMUL_DIV_13 0x00D00000 -#define PLLMR1_FBMUL_DIV_14 0x00E00000 -#define PLLMR1_FBMUL_DIV_15 0x00F00000 - -#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ -#define PLLMR1_FWDVA_DIV_8 0x00000000 -#define PLLMR1_FWDVA_DIV_7 0x00010000 -#define PLLMR1_FWDVA_DIV_6 0x00020000 -#define PLLMR1_FWDVA_DIV_5 0x00030000 -#define PLLMR1_FWDVA_DIV_4 0x00040000 -#define PLLMR1_FWDVA_DIV_3 0x00050000 -#define PLLMR1_FWDVA_DIV_2 0x00060000 -#define PLLMR1_FWDVA_DIV_1 0x00070000 -#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ -#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ - -/* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 - -/* Defines for CPC0_BOOR Register */ -#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ - -/* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ - -/* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -/* - *------------------------------------------------------------------------------- - * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, - * assuming a 33.3MHz input clock to the 405EP. - *------------------------------------------------------------------------------- - */ -#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -/* - * PLL Voltage Controlled Oscillator (VCO) definitions - * Maximum and minimum values (in MHz) for correct PLL operation. - */ -#define VCO_MIN 500 -#define VCO_MAX 1000 -#endif /* #if 0 */ #else /* #ifdef CONFIG_405EP */ /****************************************************************************** * Control @@ -1214,6 +1096,25 @@ #define GPIO1_ISR3L (GPIO1_BASE+0x40) #define GPIO1_ISR3H (GPIO1_BASE+0x44) +#elif defined(CONFIG_405EX) +#define GPIO_BASE 0xEF600800 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + #else /* !405EZ */ #define GPIO_BASE 0xEF600700 @@ -1234,39 +1135,458 @@ #endif /* CONFIG_405EZ */ -/* - * Macro for accessing the indirect EBC register - */ -#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) -#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) +#define GPIO0_BASE GPIO_BASE + +#if defined(CONFIG_405EX) +#define SDR0_SRST 0x0200 + +#define SDRAM_BESR0 0x00 +#define SDRAM_BEARL 0x02 +#define SDRAM_BEARU 0x03 +#define SDRAM_WMIRQ 0x06 /**/ +#define SDRAM_PLBOPT 0x08 /**/ +#define SDRAM_PUABA 0x09 /**/ +#define SDRAM_MCSTAT 0x1F /* memory controller status */ +#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ +#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ +#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ +#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ +#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ +#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ +#define SDRAM_CODT 0x26 /* on die termination for controller */ +#define SDRAM_VVPR 0x27 /* variable VRef programmming */ +#define SDRAM_OPARS 0x28 /* on chip driver control setup */ +#define SDRAM_OPART 0x29 /* on chip driver control trigger */ +#define SDRAM_RTR 0x30 /* refresh timer */ +#define SDRAM_PMIT 0x34 /* power management idle timer */ +#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ +#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ +#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */ +#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */ +#define SDRAM_INITPLR0 0x50 /* manual initialization control */ +#define SDRAM_INITPLR1 0x51 /* manual initialization control */ +#define SDRAM_INITPLR2 0x52 /* manual initialization control */ +#define SDRAM_INITPLR3 0x53 /* manual initialization control */ +#define SDRAM_INITPLR4 0x54 /* manual initialization control */ +#define SDRAM_INITPLR5 0x55 /* manual initialization control */ +#define SDRAM_INITPLR6 0x56 /* manual initialization control */ +#define SDRAM_INITPLR7 0x57 /* manual initialization control */ +#define SDRAM_INITPLR8 0x58 /* manual initialization control */ +#define SDRAM_INITPLR9 0x59 /* manual initialization control */ +#define SDRAM_INITPLR10 0x5a /* manual initialization control */ +#define SDRAM_INITPLR11 0x5b /* manual initialization control */ +#define SDRAM_INITPLR12 0x5c /* manual initialization control */ +#define SDRAM_INITPLR13 0x5d /* manual initialization control */ +#define SDRAM_INITPLR14 0x5e /* manual initialization control */ +#define SDRAM_INITPLR15 0x5f /* manual initialization control */ +#define SDRAM_RQDC 0x70 /* read DQS delay control */ +#define SDRAM_RFDC 0x74 /* read feedback delay control */ +#define SDRAM_RDCC 0x78 /* read data capture control */ +#define SDRAM_DLCR 0x7A /* delay line calibration */ +#define SDRAM_CLKTR 0x80 /* DDR clock timing */ +#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ +#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ +#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ +#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ +#define SDRAM_MMODE 0x88 /* memory mode */ +#define SDRAM_MEMODE 0x89 /* memory extended mode */ +#define SDRAM_ECCCR 0x98 /* ECC error status */ +#define SDRAM_RID 0xF8 /* revision ID */ + +/*-----------------------------------------------------------------------------+ +| Memory Bank 0-7 configuration ++-----------------------------------------------------------------------------*/ +#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */ +#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */ +#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */ +#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */ +#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */ +#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */ +#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */ +#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */ +#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */ +#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */ +#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */ +#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Status ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ +#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ +#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ +#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ +#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Options 1 ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */ +#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ +#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ +#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ +#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ +#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3) +#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ +#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ +#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ +#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ +#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ +#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ +#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ +#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ +#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ +#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ +#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ +#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ +#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ +#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ +#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ +#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ +#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ +#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ +#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ +#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ +#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ +#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ +#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ +#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ +#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ +#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ +#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ +#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ +#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Options 2 ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ +#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ +#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ +#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ +#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ +#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ +#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ +#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ +#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ +#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ +#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ +#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ +#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ +#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ +#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ + +/*-----------------------------------------------------------------------------+ +| SDRAM Refresh Timer Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RTR_RINT_MASK 0xFFF80000 +#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16) +#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8) + +/*-----------------------------------------------------------------------------+ +| SDRAM Read DQS Delay Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RQDC_RQDE_MASK 0x80000000 +#define SDRAM_RQDC_RQDE_DISABLE 0x00000000 +#define SDRAM_RQDC_RQDE_ENABLE 0x80000000 +#define SDRAM_RQDC_RQFD_MASK 0x000001FF +#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) + +#define SDRAM_RQDC_RQFD_MAX 0xFF + +/*-----------------------------------------------------------------------------+ +| SDRAM Read Data Capture Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RDCC_RDSS_MASK 0xC0000000 +#define SDRAM_RDCC_RDSS_T1 0x00000000 +#define SDRAM_RDCC_RDSS_T2 0x40000000 +#define SDRAM_RDCC_RDSS_T3 0x80000000 +#define SDRAM_RDCC_RDSS_T4 0xC0000000 +#define SDRAM_RDCC_RSAE_MASK 0x00000001 +#define SDRAM_RDCC_RSAE_DISABLE 0x00000001 +#define SDRAM_RDCC_RSAE_ENABLE 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Read Feedback Delay Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RFDC_ARSE_MASK 0x80000000 +#define SDRAM_RFDC_ARSE_DISABLE 0x80000000 +#define SDRAM_RFDC_ARSE_ENABLE 0x00000000 +#define SDRAM_RFDC_RFOS_MASK 0x007F0000 +#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define SDRAM_RFDC_RFFD_MASK 0x000003FF +#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) + +#define SDRAM_RFDC_RFFD_MAX 0x4FF + +/*-----------------------------------------------------------------------------+ +| SDRAM Delay Line Calibration Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_DLCR_DCLM_MASK 0x80000000 +#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 +#define SDRAM_DLCR_DCLM_AUTO 0x00000000 +#define SDRAM_DLCR_DLCR_MASK 0x08000000 +#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 +#define SDRAM_DLCR_DLCR_IDLE 0x00000000 +#define SDRAM_DLCR_DLCS_MASK 0x07000000 +#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 +#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 +#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 +#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 +#define SDRAM_DLCR_DLCS_ERROR 0x04000000 +#define SDRAM_DLCR_DLCV_MASK 0x000001FF +#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) +#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF) + +/*-----------------------------------------------------------------------------+ +| SDRAM Controller On Die Termination Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_CODT_ODT_ON 0x80000000 +#define SDRAM_CODT_ODT_OFF 0x00000000 +#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 +#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 +#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 +#define SDRAM_CODT_DQS_MASK 0x00000010 +#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 +#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 +#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 +#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 +#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 +#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 +#define SDRAM_CODT_IO_HIZ 0x00000000 +#define SDRAM_CODT_IO_NMODE 0x00000001 -#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0) -#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0) +/*-----------------------------------------------------------------------------+ +| SDRAM Mode Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_MMODE_WR_MASK 0x00000E00 +#define SDRAM_MMODE_WR_DDR1 0x00000000 +#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 +#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 +#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 +#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 +#define SDRAM_MMODE_DCL_MASK 0x00000070 +#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 +#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 +#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 +#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 +#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 +#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 +#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 +#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 +#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 + +/*-----------------------------------------------------------------------------+ +| SDRAM Extended Mode Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_MEMODE_DIC_MASK 0x00000002 +#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 +#define SDRAM_MEMODE_DIC_WEAK 0x00000002 +#define SDRAM_MEMODE_DLL_MASK 0x00000001 +#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 +#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 +#define SDRAM_MEMODE_RTT_MASK 0x00000044 +#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 +#define SDRAM_MEMODE_RTT_75OHM 0x00000004 +#define SDRAM_MEMODE_RTT_150OHM 0x00000040 +#define SDRAM_MEMODE_DQS_MASK 0x00000400 +#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 +#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Clock Timing Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 +#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 +#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Write Timing Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000 +#define SDRAM_WRDTR_LLWP_MASK 0x10000000 +#define SDRAM_WRDTR_LLWP_DIS 0x10000000 +#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 +#define SDRAM_WRDTR_WTR_MASK 0x0E000000 +#define SDRAM_WRDTR_WTR_0_DEG 0x06000000 +#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 +#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR1 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR1_LDOF_MASK 0x80000000 +#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 +#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 +#define SDRAM_SDTR1_RTW_MASK 0x00F00000 +#define SDRAM_SDTR1_RTW_2_CLK 0x00200000 +#define SDRAM_SDTR1_RTW_3_CLK 0x00300000 +#define SDRAM_SDTR1_WTWO_MASK 0x000F0000 +#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 +#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 +#define SDRAM_SDTR1_RTRO_MASK 0x0000F000 +#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000 +#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR2 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR2_RCD_MASK 0xF0000000 +#define SDRAM_SDTR2_RCD_1_CLK 0x10000000 +#define SDRAM_SDTR2_RCD_2_CLK 0x20000000 +#define SDRAM_SDTR2_RCD_3_CLK 0x30000000 +#define SDRAM_SDTR2_RCD_4_CLK 0x40000000 +#define SDRAM_SDTR2_RCD_5_CLK 0x50000000 +#define SDRAM_SDTR2_WTR_MASK 0x0F000000 +#define SDRAM_SDTR2_WTR_1_CLK 0x01000000 +#define SDRAM_SDTR2_WTR_2_CLK 0x02000000 +#define SDRAM_SDTR2_WTR_3_CLK 0x03000000 +#define SDRAM_SDTR2_WTR_4_CLK 0x04000000 +#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 +#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 +#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 +#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 +#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 +#define SDRAM_SDTR2_WPC_MASK 0x0000F000 +#define SDRAM_SDTR2_WPC_2_CLK 0x00002000 +#define SDRAM_SDTR2_WPC_3_CLK 0x00003000 +#define SDRAM_SDTR2_WPC_4_CLK 0x00004000 +#define SDRAM_SDTR2_WPC_5_CLK 0x00005000 +#define SDRAM_SDTR2_WPC_6_CLK 0x00006000 +#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12) +#define SDRAM_SDTR2_RPC_MASK 0x00000F00 +#define SDRAM_SDTR2_RPC_2_CLK 0x00000200 +#define SDRAM_SDTR2_RPC_3_CLK 0x00000300 +#define SDRAM_SDTR2_RPC_4_CLK 0x00000400 +#define SDRAM_SDTR2_RP_MASK 0x000000F0 +#define SDRAM_SDTR2_RP_3_CLK 0x00000030 +#define SDRAM_SDTR2_RP_4_CLK 0x00000040 +#define SDRAM_SDTR2_RP_5_CLK 0x00000050 +#define SDRAM_SDTR2_RP_6_CLK 0x00000060 +#define SDRAM_SDTR2_RP_7_CLK 0x00000070 +#define SDRAM_SDTR2_RRD_MASK 0x0000000F +#define SDRAM_SDTR2_RRD_2_CLK 0x00000002 +#define SDRAM_SDTR2_RRD_3_CLK 0x00000003 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR3 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR3_RAS_MASK 0x1F000000 +#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define SDRAM_SDTR3_RC_MASK 0x001F0000 +#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define SDRAM_SDTR3_XCS_MASK 0x00001F00 +#define SDRAM_SDTR3_XCS 0x00000D00 +#define SDRAM_SDTR3_RFC_MASK 0x0000003F +#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) + +/*-----------------------------------------------------------------------------+ +| Memory Bank 0-1 configuration ++-----------------------------------------------------------------------------*/ +#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ +#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ +#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ +#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ +#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ +#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ +#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ +#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ +#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ +#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ +#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ +#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ +#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ +#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ + +#define sdr_uart0 0x0120 /* UART0 Config */ +#define sdr_uart1 0x0121 /* UART1 Config */ +#define sdr_mfr 0x4300 /* SDR0_MFR reg */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +#define cpr0_clkupd 0x020 +#define cpr0_pllc 0x040 +#define cpr0_plld 0x060 +#define cpr0_cpud 0x080 +#define cpr0_plbd 0x0a0 +#define cpr0_opbd 0x0c0 +#define cpr0_perd 0x0e0 +#define cpr0_ahbd 0x100 +#define cpr0_icfg 0x140 + +#define SDR_PINSTP 0x0040 +#define sdr_sdcs 0x0060 + +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +/* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0 0x4000 +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ -#ifndef __ASSEMBLY__ +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ -typedef struct -{ - unsigned long pllFwdDiv; - unsigned long pllFwdDivB; - unsigned long pllFbkDiv; - unsigned long pllPlbDiv; - unsigned long pllPciDiv; - unsigned long pllExtBusDiv; - unsigned long pllOpbDiv; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long freqProcessor; - unsigned long freqPLB; - unsigned long freqPCI; - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pciClkSync; /* PCI clock is synchronous */ - unsigned long freqVCOHz; -} PPC405_SYS_INFO; +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) -#endif /* _ASMLANGUAGE */ +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) -#define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache - line aligned data. */ +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ + +#define SDR0_PFC0 0x4100 +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME 0x02000000 +#define SDR0_PFC1_U0ME 0x00080000 +#define SDR0_PFC1_U0IM 0x00040000 +#define SDR0_PFC1_SIS 0x00020000 +#define SDR0_PFC1_DMAAEN 0x00010000 +#define SDR0_PFC1_DMADEN 0x00008000 +#define SDR0_PFC1_USBEN 0x00004000 +#define SDR0_PFC1_AHBSWAP 0x00000020 +#define SDR0_PFC1_USBBIGEN 0x00000010 +#define SDR0_PFC1_GPT_FREQ 0x0000000f +#endif #endif /* __PPC405_H__ */ |