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-rw-r--r--include/configs/P2041RDB.h58
-rw-r--r--include/configs/P3060QDS.h48
-rw-r--r--include/configs/P4080DS.h1
-rw-r--r--include/configs/P5020DS.h2
-rw-r--r--include/configs/am335x_evm.h1
-rw-r--r--include/configs/am3517_crane.h2
-rw-r--r--include/configs/am3517_evm.h2
-rw-r--r--include/configs/cam_enc_4xx.h3
-rw-r--r--include/configs/corenet_ds.h83
-rw-r--r--include/configs/da850evm.h15
-rw-r--r--include/configs/devkit8000.h1
-rw-r--r--include/configs/hawkboard.h5
-rw-r--r--include/configs/igep00x0.h1
-rw-r--r--include/configs/mcx.h2
-rw-r--r--include/configs/omap3_beagle.h1
-rw-r--r--include/configs/omap3_evm_common.h1
-rw-r--r--include/configs/omap3_overo.h1
-rw-r--r--include/configs/omap4_common.h2
-rw-r--r--include/configs/omap5_evm.h2
-rw-r--r--include/configs/p1_p2_rdb_pc.h10
-rw-r--r--include/configs/tam3517-common.h2
-rw-r--r--include/configs/tricorder.h1
22 files changed, 132 insertions, 112 deletions
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 1c0eb7401..31696655b 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -22,7 +22,7 @@
/*
* P2041 RDB board configuration file
- *
+ * Also supports P2040 RDB
*/
#ifndef __CONFIG_H
#define __CONFIG_H
@@ -36,6 +36,15 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500 /* BOOKE e500 family */
@@ -73,7 +82,7 @@
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
-#ifndef CONFIG_RAMBOOT_PBL
+#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_NOWHERE
#endif
#else
@@ -104,8 +113,12 @@
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR 0xffe20000
+#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_ENV_IS_NOWHERE)
- #define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
@@ -374,6 +387,35 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
* eSPI - Enhanced SPI
*/
#define CONFIG_FSL_ESPI
@@ -485,6 +527,16 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
diff --git a/include/configs/P3060QDS.h b/include/configs/P3060QDS.h
deleted file mode 100644
index 800654700..000000000
--- a/include/configs/P3060QDS.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * P3060 QDS board configuration file
- */
-#define CONFIG_P3060QDS
-#define CONFIG_PHYS_64BIT
-#define CONFIG_PPC_P3060
-#define CONFIG_FSL_QIXIS
-
-#define CONFIG_NAND_FSL_ELBC
-
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_EON
-#define CONFIG_SPI_FLASH_SST
-
-#include "corenet_ds.h"
-
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-
-/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */
-#define CONFIG_I2C_MUX
-#define CONFIG_I2C_MULTI_BUS
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 4a2e47513..d6f2f5ceb 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -22,6 +22,7 @@
/*
* P4080 DS board configuration file
+ * Also supports P4040 DS
*/
#define CONFIG_P4080DS
#define CONFIG_PHYS_64BIT
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index 4afc4f16e..8625f7629 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -22,7 +22,7 @@
/*
* P5020 DS board configuration file
- *
+ * Also supports P5010 DS
*/
#define CONFIG_P5020DS
#define CONFIG_PHYS_64BIT
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index a3752bca6..263a5adb3 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -193,6 +193,7 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (46 * 1024)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index f24b44d5e..8ddeff46f 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -314,6 +314,8 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 95f8d7885..698081100 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -313,6 +313,8 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
index 91ab81284..9b56e028f 100644
--- a/include/configs/cam_enc_4xx.h
+++ b/include/configs/cam_enc_4xx.h
@@ -215,10 +215,11 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_LOAD
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_POST_MEM_SUPPORT
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index f8f7a82aa..f4f9bd12a 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -31,13 +31,21 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
+#if defined(CONFIG_P3041DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
+#elif defined(CONFIG_P4080DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
+#elif defined(CONFIG_P5020DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
+#endif
#endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
-#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_NO_FLASH
#endif
@@ -77,7 +85,7 @@
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
-#if !defined(CONFIG_SRIOBOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_ENV_IS_NOWHERE
#endif
#else
@@ -108,7 +116,7 @@
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_ENV_SIZE 0x2000
@@ -186,11 +194,7 @@
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR3
-#ifdef CONFIG_P3060QDS
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#else
#define CONFIG_SYS_SPD_BUS_NUM 1
-#endif
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
@@ -389,51 +393,32 @@
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
- * SRIOBOOT - MASTER
- */
-#ifdef CONFIG_SRIOBOOT_MASTER
-/* master port for srioboot*/
-#define CONFIG_SRIOBOOT_MASTER_PORT 0
-/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */
-/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
/*
- * for slave UCODE instored in master memory space,
+ * for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull
-#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull
-#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */
-/*
- * for slave ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull
-#define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull
-#define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+
/* slave core release by master*/
-#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF
-#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */
-#endif
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/*
- * SRIOBOOT - SLAVE
+ * SRIO_PCIE_BOOT - SLAVE
*/
-#ifdef CONFIG_SRIOBOOT_SLAVE
-/* slave port for srioboot */
-#define CONFIG_SRIOBOOT_SLAVE_PORT0
-/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
-#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif
/*
@@ -556,13 +541,13 @@
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
* in two corenet boards, slave's ucode could be stored in master's memory
* space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO outbound window->master inbound window->master LAW->
- * the ucode address in master's NOR flash.
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
@@ -724,7 +709,7 @@
#define CONFIG_BAUDRATE 115200
-#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS)
+#ifdef CONFIG_P4080DS
#define __USB_PHY_TYPE ulpi
#else
#define __USB_PHY_TYPE utmi
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 09a966092..ddd615509 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -380,6 +380,16 @@
#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
+ CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
@@ -392,10 +402,9 @@
/* Load U-Boot Image From MMC */
#ifdef CONFIG_SPL_MMC_LOAD
#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SYS_MMC_U_BOOT_OFFS 0x75
-#define CONFIG_SYS_MMC_U_BOOT_SIZE 0x30000
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75
+#undef CONFIG_SPL_SPI_SUPPORT
#undef CONFIG_SPL_SPI_LOAD
#endif
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index de75dafc9..2d2ee5f1a 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -303,6 +303,7 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_LIBCOMMON_SUPPORT
diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h
index 73ab4c837..c0e3ed3ef 100644
--- a/include/configs/hawkboard.h
+++ b/include/configs/hawkboard.h
@@ -60,9 +60,10 @@
/* Spl */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_LOAD
#define CONFIG_SPL_LIBGENERIC_SUPPORT /* for udelay and __div64_32 for NAND */
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-hawk.lds"
@@ -79,6 +80,7 @@
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 -\
GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_MONITOR_LEN 0x60000
/* memtest start addr */
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1)
@@ -136,7 +138,6 @@
#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xe0000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1180000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
index 5468a1a21..b1071e892 100644
--- a/include/configs/igep00x0.h
+++ b/include/configs/igep00x0.h
@@ -295,6 +295,7 @@
/* SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024)
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 733022e78..359522a64 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -359,6 +359,8 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_SOFTECC
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 782a4c598..f79f99645 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -391,6 +391,7 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
index d9578f47b..2ef3aaa18 100644
--- a/include/configs/omap3_evm_common.h
+++ b/include/configs/omap3_evm_common.h
@@ -273,6 +273,7 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index dd4b2c0e8..f6d6f75fc 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -293,6 +293,7 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index ee0c4b9d9..cbc9bdb40 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -232,9 +232,11 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40304350
#define CONFIG_SPL_MAX_SIZE (38 * 1024)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_DISPLAY_PRINT
/*
* 64 bytes before this address should be set aside for u-boot.img's
diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h
index 4f0a6c135..743edfdcc 100644
--- a/include/configs/omap5_evm.h
+++ b/include/configs/omap5_evm.h
@@ -229,9 +229,11 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40300350
#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_DISPLAY_PRINT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index a8882d49d..b18f4a0ec 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -31,7 +31,7 @@
#endif
#if defined(CONFIG_P1020MBG)
-#define CONFIG_BOARDNAME "P1020MBG"
+#define CONFIG_BOARDNAME "P1020MBG-PC"
#define CONFIG_P1020
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
@@ -41,7 +41,7 @@
#endif
#if defined(CONFIG_P1020UTM)
-#define CONFIG_BOARDNAME "P1020UTM"
+#define CONFIG_BOARDNAME "P1020UTM-PC"
#define CONFIG_P1020
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xe0
@@ -49,7 +49,7 @@
#endif
#if defined(CONFIG_P1020RDB)
-#define CONFIG_BOARDNAME "P1020RDB"
+#define CONFIG_BOARDNAME "P1020RDB-PC"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P1020
#define CONFIG_SPI_FLASH
@@ -64,7 +64,7 @@
#endif
#if defined(CONFIG_P1021RDB)
-#define CONFIG_BOARDNAME "P1021RDB"
+#define CONFIG_BOARDNAME "P1021RDB-PC"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P1021
#define CONFIG_QE
@@ -111,7 +111,7 @@
#endif
#if defined(CONFIG_P2020RDB)
-#define CONFIG_BOARDNAME "P2020RDB"
+#define CONFIG_BOARDNAME "P2020RDB-PCA"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P2020
#define CONFIG_SPI_FLASH
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index a13fd9376..cbb6c7ec3 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -239,6 +239,8 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_CONSOLE
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_SOFTECC
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 63c98dc72..00d02e8ca 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -271,6 +271,7 @@
/* Defines for SPL */
#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_BOARD_INIT
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-11-01 17:49:16 +0000