diff options
Diffstat (limited to 'include/configs/hymod.h')
| -rw-r--r-- | include/configs/hymod.h | 212 |
1 files changed, 106 insertions, 106 deletions
diff --git a/include/configs/hymod.h b/include/configs/hymod.h index 4c83193f8..0fdcda230 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -87,10 +87,10 @@ * - RAM for BD/Buffers is on the 60x Bus (see 28-13) * - Enable Full Duplex in FSMR */ -# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) +# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) +# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11) +# define CONFIG_SYS_CPMFCR_RAMTYPE 0 +# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) # define MDIO_PORT 0 /* Port A */ # define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ @@ -104,10 +104,10 @@ * - RAM for BD/Buffers is on the 60x Bus (see 28-13) * - Enable Full Duplex in FSMR */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) +# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CONFIG_SYS_CPMFCR_RAMTYPE 0 +# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) # define MDIO_PORT 0 /* Port A */ # define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ @@ -121,10 +121,10 @@ * - RAM for BD/Buffers is on the 60x Bus (see 28-13) * - Enable Full Duplex in FSMR */ -# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) +# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) +# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) +# define CONFIG_SYS_CPMFCR_RAMTYPE 0 +# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) # define MDIO_PORT 0 /* Port A */ # define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ @@ -252,53 +252,53 @@ /* * Hymod specific configurable options */ -#undef CFG_HYMOD_DBLEDS /* walk mezz board LEDs */ +#undef CONFIG_SYS_HYMOD_DBLEDS /* walk mezz board LEDs */ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ -#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ +#define CONFIG_SYS_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0x7e +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0x7e /* these are for the ST M24C02 2kbit serial i2c eeprom */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */ -#define CFG_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */ /* * standard dtt sensor configuration - bottom bit will determine local or * remote sensor of the ADM1021, the rest determines index into - * CFG_DTT_ADM1021 array below. + * CONFIG_SYS_DTT_ADM1021 array below. * * On HYMOD board, the remote sensor should be connected to the MPC8260 * temperature diode thingy, but an errata said this didn't work and @@ -323,7 +323,7 @@ * - local temp sensor enabled, min set to 0 deg, max set to 85 deg * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above) */ -#define CFG_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } } +#define CONFIG_SYS_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } } /* * Low Level Configuration Settings @@ -334,86 +334,86 @@ /*----------------------------------------------------------------------- * Hard Reset Configuration Words * - * if you change bits in the HRCW, you must also change the CFG_* + * if you change bits in the HRCW, you must also change the CONFIG_SYS_* * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. */ #ifdef DEBUG -#define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ +#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ HRCW_MODCK_H0010) #else -#define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ +#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ HRCW_MODCK_H0101) #endif /* no slaves so just duplicate the master hrcw */ -#define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER +#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER +#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER +#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER +#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER +#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER +#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER +#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ -#define CFG_IMMR 0xF0000000 +#define CONFIG_SYS_IMMR 0xF0000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE TEXT_BASE -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_FPGA_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_FPGA_BASE 0x80000000 /* - * unfortunately, CFG_MONITOR_LEN must include the + * unfortunately, CONFIG_SYS_MONITOR_LEN must include the * (very large i.e. 256kB) environment flash sector */ -#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ +#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ #define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ -#define CONFIG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) +#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ +#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ #endif /*----------------------------------------------------------------------- @@ -426,14 +426,14 @@ * * HID1 has only read-only information - nothing to set. */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ +#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ HID0_IFEM|HID0_ABE) #ifdef DEBUG -#define CFG_HID0_FINAL 0 +#define CONFIG_SYS_HID0_FINAL 0 #else -#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) +#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) #endif -#define CFG_HID2 0 +#define CONFIG_SYS_HID2 0 /*----------------------------------------------------------------------- * RMR - Reset Mode Register 5-5 @@ -441,22 +441,22 @@ * turn on Checkstop Reset Enable */ #ifdef DEBUG -#define CFG_RMR 0 +#define CONFIG_SYS_RMR 0 #else -#define CFG_RMR RMR_CSRE +#define CONFIG_SYS_RMR RMR_CSRE #endif /*----------------------------------------------------------------------- * BCR - Bus Configuration 4-25 *----------------------------------------------------------------------- */ -#define CFG_BCR (BCR_ETM) +#define CONFIG_SYS_BCR (BCR_ETM) /*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration 4-31 *----------------------------------------------------------------------- */ -#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\ +#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\ SIUMCR_APPC10|SIUMCR_MMR11) /*----------------------------------------------------------------------- @@ -466,10 +466,10 @@ * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable */ #if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) #else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ SYPCR_SWRI|SYPCR_SWP) #endif /* CONFIG_WATCHDOG */ @@ -479,7 +479,7 @@ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, * and enable Time Counter */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) +#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 4-42 @@ -487,20 +487,20 @@ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable * Periodic timer */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) +#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) /*----------------------------------------------------------------------- * SCCR - System Clock Control 9-8 *----------------------------------------------------------------------- * Ensure DFBRG is Divide by 16 */ -#define CFG_SCCR (SCCR_DFBRG01) +#define CONFIG_SYS_SCCR (SCCR_DFBRG01) /*----------------------------------------------------------------------- * RCCR - RISC Controller Configuration 13-7 *----------------------------------------------------------------------- */ -#define CFG_RCCR 0 +#define CONFIG_SYS_RCCR 0 /* * Init Memory Controller: @@ -533,10 +533,10 @@ */ /* 32 bit, read-write, GPCM on 60x bus */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE&BRx_BA_MSK)|\ +#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\ BRx_PS_32|BRx_MS_GPCM_P|BRx_V) /* up to 32 Mb */ -#define CFG_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) /* * Bank 2 - SDRAM @@ -556,13 +556,13 @@ * address lines to be configured to the required multiplexing scheme." */ -#define CFG_SDRAM_SIZE 64 +#define CONFIG_SYS_SDRAM_SIZE 64 /* 64 bit, read-write, SDRAM on 60x bus */ -#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE&BRx_BA_MSK)|\ +#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\ BRx_PS_64|BRx_MS_SDRAM_P|BRx_V) /* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */ -#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE)|\ +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\ ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12) /* @@ -579,7 +579,7 @@ * was written is 1 clock, CAS Latency is 2. */ -#define CFG_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\ +#define CONFIG_SYS_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\ PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\ PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\ PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\ @@ -611,11 +611,11 @@ */ #ifdef DEBUG -#define CFG_PSRT 39 -#define CFG_MPTPR MPTPR_PTP_DIV8 +#define CONFIG_SYS_PSRT 39 +#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 #else -#define CFG_PSRT 31 -#define CFG_MPTPR MPTPR_PTP_DIV32 +#define CONFIG_SYS_PSRT 31 +#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 #endif /* @@ -651,7 +651,7 @@ */ /* all the bank sizes must be a power of two, greater or equal to 32768 */ -#define FPGA_MAIN_CFG_BASE (CFG_FPGA_BASE) +#define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) #define FPGA_MAIN_CFG_SIZE 32768 #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE) #define FPGA_MAIN_REG_SIZE 32768 @@ -661,36 +661,36 @@ #define FPGA_MEZZ_CFG_SIZE 32768 /* 8 bit, read-write, UPMC */ -#define CFG_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) +#define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) /* up to 32Kbyte, burst inhibit */ -#define CFG_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI) +#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI) /* 32 bit, read-write, GPCM */ -#define CFG_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V) +#define CONFIG_SYS_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V) /* up to 32Kbyte */ -#define CFG_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE)) +#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE)) /* 32 bit, read-write, UPMB */ -#define CFG_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V) +#define CONFIG_SYS_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V) /* up to 32Kbyte */ -#define CFG_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI) +#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI) /* 8 bit, write-only, UPMC */ -#define CFG_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) +#define CONFIG_SYS_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) /* up to 32Kbyte, burst inhibit */ -#define CFG_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI) +#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI) /*----------------------------------------------------------------------- * MBMR - Machine B Mode 10-27 *----------------------------------------------------------------------- */ -#define CFG_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */ +#define CONFIG_SYS_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */ /*----------------------------------------------------------------------- * MCMR - Machine C Mode 10-27 *----------------------------------------------------------------------- */ -#define CFG_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */ +#define CONFIG_SYS_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */ /* * FPGA I/O Port/Bit information |