diff options
Diffstat (limited to 'include/configs/AmigaOneG3SE.h')
| -rw-r--r-- | include/configs/AmigaOneG3SE.h | 182 |
1 files changed, 91 insertions, 91 deletions
diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h index a6e92287f..b71da1fbf 100644 --- a/include/configs/AmigaOneG3SE.h +++ b/include/configs/AmigaOneG3SE.h @@ -50,7 +50,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #undef CONFIG_CLOCKS_IN_MHZ /* clocks passed to Linux in Hz */ @@ -100,52 +100,52 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "] " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "] " /* Monitor Command Prompt */ -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -/* #undef CFG_HUSH_PARSER */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ +/* #undef CONFIG_SYS_HUSH_PARSER */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CFG_MAXARGS 64 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00500000 /* Default load address */ +#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR 0x00500000 /* Default load address */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF00000 -#define CFG_FLASH_MAX_SIZE 0x00080000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0xFFF00000 +#define CONFIG_SYS_FLASH_MAX_SIZE 0x00080000 /* Maximum amount of RAM. */ -#define CFG_MAX_RAM_SIZE 0x80000000 /* 2G */ +#define CONFIG_SYS_MAX_RAM_SIZE 0x80000000 /* 2G */ -#define CFG_RESET_ADDRESS 0xFFF00100 +#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 -#define CFG_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (768 << 10) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (2500 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* Reserve 512 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve 128 kB for malloc() */ -#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \ - CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE -#define CFG_RAMBOOT +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \ + CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE +#define CONFIG_SYS_RAMBOOT #else -#undef CFG_RAMBOOT +#undef CONFIG_SYS_RAMBOOT #endif -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area @@ -154,88 +154,88 @@ /* Size in bytes reserved for initial data */ /* HJF: used to be 0x400000 */ -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x8000 -#define CFG_GBL_DATA_SIZE 128 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_END 0x8000 +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CFG_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_LOCK /* * Temporary buffer for serial data until the real serial driver * is initialised (memtest will destroy this buffer) */ -#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR -#define CFG_SCONSOLE_SIZE 0x0002000 +#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000 /* SDRAM 0 - 256MB */ -/*HJF: #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_DBAT0U CFG_IBAT0U*/ +/*HJF: #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U*/ -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_DBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) /* PCI Range */ -#define CFG_DBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) /* HJF: -#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW) -#define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) -#define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR) | BATL_PP_RW) +#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) +#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP) */ /* Init RAM in the CPU DCache (no backing memory) */ -#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) /* This used to be commented out */ -#define CFG_IBAT2L CFG_DBAT2L +#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L /* This here too */ -#define CFG_IBAT2U CFG_DBAT2U +#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U /* I/O and PCI memory at 0xf0000000 */ -#define CFG_DBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) */ -#define CFG_HZ 1000 -#define CFG_BUS_HZ 133000000 /* bus speed - 100 mhz */ -#define CFG_CPU_CLK 133000000 -#define CFG_BUS_CLK 133000000 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_BUS_HZ 133000000 /* bus speed - 100 mhz */ +#define CONFIG_SYS_CPU_CLK 133000000 +#define CONFIG_SYS_BUS_CLK 133000000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 8 /* Max number of sectors in one bank */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 8 /* Max number of sectors in one bank */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ /* * Environment is stored in NVRAM. @@ -247,22 +247,22 @@ */ #define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment. See comment above */ -#define CFG_CONSOLE_IS_IN_ENV 1 /* stdin/stdout/stderr are in environment */ -#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* stdin/stdout/stderr are in environment */ +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 #define CONFIG_ENV_OVERWRITE 1 /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 +#define CONFIG_SYS_CACHELINE_SIZE 32 #if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /* * L2 cache */ -#define CFG_L2 +#define CONFIG_SYS_L2 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #define L2_ENABLE (L2_INIT | L2CR_L2E) @@ -281,26 +281,26 @@ */ #define CONFIG_ATAPI 1 -#define CFG_IDE_MAXBUS 2 -#define CFG_IDE_MAXDEVICE 4 +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 4 #define CONFIG_ISO_PARTITION 1 -#define CFG_ATA_BASE_ADDR 0xFE000000 /* was: via_get_base_addr() */ -#define CFG_ATA_IDE0_OFFSET 0x1F0 -#define CFG_ATA_IDE1_OFFSET 0x170 +#define CONFIG_SYS_ATA_BASE_ADDR 0xFE000000 /* was: via_get_base_addr() */ +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1F0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 -#define CFG_ATA_REG_OFFSET 0 -#define CFG_ATA_DATA_OFFSET 0 -#define CFG_ATA_ALT_OFFSET 0x0200 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 /*----------------------------------------------------------------------- * Disk-On-Chip configuration */ -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ +#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ -#define CFG_DOC_SUPPORT_2000 -#undef CFG_DOC_SUPPORT_MILLENNIUM +#define CONFIG_SYS_DOC_SUPPORT_2000 +#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM /*----------------------------------------------------------------------- RTC @@ -311,16 +311,16 @@ * NS16550 Configuration */ -#define CFG_NS16550 +#define CONFIG_SYS_NS16550 -#define CFG_NS16550_COM1 0xFE0003F8 -#define CFG_NS16550_COM2 0xFE0002F8 +#define CONFIG_SYS_NS16550_COM1 0xFE0003F8 +#define CONFIG_SYS_NS16550_COM2 0xFE0002F8 -#define CFG_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_REG_SIZE 1 /* base address for ISA I/O */ -#define CFG_ISA_IO_BASE_ADDRESS 0xFE000000 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xFE000000 /* ISA Interrupt stuff (taken from JWL) */ @@ -346,7 +346,7 @@ */ #define CONFIG_NET_MULTI -#define CFG_BOARD_ASM_INIT +#define CONFIG_SYS_BOARD_ASM_INIT #define CONFIG_LAST_STAGE_INIT /* #define CONFIG_ETHADDR 00:09:D2:10:00:76 */ @@ -363,7 +363,7 @@ #define CONFIG_USB_UHCI 1 #define CONFIG_USB_STORAGE 1 #define CONFIG_USB_KEYBOARD 1 -#define CFG_DEVICE_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */ +#define CONFIG_SYS_DEVICE_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */ /* * Autoboot stuff |