diff options
Diffstat (limited to 'include/commproc.h')
| -rw-r--r-- | include/commproc.h | 62 |
1 files changed, 43 insertions, 19 deletions
diff --git a/include/commproc.h b/include/commproc.h index 42db99897..159c294f8 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -1100,6 +1100,34 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */ #endif /* CONFIG_MHPC */ +/*** NETVIA *******************************************************/ + +#if defined(CONFIG_NETVIA) +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC2 use. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ +#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ + +#define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ +#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ + +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to + * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + */ +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002f00) + +#endif /* CONFIG_NETVIA */ + /*** RPXCLASSIC *****************************************************/ #ifdef CONFIG_RPXCLASSIC @@ -1309,31 +1337,27 @@ typedef struct scc_enet { # endif /* CONFIG_FEC_ENET */ #endif /* CONFIG_TQM860L, CONFIG_TQM855L */ -#if defined(CONFIG_NETVIA) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. +/*** V37 **********************************************************/ + +#ifdef CONFIG_V37 +/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of + * this may be unique to the Marel V37 configuration. + * Note TENA is on Port B. */ #define PROFF_ENET PROFF_SCC2 #define CPM_CR_ENET CPM_CR_CH_SCC2 #define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ - -#define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ -#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ +#define PA_ENET_RXD ((ushort)0x0004) +#define PA_ENET_TXD ((ushort)0x0008) +#define PA_ENET_TCLK ((ushort)0x0400) +#define PA_ENET_RCLK ((ushort)0x0200) +#define PB_ENET_TENA ((uint)0x00002000) +#define PC_ENET_CLSN ((ushort)0x0040) +#define PC_ENET_RENA ((ushort)0x0080) -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ #define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002f00) - -#endif /* CONFIG_NETVIA */ +#define SICR_ENET_CLKRT ((uint)0x00002e00) +#endif /* CONFIG_V37 */ /*********************************************************************/ |