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-rw-r--r--include/asm-arm/arch-omap3/cpu.h4
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h2
2 files changed, 3 insertions, 3 deletions
diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
index 7a032b828..8ab2e391b 100644
--- a/include/asm-arm/arch-omap3/cpu.h
+++ b/include/asm-arm/arch-omap3/cpu.h
@@ -120,9 +120,9 @@ struct gpmc {
u8 res4[0xC];
u32 config; /* 0x50 */
u32 status; /* 0x54 */
- u8 res5[0x8];
+ u8 res5[0x8]; /* 0x58 */
struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
- u8 res6[0x18];
+ u8 res6[0x14]; /* 0x1E0 */
u32 ecc_config; /* 0x1F4 */
u32 ecc_control; /* 0x1F8 */
u32 ecc_size_config; /* 0x1FC */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index f34af1972..a25d4c512 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1094,7 +1094,7 @@ typedef void (*ExcpHndlr) (void) ;
#define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */
#define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */
-#define OSCR_CLK_FREQ 3.250 /* MHz */
+#define OSCR_CLK_FREQ 3250 /* kHz = 3.25 MHz */
#endif /* CONFIG_CPU_MONAHANS */
#define OSSR_M4 (1 << 4) /* Match status channel 4 */