diff options
Diffstat (limited to 'drivers')
96 files changed, 2395 insertions, 976 deletions
diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index dbb5e8cce..3b2ed6e10 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -52,10 +52,6 @@ /* Length of the BIOS image */ #define MAX_BIOSLEN (128 * 1024L) -/* Define some useful types and macros */ -#define true 1 -#define false 0 - /* Place to save PCI BAR's that we change and later restore */ static u32 saveROMBaseAddress; static u32 saveBaseAddress10; @@ -242,7 +238,7 @@ pcidev - PCI device info for the video card on the bus to boot VGAInfo - BIOS emulator VGA info structure RETURNS: -True if successfully initialised, false if not. +true if successfully initialised, false if not. REMARKS: Loads and POST's the display controllers BIOS, directly from the BIOS @@ -295,7 +291,7 @@ static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) PARAMETERS: pcidev - PCI device info for the video card on the bus to boot pVGAInfo - Place to return VGA info structure is requested -cleanUp - True to clean up on exit, false to leave emulator active +cleanUp - true to clean up on exit, false to leave emulator active REMARKS: Boots the PCI/AGP video card on the bus using the Video ROM BIOS image diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c index 84724b712..ad88a53f0 100644 --- a/drivers/bios_emulator/besys.c +++ b/drivers/bios_emulator/besys.c @@ -47,6 +47,8 @@ * ****************************************************************************/ +#define __io +#include <asm/io.h> #include <common.h> #include "biosemui.h" diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c index 7cf48792e..bcc192fb2 100644 --- a/drivers/bios_emulator/bios.c +++ b/drivers/bios_emulator/bios.c @@ -41,6 +41,8 @@ * ****************************************************************************/ +#define __io +#include <asm/io.h> #include <common.h> #include "biosemui.h" diff --git a/drivers/bios_emulator/include/biosemu.h b/drivers/bios_emulator/include/biosemu.h index 13cb3170c..e92e96e82 100644 --- a/drivers/bios_emulator/include/biosemu.h +++ b/drivers/bios_emulator/include/biosemu.h @@ -127,9 +127,9 @@ biosmem_limit - Limit of the BIOS image busmem_base - Base of the VGA bus memory timer - Timer used to emulate PC timer ports timer0 - Latched value for timer 0 -timer0Latched - True if timer 0 value was just latched +timer0Latched - true if timer 0 value was just latched timer2 - Current value for timer 2 -emulateVGA - True to emulate VGA I/O and memory accesses +emulateVGA - true to emulate VGA I/O and memory accesses ****************************************************************************/ typedef struct { diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index 6417d0999..2fa8050f6 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -309,7 +309,7 @@ void x86emu_single_step(void) case 'P': noDecode = (noDecode) ? 0 : 1; printk("Toggled decoding to %s\n", - (noDecode) ? "FALSE" : "TRUE"); + (noDecode) ? "false" : "true"); break; case 't': case 0: diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 8c785ae92..cab7f8c7a 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -865,14 +865,14 @@ int scsi_exec(ccb *pccb) break; default: printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); - return FALSE; + return false; } if (ret) { debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); - return FALSE; + return false; } - return TRUE; + return true; } diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c index 28d87f538..49288a7ba 100644 --- a/drivers/block/sata_dwc.c +++ b/drivers/block/sata_dwc.c @@ -360,7 +360,7 @@ int init_sata(int dev) if (status == 0x7f) { printf("Hard Disk not found.\n"); dev_state = SATA_NODEVICE; - rc = FALSE; + rc = false; return rc; } @@ -381,7 +381,7 @@ int init_sata(int dev) printf("** TimeOUT **\n"); dev_state = SATA_NODEVICE; - rc = FALSE; + rc = false; return rc; } if ((i >= 100) && ((i % 100) == 0)) @@ -458,7 +458,7 @@ static int sata_dwc_softreset(struct ata_port *ap) } else { printf("No device found\n"); dev_state = SATA_NODEVICE; - return FALSE; + return false; } tmp = ATA_DEVICE_OBS; @@ -737,7 +737,7 @@ static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class, status = ata_busy_wait(ap, ATA_BUSY, 30000); if (status & ATA_BUSY) { printf("BSY = 0 check. timeout.\n"); - rc = FALSE; + rc = false; return rc; } @@ -987,7 +987,7 @@ unsigned ata_exec_internal(struct ata_device *dev, status = ata_busy_wait(ap, ATA_BUSY, 300000); if (status & ATA_BUSY) { printf("BSY = 0 check. timeout.\n"); - rc = FALSE; + rc = false; return rc; } @@ -997,7 +997,7 @@ unsigned ata_exec_internal(struct ata_device *dev, tag = ATA_TAG_INTERNAL; if (test_and_set_bit(tag, &ap->qc_allocated)) { - rc = FALSE; + rc = false; return rc; } @@ -1656,14 +1656,14 @@ static int check_sata_dev_state(void) ret = ata_dev_read_sectors(pdata, datalen, 0, 1); - if (ret == TRUE) + if (ret == true) break; i++; if (i > (ATA_RESET_TIME * 100)) { printf("** TimeOUT **\n"); dev_state = SATA_NODEVICE; - return FALSE; + return false; } if ((i >= 100) && ((i % 100) == 0)) @@ -1672,7 +1672,7 @@ static int check_sata_dev_state(void) dev_state = SATA_READY; - return TRUE; + return true; } static unsigned int ata_dev_set_feature(struct ata_device *dev, @@ -1772,7 +1772,7 @@ ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer) blks = 0; } - if (ata_dev_read_sectors(pdata, datalen, block, n_block) != TRUE) { + if (ata_dev_read_sectors(pdata, datalen, block, n_block) != true) { printf("sata_dwc : Hard disk read error.\n"); blkcnt -= blks; break; @@ -1795,7 +1795,7 @@ static int ata_dev_read_sectors(unsigned char *pdata, unsigned long datalen, int may_fallback = 1; if (dev_state == SATA_ERROR) - return FALSE; + return false; ata_dev_select(ap, dev->devno, 1, 1); @@ -1893,11 +1893,11 @@ retry: goto err_out; } - return TRUE; + return true; err_out: printf("failed to READ SECTORS (%s, err_mask=0x%x)\n", reason, err_mask); - return FALSE; + return false; } #if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48) @@ -1946,7 +1946,7 @@ ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer) blks = 0; } - if (ata_dev_write_sectors(pdata, datalen, block, n_block) != TRUE) { + if (ata_dev_write_sectors(pdata, datalen, block, n_block) != true) { printf("sata_dwc : Hard disk read error.\n"); blkcnt -= blks; break; @@ -1969,7 +1969,7 @@ static int ata_dev_write_sectors(unsigned char* pdata, unsigned long datalen, int may_fallback = 1; if (dev_state == SATA_ERROR) - return FALSE; + return false; ata_dev_select(ap, dev->devno, 1, 1); @@ -2068,9 +2068,9 @@ retry: goto err_out; } - return TRUE; + return true; err_out: printf("failed to WRITE SECTORS (%s, err_mask=0x%x)\n", reason, err_mask); - return FALSE; + return false; } diff --git a/drivers/block/sata_dwc.h b/drivers/block/sata_dwc.h index 204d644c0..e4e4ab112 100644 --- a/drivers/block/sata_dwc.h +++ b/drivers/block/sata_dwc.h @@ -467,11 +467,4 @@ struct ata_port { unsigned char *pdata; }; -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #endif diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c index 564aa9838..656683a10 100644 --- a/drivers/block/sym53c8xx.c +++ b/drivers/block/sym53c8xx.c @@ -764,9 +764,9 @@ int scsi_exec(ccb *pccb) retry: scsi_issue(pccb); if(pccb->contr_stat!=SIR_COMPLETE) - return FALSE; + return false; if(pccb->status==S_GOOD) - return TRUE; + return true; if(pccb->status==S_CHECK_COND) { /* check condition */ for(i=0;i<16;i++) tmpcmd[i]=pccb->cmd[i]; @@ -797,12 +797,12 @@ retry: case SENSE_NO_SENSE: case SENSE_RECOVERED_ERROR: /* seems to be ok */ - return TRUE; + return true; break; case SENSE_NOT_READY: if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) { /* if device is not in process of becoming ready */ - return FALSE; + return false; break; } /* else fall through */ case SENSE_UNIT_ATTENTION: @@ -814,13 +814,13 @@ retry: goto retry; } PRINTF("Target %d not ready, %d retried\n",pccb->target,retrycnt); - return FALSE; + return false; default: - return FALSE; + return false; } } PRINTF("Status = %X\n",pccb->status); - return FALSE; + return false; } diff --git a/drivers/dfu/Makefile b/drivers/dfu/Makefile index 7b717bce2..153095d71 100644 --- a/drivers/dfu/Makefile +++ b/drivers/dfu/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)libdfu.o COBJS-$(CONFIG_DFU_FUNCTION) += dfu.o COBJS-$(CONFIG_DFU_MMC) += dfu_mmc.o +COBJS-$(CONFIG_DFU_NAND) += dfu_nand.o SRCS := $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index e8477fb7c..6af6890d0 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -44,90 +44,232 @@ static int dfu_find_alt_num(const char *s) static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE) dfu_buf[DFU_DATA_BUF_SIZE]; +static int dfu_write_buffer_drain(struct dfu_entity *dfu) +{ + long w_size; + int ret; + + /* flush size? */ + w_size = dfu->i_buf - dfu->i_buf_start; + if (w_size == 0) + return 0; + + /* update CRC32 */ + dfu->crc = crc32(dfu->crc, dfu->i_buf_start, w_size); + + ret = dfu->write_medium(dfu, dfu->offset, dfu->i_buf_start, &w_size); + if (ret) + debug("%s: Write error!\n", __func__); + + /* point back */ + dfu->i_buf = dfu->i_buf_start; + + /* update offset */ + dfu->offset += w_size; + + puts("#"); + + return ret; +} + int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) { - static unsigned char *i_buf; - static int i_blk_seq_num; - long w_size = 0; int ret = 0; + int tret; - debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x i_buf: 0x%p\n", - __func__, dfu->name, buf, size, blk_seq_num, i_buf); + debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x offset: 0x%llx bufoffset: 0x%x\n", + __func__, dfu->name, buf, size, blk_seq_num, dfu->offset, + dfu->i_buf - dfu->i_buf_start); - if (blk_seq_num == 0) { - i_buf = dfu_buf; - i_blk_seq_num = 0; + if (!dfu->inited) { + /* initial state */ + dfu->crc = 0; + dfu->offset = 0; + dfu->bad_skip = 0; + dfu->i_blk_seq_num = 0; + dfu->i_buf_start = dfu_buf; + dfu->i_buf_end = dfu_buf + sizeof(dfu_buf); + dfu->i_buf = dfu->i_buf_start; + + dfu->inited = 1; } - if (i_blk_seq_num++ != blk_seq_num) { + if (dfu->i_blk_seq_num != blk_seq_num) { printf("%s: Wrong sequence number! [%d] [%d]\n", - __func__, i_blk_seq_num, blk_seq_num); + __func__, dfu->i_blk_seq_num, blk_seq_num); + return -1; + } + + /* DFU 1.1 standard says: + * The wBlockNum field is a block sequence number. It increments each + * time a block is transferred, wrapping to zero from 65,535. It is used + * to provide useful context to the DFU loader in the device." + * + * This means that it's a 16 bit counter that roll-overs at + * 0xffff -> 0x0000. By having a typical 4K transfer block + * we roll-over at exactly 256MB. Not very fun to debug. + * + * Handling rollover, and having an inited variable, + * makes things work. + */ + + /* handle rollover */ + dfu->i_blk_seq_num = (dfu->i_blk_seq_num + 1) & 0xffff; + + /* flush buffer if overflow */ + if ((dfu->i_buf + size) > dfu->i_buf_end) { + tret = dfu_write_buffer_drain(dfu); + if (ret == 0) + ret = tret; + } + + /* we should be in buffer now (if not then size too large) */ + if ((dfu->i_buf + size) > dfu->i_buf_end) { + printf("%s: Wrong size! [%d] [%d] - %d\n", + __func__, dfu->i_blk_seq_num, blk_seq_num, size); return -1; } - memcpy(i_buf, buf, size); - i_buf += size; + memcpy(dfu->i_buf, buf, size); + dfu->i_buf += size; + + /* if end or if buffer full flush */ + if (size == 0 || (dfu->i_buf + size) > dfu->i_buf_end) { + tret = dfu_write_buffer_drain(dfu); + if (ret == 0) + ret = tret; + } + /* end? */ if (size == 0) { - /* Integrity check (if needed) */ - debug("%s: %s %d [B] CRC32: 0x%x\n", __func__, dfu->name, - i_buf - dfu_buf, crc32(0, dfu_buf, i_buf - dfu_buf)); + /* Now try and flush to the medium if needed. */ + if (dfu->flush_medium) + ret = dfu->flush_medium(dfu); + printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc); - w_size = i_buf - dfu_buf; - ret = dfu->write_medium(dfu, dfu_buf, &w_size); - if (ret) - debug("%s: Write error!\n", __func__); + /* clear everything */ + dfu->crc = 0; + dfu->offset = 0; + dfu->i_blk_seq_num = 0; + dfu->i_buf_start = dfu_buf; + dfu->i_buf_end = dfu_buf + sizeof(dfu_buf); + dfu->i_buf = dfu->i_buf_start; + + dfu->inited = 0; - i_blk_seq_num = 0; - i_buf = NULL; - return ret; } - return ret; + return ret = 0 ? size : ret; +} + +static int dfu_read_buffer_fill(struct dfu_entity *dfu, void *buf, int size) +{ + long chunk; + int ret, readn; + + readn = 0; + while (size > 0) { + /* get chunk that can be read */ + chunk = min(size, dfu->b_left); + /* consume */ + if (chunk > 0) { + memcpy(buf, dfu->i_buf, chunk); + dfu->crc = crc32(dfu->crc, buf, chunk); + dfu->i_buf += chunk; + dfu->b_left -= chunk; + size -= chunk; + buf += chunk; + readn += chunk; + } + + /* all done */ + if (size > 0) { + /* no more to read */ + if (dfu->r_left == 0) + break; + + dfu->i_buf = dfu->i_buf_start; + dfu->b_left = dfu->i_buf_end - dfu->i_buf_start; + + /* got to read, but buffer is empty */ + if (dfu->b_left > dfu->r_left) + dfu->b_left = dfu->r_left; + ret = dfu->read_medium(dfu, dfu->offset, dfu->i_buf, + &dfu->b_left); + if (ret != 0) { + debug("%s: Read error!\n", __func__); + return ret; + } + dfu->offset += dfu->b_left; + dfu->r_left -= dfu->b_left; + + puts("#"); + } + } + + return readn; } int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) { - static unsigned char *i_buf; - static int i_blk_seq_num; - static long r_size; - static u32 crc; int ret = 0; debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x i_buf: 0x%p\n", - __func__, dfu->name, buf, size, blk_seq_num, i_buf); + __func__, dfu->name, buf, size, blk_seq_num, dfu->i_buf); + + if (!dfu->inited) { + ret = dfu->read_medium(dfu, 0, buf, &dfu->r_left); + if (ret != 0) { + debug("%s: failed to get r_left\n", __func__); + return ret; + } - if (blk_seq_num == 0) { - i_buf = dfu_buf; - ret = dfu->read_medium(dfu, i_buf, &r_size); - debug("%s: %s %ld [B]\n", __func__, dfu->name, r_size); - i_blk_seq_num = 0; - /* Integrity check (if needed) */ - crc = crc32(0, dfu_buf, r_size); + debug("%s: %s %ld [B]\n", __func__, dfu->name, dfu->r_left); + + dfu->i_blk_seq_num = 0; + dfu->crc = 0; + dfu->offset = 0; + dfu->i_buf_start = dfu_buf; + dfu->i_buf_end = dfu_buf + sizeof(dfu_buf); + dfu->i_buf = dfu->i_buf_start; + dfu->b_left = 0; + + dfu->bad_skip = 0; + + dfu->inited = 1; } - if (i_blk_seq_num++ != blk_seq_num) { + if (dfu->i_blk_seq_num != blk_seq_num) { printf("%s: Wrong sequence number! [%d] [%d]\n", - __func__, i_blk_seq_num, blk_seq_num); + __func__, dfu->i_blk_seq_num, blk_seq_num); return -1; } + /* handle rollover */ + dfu->i_blk_seq_num = (dfu->i_blk_seq_num + 1) & 0xffff; - if (r_size >= size) { - memcpy(buf, i_buf, size); - i_buf += size; - r_size -= size; - return size; - } else { - memcpy(buf, i_buf, r_size); - i_buf += r_size; - debug("%s: %s CRC32: 0x%x\n", __func__, dfu->name, crc); - puts("UPLOAD ... done\nCtrl+C to exit ...\n"); + ret = dfu_read_buffer_fill(dfu, buf, size); + if (ret < 0) { + printf("%s: Failed to fill buffer\n", __func__); + return -1; + } - i_buf = NULL; - i_blk_seq_num = 0; - crc = 0; - return r_size; + if (ret < size) { + debug("%s: %s CRC32: 0x%x\n", __func__, dfu->name, dfu->crc); + puts("\nUPLOAD ... done\nCtrl+C to exit ...\n"); + + dfu->i_blk_seq_num = 0; + dfu->crc = 0; + dfu->offset = 0; + dfu->i_buf_start = dfu_buf; + dfu->i_buf_end = dfu_buf + sizeof(dfu_buf); + dfu->i_buf = dfu->i_buf_start; + dfu->b_left = 0; + + dfu->bad_skip = 0; + + dfu->inited = 0; } + return ret; } @@ -147,6 +289,9 @@ static int dfu_fill_entity(struct dfu_entity *dfu, char *s, int alt, if (strcmp(interface, "mmc") == 0) { if (dfu_fill_entity_mmc(dfu, s)) return -1; + } else if (strcmp(interface, "nand") == 0) { + if (dfu_fill_entity_nand(dfu, s)) + return -1; } else { printf("%s: Device %s not (yet) supported!\n", __func__, interface); diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 083d74591..e2f397840 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -22,6 +22,7 @@ #include <common.h> #include <malloc.h> #include <errno.h> +#include <div64.h> #include <dfu.h> enum dfu_mmc_op { @@ -29,32 +30,51 @@ enum dfu_mmc_op { DFU_OP_WRITE, }; +static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE) + dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE]; +static long dfu_file_buf_len; + static int mmc_block_op(enum dfu_mmc_op op, struct dfu_entity *dfu, - void *buf, long *len) + u64 offset, void *buf, long *len) { char cmd_buf[DFU_CMD_BUF_SIZE]; + u32 blk_start, blk_count; - sprintf(cmd_buf, "mmc %s 0x%x %x %x", - op == DFU_OP_READ ? "read" : "write", - (unsigned int) buf, - dfu->data.mmc.lba_start, - dfu->data.mmc.lba_size); + /* + * We must ensure that we work in lba_blk_size chunks, so ALIGN + * this value. + */ + *len = ALIGN(*len, dfu->data.mmc.lba_blk_size); - if (op == DFU_OP_READ) - *len = dfu->data.mmc.lba_blk_size * dfu->data.mmc.lba_size; + blk_start = dfu->data.mmc.lba_start + + (u32)lldiv(offset, dfu->data.mmc.lba_blk_size); + blk_count = *len / dfu->data.mmc.lba_blk_size; + if (blk_start + blk_count > + dfu->data.mmc.lba_start + dfu->data.mmc.lba_size) { + puts("Request would exceed designated area!\n"); + return -EINVAL; + } + + sprintf(cmd_buf, "mmc %s %p %x %x", + op == DFU_OP_READ ? "read" : "write", + buf, blk_start, blk_count); debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); return run_command(cmd_buf, 0); } -static inline int mmc_block_write(struct dfu_entity *dfu, void *buf, long *len) +static int mmc_file_buffer(struct dfu_entity *dfu, void *buf, long *len) { - return mmc_block_op(DFU_OP_WRITE, dfu, buf, len); -} + if (dfu_file_buf_len + *len > CONFIG_SYS_DFU_MAX_FILE_SIZE) { + dfu_file_buf_len = 0; + return -EINVAL; + } -static inline int mmc_block_read(struct dfu_entity *dfu, void *buf, long *len) -{ - return mmc_block_op(DFU_OP_READ, dfu, buf, len); + /* Add to the current buffer. */ + memcpy(dfu_file_buf + dfu_file_buf_len, buf, *len); + dfu_file_buf_len += *len; + + return 0; } static int mmc_file_op(enum dfu_mmc_op op, struct dfu_entity *dfu, @@ -66,20 +86,23 @@ static int mmc_file_op(enum dfu_mmc_op op, struct dfu_entity *dfu, switch (dfu->layout) { case DFU_FS_FAT: - sprintf(cmd_buf, "fat%s mmc %d:%d 0x%x %s %lx", + sprintf(cmd_buf, "fat%s mmc %d:%d 0x%x %s", op == DFU_OP_READ ? "load" : "write", dfu->data.mmc.dev, dfu->data.mmc.part, - (unsigned int) buf, dfu->name, *len); + (unsigned int) buf, dfu->name); + if (op == DFU_OP_WRITE) + sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len); break; case DFU_FS_EXT4: - sprintf(cmd_buf, "ext4%s mmc %d:%d /%s 0x%x %ld", + sprintf(cmd_buf, "ext4%s mmc %d:%d 0x%x /%s", op == DFU_OP_READ ? "load" : "write", dfu->data.mmc.dev, dfu->data.mmc.part, - dfu->name, (unsigned int) buf, *len); + (unsigned int) buf, dfu->name); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, dfu_get_layout(dfu->layout)); + return -1; } debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); @@ -102,27 +125,18 @@ static int mmc_file_op(enum dfu_mmc_op op, struct dfu_entity *dfu, return ret; } -static inline int mmc_file_write(struct dfu_entity *dfu, void *buf, long *len) -{ - return mmc_file_op(DFU_OP_WRITE, dfu, buf, len); -} - -static inline int mmc_file_read(struct dfu_entity *dfu, void *buf, long *len) -{ - return mmc_file_op(DFU_OP_READ, dfu, buf, len); -} - -int dfu_write_medium_mmc(struct dfu_entity *dfu, void *buf, long *len) +int dfu_write_medium_mmc(struct dfu_entity *dfu, + u64 offset, void *buf, long *len) { int ret = -1; switch (dfu->layout) { case DFU_RAW_ADDR: - ret = mmc_block_write(dfu, buf, len); + ret = mmc_block_op(DFU_OP_WRITE, dfu, offset, buf, len); break; case DFU_FS_FAT: case DFU_FS_EXT4: - ret = mmc_file_write(dfu, buf, len); + ret = mmc_file_buffer(dfu, buf, len); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -132,17 +146,34 @@ int dfu_write_medium_mmc(struct dfu_entity *dfu, void *buf, long *len) return ret; } -int dfu_read_medium_mmc(struct dfu_entity *dfu, void *buf, long *len) +int dfu_flush_medium_mmc(struct dfu_entity *dfu) +{ + int ret = 0; + + if (dfu->layout != DFU_RAW_ADDR) { + /* Do stuff here. */ + ret = mmc_file_op(DFU_OP_WRITE, dfu, &dfu_file_buf, + &dfu_file_buf_len); + + /* Now that we're done */ + dfu_file_buf_len = 0; + } + + return ret; +} + +int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, + long *len) { int ret = -1; switch (dfu->layout) { case DFU_RAW_ADDR: - ret = mmc_block_read(dfu, buf, len); + ret = mmc_block_op(DFU_OP_READ, dfu, offset, buf, len); break; case DFU_FS_FAT: case DFU_FS_EXT4: - ret = mmc_file_read(dfu, buf, len); + ret = mmc_file_op(DFU_OP_READ, dfu, buf, len); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -181,14 +212,15 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) mmc = find_mmc_device(dev); if (mmc == NULL || mmc_init(mmc)) { - printf("%s: could not find mmc device #%d!\n", __func__, dev); + printf("%s: could not find mmc device #%d!\n", + __func__, dev); return -ENODEV; } blk_dev = &mmc->block_dev; if (get_partition_info(blk_dev, part, &partinfo) != 0) { printf("%s: could not find partition #%d on mmc device #%d!\n", - __func__, part, dev); + __func__, part, dev); return -ENODEV; } @@ -208,6 +240,10 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) dfu->read_medium = dfu_read_medium_mmc; dfu->write_medium = dfu_write_medium_mmc; + dfu->flush_medium = dfu_flush_medium_mmc; + + /* initial state */ + dfu->inited = 0; return 0; } diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c new file mode 100644 index 000000000..7dc89b2f2 --- /dev/null +++ b/drivers/dfu/dfu_nand.c @@ -0,0 +1,187 @@ +/* + * dfu_nand.c -- DFU for NAND routines. + * + * Copyright (C) 2012-2013 Texas Instruments, Inc. + * + * Based on dfu_mmc.c which is: + * Copyright (C) 2012 Samsung Electronics + * author: Lukasz Majewski <l.majewski@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <div64.h> +#include <dfu.h> +#include <linux/mtd/mtd.h> +#include <jffs2/load_kernel.h> +#include <nand.h> + +enum dfu_nand_op { + DFU_OP_READ = 1, + DFU_OP_WRITE, +}; + +static int nand_block_op(enum dfu_nand_op op, struct dfu_entity *dfu, + u64 offset, void *buf, long *len) +{ + loff_t start, lim; + size_t count, actual; + int ret; + nand_info_t *nand; + + /* if buf == NULL return total size of the area */ + if (buf == NULL) { + *len = dfu->data.nand.size; + return 0; + } + + start = dfu->data.nand.start + offset + dfu->bad_skip; + lim = dfu->data.nand.start + dfu->data.nand.size - start; + count = *len; + + if (nand_curr_device < 0 || + nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || + !nand_info[nand_curr_device].name) { + printf("%s: invalid nand device\n", __func__); + return -1; + } + + nand = &nand_info[nand_curr_device]; + + if (op == DFU_OP_READ) + ret = nand_read_skip_bad(nand, start, &count, &actual, + lim, buf); + else + ret = nand_write_skip_bad(nand, start, &count, &actual, + lim, buf, 0); + + if (ret != 0) { + printf("%s: nand_%s_skip_bad call failed at %llx!\n", + __func__, op == DFU_OP_READ ? "read" : "write", + start); + return ret; + } + + /* + * Find out where we stopped writing data. This can be deeper into + * the NAND than we expected due to having to skip bad blocks. So + * we must take this into account for the next write, if any. + */ + if (actual > count) + dfu->bad_skip += actual - count; + + return ret; +} + +static inline int nand_block_write(struct dfu_entity *dfu, + u64 offset, void *buf, long *len) +{ + return nand_block_op(DFU_OP_WRITE, dfu, offset, buf, len); +} + +static inline int nand_block_read(struct dfu_entity *dfu, + u64 offset, void *buf, long *len) +{ + return nand_block_op(DFU_OP_READ, dfu, offset, buf, len); +} + +static int dfu_write_medium_nand(struct dfu_entity *dfu, + u64 offset, void *buf, long *len) +{ + int ret = -1; + + switch (dfu->layout) { + case DFU_RAW_ADDR: + ret = nand_block_write(dfu, offset, buf, len); + break; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + } + + return ret; +} + +static int dfu_read_medium_nand(struct dfu_entity *dfu, u64 offset, void *buf, + long *len) +{ + int ret = -1; + + switch (dfu->layout) { + case DFU_RAW_ADDR: + ret = nand_block_read(dfu, offset, buf, len); + break; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + } + + return ret; +} + +int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) +{ + char *st; + int ret, dev, part; + + dfu->dev_type = DFU_DEV_NAND; + st = strsep(&s, " "); + if (!strcmp(st, "raw")) { + dfu->layout = DFU_RAW_ADDR; + dfu->data.nand.start = simple_strtoul(s, &s, 16); + s++; + dfu->data.nand.size = simple_strtoul(s, &s, 16); + } else if (!strcmp(st, "part")) { + char mtd_id[32]; + struct mtd_device *mtd_dev; + u8 part_num; + struct part_info *pi; + + dfu->layout = DFU_RAW_ADDR; + + dev = simple_strtoul(s, &s, 10); + s++; + part = simple_strtoul(s, &s, 10); + + sprintf(mtd_id, "%s%d,%d", "nand", dev, part - 1); + printf("using id '%s'\n", mtd_id); + + mtdparts_init(); + + ret = find_dev_and_part(mtd_id, &mtd_dev, &part_num, &pi); + if (ret != 0) { + printf("Could not locate '%s'\n", mtd_id); + return -1; + } + + dfu->data.nand.start = pi->offset; + dfu->data.nand.size = pi->size; + + } else { + printf("%s: Memory layout (%s) not supported!\n", __func__, st); + return -1; + } + + dfu->read_medium = dfu_read_medium_nand; + dfu->write_medium = dfu_write_medium_nand; + + /* initial state */ + dfu->inited = 0; + + return 0; +} diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index 4703fc171..0ae78f92b 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -140,7 +140,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ + (*fn->config) (true, true, cookie); /* Assert nCONFIG */ udelay(2); /* T_cfg > 2us */ @@ -152,7 +152,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) return FPGA_FAIL; } - (*fn->config) (FALSE, TRUE, cookie); /* Deassert nCONFIG */ + (*fn->config) (false, true, cookie); /* Deassert nCONFIG */ udelay(2); /* T_cf2st1 < 4us */ /* Wait for nSTATUS to be released (i.e. deasserted) */ @@ -192,13 +192,13 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) i = 8; do { /* Deassert the clock */ - (*fn->clk) (FALSE, TRUE, cookie); + (*fn->clk) (false, true, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->data) ( (val & 0x01), TRUE, cookie); + (*fn->data) ((val & 0x01), true, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (true, true, cookie); CONFIG_FPGA_DELAY (); val >>= 1; i --; @@ -232,9 +232,9 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) for (i = 0; i < 12; i++) { CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ } ret_val = FPGA_SUCCESS; diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index f087d0182..8388da508 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -215,7 +215,7 @@ int altera_info( Altera_desc *desc ) static int altera_validate (Altera_desc * desc, const char *fn) { - int ret_val = FALSE; + int ret_val = false; if (desc) { if ((desc->family > min_altera_type) && @@ -223,7 +223,7 @@ static int altera_validate (Altera_desc * desc, const char *fn) if ((desc->iface > min_altera_iface_type) && (desc->iface < max_altera_iface_type)) { if (desc->size) { - ret_val = TRUE; + ret_val = true; } else { printf ("%s: NULL part size\n", fn); } diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 0773e731e..6b734c2b3 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -144,9 +144,9 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->config) (FALSE, TRUE, cookie); /* De-assert nCONFIG */ + (*fn->config) (false, true, cookie); /* De-assert nCONFIG */ udelay(100); - (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ + (*fn->config) (true, true, cookie); /* Assert nCONFIG */ udelay(2); /* T_cfg > 2us */ @@ -164,7 +164,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) /* Get ready for the burn */ CONFIG_FPGA_DELAY (); - ret = (*fn->write) (buf, bsize, TRUE, cookie); + ret = (*fn->write) (buf, bsize, true, cookie); if (ret) { puts ("** Write failed.\n"); (*fn->abort) (cookie); diff --git a/drivers/fpga/lattice.c b/drivers/fpga/lattice.c index d8b642a6b..8c3465a7f 100644 --- a/drivers/fpga/lattice.c +++ b/drivers/fpga/lattice.c @@ -275,7 +275,7 @@ signed char ispVM(void) static int lattice_validate(Lattice_desc *desc, const char *fn) { - int ret_val = FALSE; + int ret_val = false; if (desc) { if ((desc->family > min_lattice_type) && @@ -283,7 +283,7 @@ static int lattice_validate(Lattice_desc *desc, const char *fn) if ((desc->iface > min_lattice_iface_type) && (desc->iface < max_lattice_iface_type)) { if (desc->size) { - ret_val = TRUE; + ret_val = true; } else { printf("%s: NULL part size\n", fn); } diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 4bc707004..0bc400d70 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -162,11 +162,11 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ + (*fn->pgm) (true, true, cookie); /* Assert the program, commit */ /* Get ready for the burn */ CONFIG_FPGA_DELAY (); - (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ + (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */ ts = get_timer (0); /* get current time */ /* Now wait for INIT and BUSY to go high */ @@ -179,20 +179,20 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) } } while ((*fn->init) (cookie) && (*fn->busy) (cookie)); - (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */ - (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->wr) (true, true, cookie); /* Assert write, commit */ + (*fn->cs) (true, true, cookie); /* Assert chip select, commit */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ /* Load the data */ while (bytecount < bsize) { /* XXX - do we check for an Ctrl-C press in here ??? */ /* XXX - Check the error bit? */ - (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */ + (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ #ifdef CONFIG_SYS_FPGA_CHECK_BUSY ts = get_timer (0); /* get current time */ @@ -201,9 +201,9 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) * make sure we aren't busy forever... */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for BUSY to clear.\n"); @@ -220,8 +220,8 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) } CONFIG_FPGA_DELAY (); - (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */ - (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */ + (*fn->cs) (false, true, cookie); /* Deassert the chip select */ + (*fn->wr) (false, true, cookie); /* Deassert the write pin */ #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); /* terminate the dotted line */ @@ -233,9 +233,9 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) while ((*fn->done) (cookie) == FPGA_FAIL) { CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); @@ -277,15 +277,15 @@ static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) printf ("Starting Dump of FPGA Device %d...\n", cookie); - (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->cs) (true, true, cookie); /* Assert chip select, commit */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ /* dump the data */ while (bytecount < bsize) { /* XXX - do we check for an Ctrl-C press in here ??? */ - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */ #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK if (bytecount % (bsize / 40) == 0) @@ -293,9 +293,9 @@ static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) #endif } - (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */ - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->cs) (false, false, cookie); /* Deassert the chip select */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); /* terminate the dotted line */ @@ -351,7 +351,7 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ + (*fn->pgm) (true, true, cookie); /* Assert the program, commit */ /* Wait for INIT state (init low) */ ts = get_timer (0); /* get current time */ @@ -365,7 +365,7 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* Get ready for the burn */ CONFIG_FPGA_DELAY (); - (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ + (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */ ts = get_timer (0); /* get current time */ /* Now wait for INIT to go high */ @@ -390,13 +390,13 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) i = 8; do { /* Deassert the clock */ - (*fn->clk) (FALSE, TRUE, cookie); + (*fn->clk) (false, true, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val & 0x80), TRUE, cookie); + (*fn->wr) ((val & 0x80), true, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (true, true, cookie); CONFIG_FPGA_DELAY (); val <<= 1; i --; @@ -417,14 +417,14 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* now check for done signal */ ts = get_timer (0); /* get current time */ ret_val = FPGA_SUCCESS; - (*fn->wr) (TRUE, TRUE, cookie); + (*fn->wr) (true, true, cookie); while (! (*fn->done) (cookie)) { CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ putc ('*'); diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 1633a7069..c63c60529 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -166,11 +166,11 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ + (*fn->pgm) (true, true, cookie); /* Assert the program, commit */ /* Get ready for the burn */ CONFIG_FPGA_DELAY (); - (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ + (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */ ts = get_timer (0); /* get current time */ /* Now wait for INIT and BUSY to go high */ @@ -183,20 +183,20 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) } } while ((*fn->init) (cookie) && (*fn->busy) (cookie)); - (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */ - (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->wr) (true, true, cookie); /* Assert write, commit */ + (*fn->cs) (true, true, cookie); /* Assert chip select, commit */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ /* Load the data */ while (bytecount < bsize) { /* XXX - do we check for an Ctrl-C press in here ??? */ /* XXX - Check the error bit? */ - (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */ + (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ #ifdef CONFIG_SYS_FPGA_CHECK_BUSY ts = get_timer (0); /* get current time */ @@ -205,9 +205,9 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) * make sure we aren't busy forever... */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for BUSY to clear.\n"); @@ -224,8 +224,8 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) } CONFIG_FPGA_DELAY (); - (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */ - (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */ + (*fn->cs) (false, true, cookie); /* Deassert the chip select */ + (*fn->wr) (false, true, cookie); /* Deassert the write pin */ #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); /* terminate the dotted line */ @@ -239,9 +239,9 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) * make sure we aren't busy forever... */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); @@ -283,15 +283,15 @@ static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) printf ("Starting Dump of FPGA Device %d...\n", cookie); - (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->cs) (true, true, cookie); /* Assert chip select, commit */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ /* dump the data */ while (bytecount < bsize) { /* XXX - do we check for an Ctrl-C press in here ??? */ - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */ #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK if (bytecount % (bsize / 40) == 0) @@ -299,9 +299,9 @@ static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) #endif } - (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */ - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->cs) (false, false, cookie); /* Deassert the chip select */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); /* terminate the dotted line */ @@ -357,7 +357,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ + (*fn->pgm) (true, true, cookie); /* Assert the program, commit */ /* Wait for INIT state (init low) */ ts = get_timer (0); /* get current time */ @@ -373,7 +373,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* Get ready for the burn */ CONFIG_FPGA_DELAY (); - (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ + (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */ ts = get_timer (0); /* get current time */ /* Now wait for INIT to go high */ @@ -389,7 +389,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* Load the data */ if(*fn->bwr) - (*fn->bwr) (data, bsize, TRUE, cookie); + (*fn->bwr) (data, bsize, true, cookie); else { while (bytecount < bsize) { @@ -405,13 +405,13 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) i = 8; do { /* Deassert the clock */ - (*fn->clk) (FALSE, TRUE, cookie); + (*fn->clk) (false, true, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val & 0x80), TRUE, cookie); + (*fn->wr) ((val & 0x80), true, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (true, true, cookie); CONFIG_FPGA_DELAY (); val <<= 1; i --; @@ -433,16 +433,16 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* now check for done signal */ ts = get_timer (0); /* get current time */ ret_val = FPGA_SUCCESS; - (*fn->wr) (TRUE, TRUE, cookie); + (*fn->wr) (true, true, cookie); while (! (*fn->done) (cookie)) { /* XXX - we should have a check in here somewhere to * make sure we aren't busy forever... */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ putc ('*'); diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index b26d23151..3974e47d9 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -221,7 +221,7 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) * There is no maximum value for the pulse width. Check to make * sure that INIT_B goes low after assertion of PROG_B */ - (*fn->pgm) (TRUE, TRUE, cookie); + (*fn->pgm) (true, true, cookie); udelay (10); ts = get_timer (0); do { @@ -234,9 +234,9 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) } } while (!(*fn->init) (cookie)); - (*fn->pgm) (FALSE, TRUE, cookie); + (*fn->pgm) (false, true, cookie); CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (true, true, cookie); /* * Start a timer and wait for INIT_B to go high @@ -253,8 +253,8 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) } } while ((*fn->init) (cookie) && (*fn->busy) (cookie)); - (*fn->wr) (TRUE, TRUE, cookie); - (*fn->cs) (TRUE, TRUE, cookie); + (*fn->wr) (true, true, cookie); + (*fn->cs) (true, true, cookie); udelay (10000); @@ -286,15 +286,15 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) } #endif - (*fn->wdata) (data[bytecount++], TRUE, cookie); + (*fn->wdata) (data[bytecount++], true, cookie); CONFIG_FPGA_DELAY (); /* * Cycle the clock pin */ - (*fn->clk) (FALSE, TRUE, cookie); + (*fn->clk) (false, true, cookie); CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (true, true, cookie); #ifdef CONFIG_SYS_FPGA_CHECK_BUSY ts = get_timer (0); @@ -319,8 +319,8 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. */ CONFIG_FPGA_DELAY (); - (*fn->cs) (FALSE, TRUE, cookie); - (*fn->wr) (FALSE, TRUE, cookie); + (*fn->cs) (false, true, cookie); + (*fn->wr) (false, true, cookie); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); @@ -381,8 +381,8 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) printf ("Starting Dump of FPGA Device %d...\n", cookie); - (*fn->cs) (TRUE, TRUE, cookie); - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->cs) (true, true, cookie); + (*fn->clk) (true, true, cookie); while (bytecount < bsize) { #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC @@ -394,8 +394,8 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* * Cycle the clock and read the data */ - (*fn->clk) (FALSE, TRUE, cookie); - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (false, true, cookie); + (*fn->clk) (true, true, cookie); (*fn->rdata) (&(data[bytecount++]), cookie); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK if (bytecount % (bsize / 40) == 0) @@ -406,9 +406,9 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* * Deassert CS_B and cycle the clock to deselect the device. */ - (*fn->cs) (FALSE, FALSE, cookie); - (*fn->clk) (FALSE, TRUE, cookie); - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->cs) (false, false, cookie); + (*fn->clk) (false, true, cookie); + (*fn->clk) (true, true, cookie); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 4072cb414..32787b236 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -242,7 +242,7 @@ int xilinx_info (Xilinx_desc * desc) static int xilinx_validate (Xilinx_desc * desc, char *fn) { - int ret_val = FALSE; + int ret_val = false; if (desc) { if ((desc->family > min_xilinx_type) && @@ -250,7 +250,7 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn) if ((desc->iface > min_xilinx_iface_type) && (desc->iface < max_xilinx_iface_type)) { if (desc->size) { - ret_val = TRUE; + ret_val = true; } else printf ("%s: NULL part size\n", fn); } else diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 60dbb7864..cf10b0d4c 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -210,9 +210,11 @@ unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) static inline void * flash_map (flash_info_t * info, flash_sect_t sect, uint offset) { - unsigned int byte_offset = offset * info->portwidth; + unsigned int byte_offset = offset * info->portwidth / info->chipwidth; + unsigned int addr = (info->start[sect] + byte_offset); + unsigned int mask = 0xffffffff << (info->portwidth - 1); - return (void *)(info->start[sect] + byte_offset); + return (void *)(uintptr_t)(addr & mask); } static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, @@ -398,6 +400,8 @@ void flash_write_cmd (flash_info_t * info, flash_sect_t sect, #endif flash_write64(cword.ll, addr); break; + default: + printf("fwc: Unknown port width %d\n", info->portwidth); } /* Ensure all the instructions are fully finished */ @@ -585,7 +589,6 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector, prompt, info->start[sector], flash_read_long (info, sector, 0)); flash_write_cmd (info, sector, 0, info->cmd_reset); - udelay(1); return ERR_TIMOUT; } udelay (1); /* also triggers watchdog */ @@ -753,12 +756,8 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) static flash_sect_t find_sector (flash_info_t * info, ulong addr) { static flash_sect_t saved_sector; /* previously found sector */ - static flash_info_t *saved_info; /* previously used flash bank */ flash_sect_t sector = saved_sector; - if ((info != saved_info) || (sector >= info->sector_count)) - sector = 0; - while ((info->start[sector] < addr) && (sector < info->sector_count - 1)) sector++; @@ -770,7 +769,6 @@ static flash_sect_t find_sector (flash_info_t * info, ulong addr) sector--; saved_sector = sector; - saved_info = info; return sector; } @@ -787,12 +785,15 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, /* Check if Flash is (sufficiently) erased */ switch (info->portwidth) { case FLASH_CFI_8BIT: + debug("%s: 8-bit 0x%02x\n", __func__, cword.c); flag = ((flash_read8(dstaddr) & cword.c) == cword.c); break; case FLASH_CFI_16BIT: + debug("%s: 16-bit 0x%04x\n", __func__, cword.w); flag = ((flash_read16(dstaddr) & cword.w) == cword.w); break; case FLASH_CFI_32BIT: + debug("%s: 32-bit 0x%08lx\n", __func__, cword.l); flag = ((flash_read32(dstaddr) & cword.l) == cword.l); break; case FLASH_CFI_64BIT: @@ -1053,6 +1054,8 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) flash_sect_t sect; int st; + debug("%s: erasing sectors %d to %d\n", __func__, s_first, s_last); + if (info->flash_id != FLASH_MAN_CFI) { puts ("Can't erase unknown flash type - aborted\n"); return 1; @@ -1162,6 +1165,9 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) rcode = 1; else if (flash_verbose) putc ('.'); + } else { + debug("\nSector %d is protected.\n", + info->protect[sect]); } } @@ -1857,7 +1863,7 @@ static void flash_read_cfi (flash_info_t *info, void *buf, unsigned int i; for (i = 0; i < len; i++) - p[i] = flash_read_uchar(info, start + i); + p[i] = flash_read_uchar(info, start + (i * 2)); } static void __flash_cmd_reset(flash_info_t *info) @@ -1878,21 +1884,40 @@ static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) { int cfi_offset; - /* Issue FLASH reset command */ - flash_cmd_reset(info); - for (cfi_offset=0; cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); cfi_offset++) { + /* Issue FLASH reset command */ + flash_cmd_reset(info); flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], FLASH_CMD_CFI); - if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') - && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') - && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { + if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && + flash_isequal(info, 0, + FLASH_OFFSET_CFI_RESP + 2, 'R') && + flash_isequal(info, 0, + FLASH_OFFSET_CFI_RESP + 4, 'Y')) { flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, sizeof(struct cfi_qry)); +#ifdef CONFIG_SYS_FLASH_INTERFACE_WIDTH + info->interface = CONFIG_SYS_FLASH_INTERFACE_WIDTH; +#else info->interface = le16_to_cpu(qry->interface_desc); - + /* Some flash chips can support multiple bus widths. + * In this case, override the interface width and + * limit it to the port width. + */ + if ((info->interface == FLASH_CFI_X8X16) && + (info->portwidth == FLASH_CFI_8BIT)) { + debug("Overriding 16-bit interface" + " width to 8-bit port width.\n"); + info->interface = FLASH_CFI_X8; + } else if ((info->interface == FLASH_CFI_X16X32) && + (info->portwidth == FLASH_CFI_16BIT)) { + debug("Overriding 16-bit interface" + " width to 16-bit port width.\n"); + info->interface = FLASH_CFI_X16; + } +#endif info->cfi_offset = flash_offset_cfi[cfi_offset]; debug ("device interface is %d\n", info->interface); @@ -1903,8 +1928,8 @@ static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) info->chipwidth << CFI_FLASH_SHIFT_WIDTH); /* calculate command offsets as in the Linux driver */ - info->addr_unlock1 = 0x555; - info->addr_unlock2 = 0x2aa; + info->addr_unlock1 = 0xaaa; + info->addr_unlock2 = 0x555; /* * modify the unlock address if we are @@ -1938,8 +1963,12 @@ static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) for (info->chipwidth = FLASH_CFI_BY8; info->chipwidth <= info->portwidth; info->chipwidth <<= 1) - if (__flash_detect_cfi(info, qry)) + if (__flash_detect_cfi(info, qry)) { + debug("Found CFI flash, portwidth %d," + " chipwidth %d\n", + info->portwidth, info->chipwidth); return 1; + } } debug ("not found\n"); return 0; @@ -1958,7 +1987,7 @@ static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) /* CFI < 1.1, try to guess from device id */ if ((info->device_id & 0x80) != 0) cfi_reverse_geometry(qry); - } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { + } else if (flash_read_uchar(info, info->ext_addr + 0x1e) == 3) { /* CFI >= 1.1, deduct from top/bottom flag */ /* note: ext_addr is valid since cfi_version > 0 */ cfi_reverse_geometry(qry); @@ -2024,6 +2053,26 @@ static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry) } } +static void flash_fixup_num(flash_info_t *info, struct cfi_qry *qry) +{ + /* + * The M29EW devices seem to report the CFI information wrong + * when it's in 8 bit mode. + * There's an app note from Numonyx on this issue. + * So adjust the buffer size for M29EW while operating in 8-bit mode + */ + if (((qry->max_buf_write_size) > 0x8) && + (info->device_id == 0x7E) && + (info->device_id2 == 0x2201 || + info->device_id2 == 0x2301 || + info->device_id2 == 0x2801 || + info->device_id2 == 0x4801)) { + debug("Adjusted buffer size on Numonyx flash" + " M29EW family in 8 bit mode\n"); + qry->max_buf_write_size = 0x8; + } +} + /* * The following code cannot be run from FLASH! * @@ -2054,14 +2103,15 @@ ulong flash_get_size (phys_addr_t base, int banknum) if (flash_detect_cfi (info, &qry)) { info->vendor = le16_to_cpu(qry.p_id); - info->ext_addr = le16_to_cpu(qry.p_adr); + info->ext_addr = le16_to_cpu(qry.p_adr) * 2; + debug("extended address is 0x%x\n", info->ext_addr); num_erase_regions = qry.num_erase_regions; if (info->ext_addr) { info->cfi_version = (ushort) flash_read_uchar (info, - info->ext_addr + 3) << 8; + info->ext_addr + 6) << 8; info->cfi_version |= (ushort) flash_read_uchar (info, - info->ext_addr + 4); + info->ext_addr + 8); } #ifdef DEBUG @@ -2105,6 +2155,9 @@ ulong flash_get_size (phys_addr_t base, int banknum) case 0x00bf: /* SST */ flash_fixup_sst(info, &qry); break; + case 0x0089: /* Numonyx */ + flash_fixup_num(info, &qry); + break; } debug ("manufacturer is %d\n", info->vendor); @@ -2112,6 +2165,8 @@ ulong flash_get_size (phys_addr_t base, int banknum) debug ("device id is 0x%x\n", info->device_id); debug ("device id2 is 0x%x\n", info->device_id2); debug ("cfi version is 0x%04x\n", info->cfi_version); + debug("port width: %d, chipwidth: %d, interface: %d\n", + info->portwidth, info->chipwidth, info->interface); size_ratio = info->portwidth / info->chipwidth; /* if the chip is x8/x16 reduce the ratio by half */ diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index 96dcda2b2..cbfc6796c 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -347,16 +347,18 @@ static struct mtd_part *add_one_partition(struct mtd_info *master, if (mtd_mod_by_eb(cur_offset, master) != 0) { /* Round up to next erasesize */ slave->offset = (mtd_div_by_eb(cur_offset, master) + 1) * master->erasesize; - printk(KERN_NOTICE "Moving partition %d: " - "0x%012llx -> 0x%012llx\n", partno, - (unsigned long long)cur_offset, (unsigned long long)slave->offset); + debug("Moving partition %d: 0x%012llx -> 0x%012llx\n", + partno, (unsigned long long)cur_offset, + (unsigned long long)slave->offset); } } if (slave->mtd.size == MTDPART_SIZ_FULL) slave->mtd.size = master->size - slave->offset; - printk(KERN_NOTICE "0x%012llx-0x%012llx : \"%s\"\n", (unsigned long long)slave->offset, - (unsigned long long)(slave->offset + slave->mtd.size), slave->mtd.name); + debug("0x%012llx-0x%012llx : \"%s\"\n", + (unsigned long long)slave->offset, + (unsigned long long)(slave->offset + slave->mtd.size), + slave->mtd.name); /* let's do some sanity checks */ if (slave->offset >= master->size) { @@ -463,7 +465,7 @@ int add_mtd_partitions(struct mtd_info *master, if (mtd_partitions.next == NULL) INIT_LIST_HEAD(&mtd_partitions); - printk(KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nbparts, master->name); + debug("Creating %d MTD partitions on \"%s\":\n", nbparts, master->name); for (i = 0; i < nbparts; i++) { slave = add_one_partition(master, parts + i, i, cur_offset); diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 507bbc254..eeba52194 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -30,8 +30,6 @@ #define DRIVER_NAME "mxc_nand" -typedef enum {false, true} bool; - struct mxc_nand_host { struct mtd_info mtd; struct nand_chip *nand; diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index ff2d34830..4727f9c98 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -416,11 +416,13 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, * @param nand NAND device * @param offset offset in flash * @param length image length + * @param used length of flash needed for the requested length * @return 0 if the image fits and there are no bad blocks * 1 if the image fits, but there are bad blocks * -1 if the image does not fit */ -static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length) +static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length, + size_t *used) { size_t len_excl_bad = 0; int ret = 0; @@ -442,8 +444,13 @@ static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length) ret = 1; offset += block_len; + *used += block_len; } + /* If the length is not a multiple of block_len, adjust. */ + if (len_excl_bad > length) + *used -= (len_excl_bad - length); + return ret; } @@ -476,23 +483,36 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf, * Write image to NAND flash. * Blocks that are marked bad are skipped and the is written to the next * block instead as long as the image is short enough to fit even after - * skipping the bad blocks. + * skipping the bad blocks. Due to bad blocks we may not be able to + * perform the requested write. In the case where the write would + * extend beyond the end of the NAND device, both length and actual (if + * not NULL) are set to 0. In the case where the write would extend + * beyond the limit we are passed, length is set to 0 and actual is set + * to the required length. * * @param nand NAND device * @param offset offset in flash * @param length buffer length + * @param actual set to size required to write length worth of + * buffer or 0 on error, if not NULL + * @param lim maximum size that actual may be in order to not + * exceed the buffer * @param buffer buffer to read from * @param flags flags modifying the behaviour of the write to NAND * @return 0 in case of success */ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, - u_char *buffer, int flags) + size_t *actual, loff_t lim, u_char *buffer, int flags) { int rval = 0, blocksize; size_t left_to_write = *length; + size_t used_for_write = 0; u_char *p_buffer = buffer; int need_skip; + if (actual) + *actual = 0; + #ifdef CONFIG_CMD_NAND_YAFFS if (flags & WITH_YAFFS_OOB) { if (flags & ~WITH_YAFFS_OOB) @@ -529,13 +549,23 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, return -EINVAL; } - need_skip = check_skip_len(nand, offset, *length); + need_skip = check_skip_len(nand, offset, *length, &used_for_write); + + if (actual) + *actual = used_for_write; + if (need_skip < 0) { printf("Attempt to write outside the flash area\n"); *length = 0; return -EINVAL; } + if (used_for_write > lim) { + puts("Size of write exceeds partition or device limit\n"); + *length = 0; + return -EFBIG; + } + if (!need_skip && !(flags & WITH_DROP_FFS)) { rval = nand_write(nand, offset, length, buffer); if (rval == 0) @@ -626,36 +656,58 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, * * Read image from NAND flash. * Blocks that are marked bad are skipped and the next block is read - * instead as long as the image is short enough to fit even after skipping the - * bad blocks. + * instead as long as the image is short enough to fit even after + * skipping the bad blocks. Due to bad blocks we may not be able to + * perform the requested read. In the case where the read would extend + * beyond the end of the NAND device, both length and actual (if not + * NULL) are set to 0. In the case where the read would extend beyond + * the limit we are passed, length is set to 0 and actual is set to the + * required length. * * @param nand NAND device * @param offset offset in flash * @param length buffer length, on return holds number of read bytes + * @param actual set to size required to read length worth of buffer or 0 + * on error, if not NULL + * @param lim maximum size that actual may be in order to not exceed the + * buffer * @param buffer buffer to write to * @return 0 in case of success */ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, - u_char *buffer) + size_t *actual, loff_t lim, u_char *buffer) { int rval; size_t left_to_read = *length; + size_t used_for_read = 0; u_char *p_buffer = buffer; int need_skip; if ((offset & (nand->writesize - 1)) != 0) { printf("Attempt to read non page-aligned data\n"); *length = 0; + if (actual) + *actual = 0; return -EINVAL; } - need_skip = check_skip_len(nand, offset, *length); + need_skip = check_skip_len(nand, offset, *length, &used_for_read); + + if (actual) + *actual = used_for_read; + if (need_skip < 0) { printf("Attempt to read outside the flash area\n"); *length = 0; return -EINVAL; } + if (used_for_read > lim) { + puts("Size of read exceeds partition or device limit\n"); + *length = 0; + return -EFBIG; + } + if (!need_skip) { rval = nand_read(nand, offset, length, buffer); if (!rval || rval == -EUCLEAN) diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index d144ac29b..a708162e4 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -478,19 +478,19 @@ static int attach_by_scanning(struct ubi_device *ubi) err = ubi_eba_init_scan(ubi, si); if (err) - goto out_wl; + goto out_vtbl; err = ubi_wl_init_scan(ubi, si); if (err) - goto out_vtbl; + goto out_eba; ubi_scan_destroy_si(si); return 0; +out_eba: + ubi_eba_close(ubi); out_vtbl: vfree(ubi->vtbl); -out_wl: - ubi_wl_close(ubi); out_si: ubi_scan_destroy_si(si); return err; diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h index 14c3a5f76..044e84990 100644 --- a/drivers/mtd/ubi/ubi.h +++ b/drivers/mtd/ubi/ubi.h @@ -59,7 +59,11 @@ #define UBI_NAME_STR "ubi" /* Normal UBI messages */ +#ifdef CONFIG_UBI_SILENCE_MSG +#define ubi_msg(fmt, ...) +#else #define ubi_msg(fmt, ...) printk(KERN_NOTICE "UBI: " fmt "\n", ##__VA_ARGS__) +#endif /* UBI warning messages */ #define ubi_warn(fmt, ...) printk(KERN_WARNING "UBI warning: %s: " fmt "\n", \ __func__, ##__VA_ARGS__) diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index 88b867a0c..d1ba722cb 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -1538,6 +1538,7 @@ int ubi_wl_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si) if (ubi->avail_pebs < WL_RESERVED_PEBS) { ubi_err("no enough physical eraseblocks (%d, need %d)", ubi->avail_pebs, WL_RESERVED_PEBS); + err = -ENOSPC; goto out_free; } ubi->avail_pebs -= WL_RESERVED_PEBS; diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c index ed7cf2032..89ebf0b51 100644 --- a/drivers/net/armada100_fec.c +++ b/drivers/net/armada100_fec.c @@ -100,7 +100,7 @@ static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg, } /* wait for the SMI register to become available */ - if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) { + if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) { printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); return -1; } @@ -108,7 +108,7 @@ static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg, writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi); /* now wait for the data to be valid */ - if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, TRUE)) { + if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) { val = readl(®s->smi); printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n", __func__, val); @@ -143,7 +143,7 @@ static int smi_reg_write(const char *devname, } /* wait for the SMI register to become available */ - if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) { + if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) { printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); return -1; } diff --git a/drivers/net/armada100_fec.h b/drivers/net/armada100_fec.h index e2df4fcb8..dcac96494 100644 --- a/drivers/net/armada100_fec.h +++ b/drivers/net/armada100_fec.h @@ -29,13 +29,6 @@ #ifndef __ARMADA100_FEC_H__ #define __ARMADA100_FEC_H__ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #define PORT_NUM 0x0 /* RX & TX descriptor command */ diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 8ba98b27d..c1863f4bb 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -313,14 +313,14 @@ void e1000_standby_eeprom(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code ****************************************************************************/ -static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) +static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) { uint32_t eecd = 0; DEBUGFUNC(); if (hw->mac_type == e1000_ich8lan) - return FALSE; + return false; if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { eecd = E1000_READ_REG(hw, EECD); @@ -330,9 +330,9 @@ static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) /* If both bits are set, device is Flash type */ if (eecd == 0x03) - return FALSE; + return false; } - return TRUE; + return true; } /****************************************************************************** @@ -421,8 +421,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->opcode_bits = 3; eeprom->address_bits = 6; eeprom->delay_usec = 50; - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; break; case e1000_82540: case e1000_82545: @@ -439,8 +439,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->word_size = 64; eeprom->address_bits = 6; } - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; break; case e1000_82541: case e1000_82541_rev_2: @@ -469,8 +469,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->address_bits = 6; } } - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; break; case e1000_82571: case e1000_82572: @@ -484,8 +484,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->page_size = 8; eeprom->address_bits = 8; } - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; break; case e1000_82573: case e1000_82574: @@ -499,9 +499,9 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->page_size = 8; eeprom->address_bits = 8; } - eeprom->use_eerd = TRUE; - eeprom->use_eewr = TRUE; - if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { + eeprom->use_eerd = true; + eeprom->use_eewr = true; + if (e1000_is_onboard_nvm_eeprom(hw) == false) { eeprom->type = e1000_eeprom_flash; eeprom->word_size = 2048; @@ -522,8 +522,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->page_size = 8; eeprom->address_bits = 8; } - eeprom->use_eerd = TRUE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = true; + eeprom->use_eewr = false; break; /* ich8lan does not support currently. if needed, please @@ -535,8 +535,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) int32_t i = 0; eeprom->type = e1000_eeprom_ich8; - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; eeprom->word_size = E1000_SHADOW_RAM_WORDS; uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); @@ -544,7 +544,7 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) * so as to save time for driver init */ if (hw->eeprom_shadow_ram != NULL) { for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - hw->eeprom_shadow_ram[i].modified = FALSE; + hw->eeprom_shadow_ram[i].modified = false; hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; } } @@ -779,8 +779,8 @@ e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, * directly. In this case, we need to acquire the EEPROM so that * FW or other port software does not interrupt. */ - if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && - hw->eeprom.use_eerd == FALSE) { + if (e1000_is_onboard_nvm_eeprom(hw) == true && + hw->eeprom.use_eerd == false) { /* Prepare the EEPROM for bit-bang reading */ if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) @@ -788,7 +788,7 @@ e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, } /* Eerd register EEPROM access requires no eeprom aquire/release */ - if (eeprom->use_eerd == TRUE) + if (eeprom->use_eerd == true) return e1000_read_eeprom_eerd(hw, offset, words, data); /* ich8lan does not support currently. if needed, please @@ -935,7 +935,7 @@ e1000_set_phy_mode(struct e1000_hw *hw) if (ret_val) return ret_val; - hw->phy_reset_disable = FALSE; + hw->phy_reset_disable = false; } } @@ -1098,17 +1098,17 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) return E1000_SUCCESS; } -static boolean_t e1000_is_second_port(struct e1000_hw *hw) +static bool e1000_is_second_port(struct e1000_hw *hw) { switch (hw->mac_type) { case e1000_80003es2lan: case e1000_82546: case e1000_82571: if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) - return TRUE; + return true; /* Fallthrough */ default: - return FALSE; + return false; } } @@ -1373,7 +1373,7 @@ e1000_reset_hw(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ - hw->tbi_compatibility_on = FALSE; + hw->tbi_compatibility_on = false; /* Delay to allow any outstanding PCI transactions to complete before * resetting the device @@ -2098,7 +2098,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw) hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) - hw->phy_reset_disable = FALSE; + hw->phy_reset_disable = false; return E1000_SUCCESS; } @@ -2118,7 +2118,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw) ****************************************************************************/ static int32_t -e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active) +e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) { uint32_t phy_ctrl = 0; int32_t ret_val; @@ -2253,7 +2253,7 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active) ****************************************************************************/ static int32_t -e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active) +e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) { uint32_t phy_ctrl = 0; int32_t ret_val; @@ -2378,7 +2378,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw) /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ if (hw->phy_type == e1000_phy_igp) { /* disable lplu d3 during driver init */ - ret_val = e1000_set_d3_lplu_state(hw, FALSE); + ret_val = e1000_set_d3_lplu_state(hw, false); if (ret_val) { DEBUGOUT("Error Disabling LPLU D3\n"); return ret_val; @@ -2386,7 +2386,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw) } /* disable lplu d0 during driver init */ - ret_val = e1000_set_d0_lplu_state(hw, FALSE); + ret_val = e1000_set_d0_lplu_state(hw, false); if (ret_val) { DEBUGOUT("Error Disabling LPLU D0\n"); return ret_val; @@ -2495,9 +2495,9 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw) /***************************************************************************** * This function checks the mode of the firmware. * - * returns - TRUE when the mode is IAMT or FALSE. + * returns - true when the mode is IAMT or false. ****************************************************************************/ -boolean_t +bool e1000_check_mng_mode(struct e1000_hw *hw) { uint32_t fwsm; @@ -2508,12 +2508,12 @@ e1000_check_mng_mode(struct e1000_hw *hw) if (hw->mac_type == e1000_ich8lan) { if ((fwsm & E1000_FWSM_MODE_MASK) == (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) - return TRUE; + return true; } else if ((fwsm & E1000_FWSM_MODE_MASK) == (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) - return TRUE; + return true; - return FALSE; + return false; } static int32_t @@ -2675,7 +2675,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw) * firmware will have already initialized them. We only initialize * them if the HW is not in IAMT mode. */ - if (e1000_check_mng_mode(hw) == FALSE) { + if (e1000_check_mng_mode(hw) == false) { /* Enable Electrical Idle on the PHY */ phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; ret_val = e1000_write_phy_reg(hw, @@ -2879,7 +2879,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw) } } - hw->get_link_status = TRUE; + hw->get_link_status = true; return E1000_SUCCESS; } @@ -3598,7 +3598,7 @@ e1000_check_for_link(struct eth_device *nic) } if (phy_data & MII_SR_LINK_STATUS) { - hw->get_link_status = FALSE; + hw->get_link_status = false; } else { /* No link detected */ return -E1000_ERR_NOLINK; @@ -3661,7 +3661,7 @@ e1000_check_for_link(struct eth_device *nic) rctl = E1000_READ_REG(hw, RCTL); rctl &= ~E1000_RCTL_SBP; E1000_WRITE_REG(hw, RCTL, rctl); - hw->tbi_compatibility_on = FALSE; + hw->tbi_compatibility_on = false; } } else { /* If TBI compatibility is was previously off, turn it on. For @@ -3670,7 +3670,7 @@ e1000_check_for_link(struct eth_device *nic) * will look like CRC errors to to the hardware. */ if (!hw->tbi_compatibility_on) { - hw->tbi_compatibility_on = TRUE; + hw->tbi_compatibility_on = true; rctl = E1000_READ_REG(hw, RCTL); rctl |= E1000_RCTL_SBP; E1000_WRITE_REG(hw, RCTL, rctl); @@ -4569,7 +4569,7 @@ e1000_detect_gig_phy(struct e1000_hw *hw) { int32_t phy_init_status, ret_val; uint16_t phy_id_high, phy_id_low; - boolean_t match = FALSE; + bool match = false; DEBUGFUNC(); @@ -4609,11 +4609,11 @@ e1000_detect_gig_phy(struct e1000_hw *hw) switch (hw->mac_type) { case e1000_82543: if (hw->phy_id == M88E1000_E_PHY_ID) - match = TRUE; + match = true; break; case e1000_82544: if (hw->phy_id == M88E1000_I_PHY_ID) - match = TRUE; + match = true; break; case e1000_82540: case e1000_82545: @@ -4621,37 +4621,37 @@ e1000_detect_gig_phy(struct e1000_hw *hw) case e1000_82546: case e1000_82546_rev_3: if (hw->phy_id == M88E1011_I_PHY_ID) - match = TRUE; + match = true; break; case e1000_82541: case e1000_82541_rev_2: case e1000_82547: case e1000_82547_rev_2: if(hw->phy_id == IGP01E1000_I_PHY_ID) - match = TRUE; + match = true; break; case e1000_82573: if (hw->phy_id == M88E1111_I_PHY_ID) - match = TRUE; + match = true; break; case e1000_82574: if (hw->phy_id == BME1000_E_PHY_ID) - match = TRUE; + match = true; break; case e1000_80003es2lan: if (hw->phy_id == GG82563_E_PHY_ID) - match = TRUE; + match = true; break; case e1000_ich8lan: if (hw->phy_id == IGP03E1000_E_PHY_ID) - match = TRUE; + match = true; if (hw->phy_id == IFE_E_PHY_ID) - match = TRUE; + match = true; if (hw->phy_id == IFE_PLUS_E_PHY_ID) - match = TRUE; + match = true; if (hw->phy_id == IFE_C_E_PHY_ID) - match = TRUE; + match = true; break; default: DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); @@ -4682,7 +4682,7 @@ e1000_set_media_type(struct e1000_hw *hw) if (hw->mac_type != e1000_82543) { /* tbi_compatibility is only valid on 82543 */ - hw->tbi_compatibility_en = FALSE; + hw->tbi_compatibility_en = false; } switch (hw->device_id) { @@ -4714,7 +4714,7 @@ e1000_set_media_type(struct e1000_hw *hw) if (status & E1000_STATUS_TBIMODE) { hw->media_type = e1000_media_type_fiber; /* tbi_compatibility not valid on fiber */ - hw->tbi_compatibility_en = FALSE; + hw->tbi_compatibility_en = false; } else { hw->media_type = e1000_media_type_copper; } @@ -4788,8 +4788,8 @@ e1000_sw_init(struct eth_device *nic) hw->media_type = e1000_media_type_fiber; } - hw->tbi_compatibility_en = TRUE; - hw->wait_autoneg_complete = TRUE; + hw->tbi_compatibility_en = true; + hw->wait_autoneg_complete = true; if (hw->mac_type < e1000_82543) hw->report_tx_early = 0; else @@ -5194,7 +5194,7 @@ e1000_initialize(bd_t * bis) hw->original_fc = e1000_fc_default; hw->autoneg_failed = 0; hw->autoneg = 1; - hw->get_link_status = TRUE; + hw->get_link_status = true; hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); hw->mac_type = e1000_undefined; diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 1bbae5085..6b93c2bfe 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -89,11 +89,6 @@ int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw, int argc, char * const argv[]); #endif -typedef enum { - FALSE = 0, - TRUE = 1 -} boolean_t; - /* Enumerated types specific to the e1000 hardware */ /* Media Access Controlers */ typedef enum { @@ -340,7 +335,7 @@ struct e1000_phy_stats { Control and Address */ #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ -#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False +#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive false Carrier Counter */ #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */ @@ -1040,14 +1035,14 @@ struct e1000_hw_stats { }; struct e1000_eeprom_info { - e1000_eeprom_type type; - uint16_t word_size; - uint16_t opcode_bits; - uint16_t address_bits; - uint16_t delay_usec; - uint16_t page_size; - boolean_t use_eerd; - boolean_t use_eewr; +e1000_eeprom_type type; + uint16_t word_size; + uint16_t opcode_bits; + uint16_t address_bits; + uint16_t delay_usec; + uint16_t page_size; + bool use_eerd; + bool use_eewr; }; typedef enum { @@ -1150,20 +1145,20 @@ struct e1000_hw { #if 0 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; #endif - boolean_t disable_polarity_correction; - boolean_t speed_downgraded; - boolean_t get_link_status; - boolean_t tbi_compatibility_en; - boolean_t tbi_compatibility_on; - boolean_t fc_strict_ieee; - boolean_t fc_send_xon; - boolean_t report_tx_early; - boolean_t phy_reset_disable; - boolean_t initialize_hw_bits_disable; + bool disable_polarity_correction; + bool speed_downgraded; + bool get_link_status; + bool tbi_compatibility_en; + bool tbi_compatibility_on; + bool fc_strict_ieee; + bool fc_send_xon; + bool report_tx_early; + bool phy_reset_disable; + bool initialize_hw_bits_disable; #if 0 - boolean_t adaptive_ifs; - boolean_t ifs_params_forced; - boolean_t in_ifs_mode; + bool adaptive_ifs; + bool ifs_params_forced; + bool in_ifs_mode; #endif e1000_smart_speed smart_speed; e1000_dsp_config dsp_config_state; @@ -1860,11 +1855,11 @@ struct e1000_hw { * Typical use: * ... * if (TBI_ACCEPT) { - * accept_frame = TRUE; + * accept_frame = true; * e1000_tbi_adjust_stats(adapter, MacAddress); * frame_length--; * } else { - * accept_frame = FALSE; + * accept_frame = false; * } * ... */ @@ -2080,7 +2075,7 @@ struct e1000_hw { #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */ #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */ #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */ -#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */ +#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=false Carrier */ #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */ #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */ #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */ diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c index 5f774f4d8..93043a1ad 100644 --- a/drivers/net/e1000_spi.c +++ b/drivers/net/e1000_spi.c @@ -17,7 +17,7 @@ * never return an error. */ static int e1000_spi_xfer(struct e1000_hw *hw, unsigned int bitlen, - const void *dout_mem, void *din_mem, boolean_t intr) + const void *dout_mem, void *din_mem, bool intr) { const uint8_t *dout = dout_mem; uint8_t *din = din_mem; @@ -145,7 +145,7 @@ int spi_xfer(struct spi_slave *spi, unsigned int bitlen, if (flags & SPI_XFER_BEGIN) e1000_standby_eeprom(hw); - ret = e1000_spi_xfer(hw, bitlen, dout_mem, din_mem, TRUE); + ret = e1000_spi_xfer(hw, bitlen, dout_mem, din_mem, true); if (flags & SPI_XFER_END) e1000_standby_eeprom(hw); @@ -169,7 +169,7 @@ int spi_xfer(struct spi_slave *spi, unsigned int bitlen, #define SPI_EEPROM_STATUS_BUSY 0x01 #define SPI_EEPROM_STATUS_WREN 0x02 -static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, boolean_t intr) +static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, bool intr) { u8 op[] = { SPI_EEPROM_ENABLE_WR }; e1000_standby_eeprom(hw); @@ -181,7 +181,7 @@ static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, boolean_t intr) * of the EEPROM commands at this time. */ #if 0 -static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, boolean_t intr) +static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, bool intr) { u8 op[] = { SPI_EEPROM_DISABLE_WR }; e1000_standby_eeprom(hw); @@ -189,7 +189,7 @@ static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, boolean_t intr) } static int e1000_spi_eeprom_write_status(struct e1000_hw *hw, - u8 status, boolean_t intr) + u8 status, bool intr) { u8 op[] = { SPI_EEPROM_WRITE_STATUS, status }; e1000_standby_eeprom(hw); @@ -197,7 +197,7 @@ static int e1000_spi_eeprom_write_status(struct e1000_hw *hw, } #endif -static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, boolean_t intr) +static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, bool intr) { u8 op[] = { SPI_EEPROM_READ_STATUS, 0 }; e1000_standby_eeprom(hw); @@ -207,7 +207,7 @@ static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, boolean_t intr) } static int e1000_spi_eeprom_write_page(struct e1000_hw *hw, - const void *data, u16 off, u16 len, boolean_t intr) + const void *data, u16 off, u16 len, bool intr) { u8 op[] = { SPI_EEPROM_WRITE_PAGE, @@ -225,7 +225,7 @@ static int e1000_spi_eeprom_write_page(struct e1000_hw *hw, } static int e1000_spi_eeprom_read_page(struct e1000_hw *hw, - void *data, u16 off, u16 len, boolean_t intr) + void *data, u16 off, u16 len, bool intr) { u8 op[] = { SPI_EEPROM_READ_PAGE, @@ -242,7 +242,7 @@ static int e1000_spi_eeprom_read_page(struct e1000_hw *hw, return 0; } -static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, boolean_t intr) +static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, bool intr) { int status; while ((status = e1000_spi_eeprom_read_status(hw, intr)) >= 0) { @@ -253,7 +253,7 @@ static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, boolean_t intr) } static int e1000_spi_eeprom_dump(struct e1000_hw *hw, - void *data, u16 off, unsigned int len, boolean_t intr) + void *data, u16 off, unsigned int len, bool intr) { /* Interruptibly wait for the EEPROM to be ready */ if (e1000_spi_eeprom_poll_ready(hw, intr)) @@ -282,7 +282,7 @@ static int e1000_spi_eeprom_dump(struct e1000_hw *hw, } static int e1000_spi_eeprom_program(struct e1000_hw *hw, - const void *data, u16 off, u16 len, boolean_t intr) + const void *data, u16 off, u16 len, bool intr) { /* Program each page in sequence */ while (len) { @@ -362,7 +362,7 @@ static int do_e1000_spi_show(cmd_tbl_t *cmdtp, struct e1000_hw *hw, free(buffer); return 1; } - err = e1000_spi_eeprom_dump(hw, buffer, offset, length, TRUE); + err = e1000_spi_eeprom_dump(hw, buffer, offset, length, true); e1000_release_eeprom(hw); if (err) { E1000_ERR(hw->nic, "Interrupted!\n"); @@ -421,7 +421,7 @@ static int do_e1000_spi_dump(cmd_tbl_t *cmdtp, struct e1000_hw *hw, } /* Perform the programming operation */ - if (e1000_spi_eeprom_dump(hw, dest, offset, length, TRUE) < 0) { + if (e1000_spi_eeprom_dump(hw, dest, offset, length, true) < 0) { E1000_ERR(hw->nic, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; @@ -456,7 +456,7 @@ static int do_e1000_spi_program(cmd_tbl_t *cmdtp, struct e1000_hw *hw, } /* Perform the programming operation */ - if (e1000_spi_eeprom_program(hw, source, offset, length, TRUE) < 0) { + if (e1000_spi_eeprom_program(hw, source, offset, length, true) < 0) { E1000_ERR(hw->nic, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; @@ -472,7 +472,7 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, { uint16_t i, length, checksum = 0, checksum_reg; uint16_t *buffer; - boolean_t upd; + bool upd; if (argc == 0) upd = 0; @@ -498,7 +498,7 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, } /* Read the EEPROM */ - if (e1000_spi_eeprom_dump(hw, buffer, 0, length, TRUE) < 0) { + if (e1000_spi_eeprom_dump(hw, buffer, 0, length, true) < 0) { E1000_ERR(hw->nic, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; @@ -533,7 +533,7 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, printf("%s: Reprogramming the EEPROM checksum...\n", hw->nic->name); buffer[i] = cpu_to_le16(checksum); if (e1000_spi_eeprom_program(hw, &buffer[i], i * sizeof(uint16_t), - sizeof(uint16_t), TRUE)) { + sizeof(uint16_t), true)) { E1000_ERR(hw->nic, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; diff --git a/drivers/net/ne2000_base.h b/drivers/net/ne2000_base.h index 5446de4bb..eee0956fd 100644 --- a/drivers/net/ne2000_base.h +++ b/drivers/net/ne2000_base.h @@ -79,10 +79,6 @@ are GPL, so this is, of course, GPL. #ifndef __NE2000_BASE_H__ #define __NE2000_BASE_H__ -#define bool int -#define false 0 -#define true 1 - /* * Debugging details * diff --git a/drivers/net/npe/IxEthAcc.c b/drivers/net/npe/IxEthAcc.c index 20d3d9e9b..718555895 100644 --- a/drivers/net/npe/IxEthAcc.c +++ b/drivers/net/npe/IxEthAcc.c @@ -82,7 +82,7 @@ extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex; * @ingroup IxEthAccPri * */ -BOOL ixEthAccServiceInit = FALSE; +BOOL ixEthAccServiceInit = false; /* global filtering bit mask */ PUBLIC UINT32 ixEthAccNewSrcMask; @@ -168,7 +168,7 @@ PUBLIC IxEthAccStatus ixEthAccInit() } /* initialiasation is complete */ - ixEthAccServiceInit = TRUE; + ixEthAccServiceInit = true; return IX_ETH_ACC_SUCCESS; @@ -200,11 +200,11 @@ PUBLIC void ixEthAccUnload(void) /* set all ports as uninitialized */ for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) { - ixEthAccPortData[portId].portInitialized = FALSE; + ixEthAccPortData[portId].portInitialized = false; } /* uninitialize the service */ - ixEthAccServiceInit = FALSE; + ixEthAccServiceInit = false; } } @@ -248,7 +248,7 @@ PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId) * Set the port init flag. */ - ixEthAccPortData[portId].portInitialized = TRUE; + ixEthAccPortData[portId].portInitialized = true; #ifdef CONFIG_IXP425_COMPONENT_ETHDB /* init learning/filtering database structures for this port */ diff --git a/drivers/net/npe/IxEthAccCommon.c b/drivers/net/npe/IxEthAccCommon.c index 211203dff..b93a8c8a3 100644 --- a/drivers/net/npe/IxEthAccCommon.c +++ b/drivers/net/npe/IxEthAccCommon.c @@ -102,7 +102,7 @@ IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate = (IxQMgrCallbackId) 0, /**< Callback tag */ IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - TRUE, /**< Enable Q notification at startup */ + true, /**< Enable Q notification at startup */ IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ @@ -122,7 +122,7 @@ IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate = (IxQMgrCallbackId) 0, /**< Callback tag */ IX_QMGR_Q_SIZE64, /**< Allocate Smaller Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - TRUE, /**< Enable Q notification at startup */ + true, /**< Enable Q notification at startup */ IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ @@ -144,7 +144,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) IX_ETH_PORT_1, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - FALSE, /**< Disable Q notification at startup */ + false, /**< Disable Q notification at startup */ IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ @@ -157,7 +157,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) IX_ETH_PORT_2, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - FALSE, /**< Disable Q notification at startup */ + false, /**< Disable Q notification at startup */ IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ @@ -170,7 +170,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) IX_ETH_PORT_3, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - FALSE, /**< Disable Q notification at startup */ + false, /**< Disable Q notification at startup */ IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE, /**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ @@ -183,7 +183,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) IX_ETH_PORT_1, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - FALSE, /**< Disable Q notification at startup */ + false, /**< Disable Q notification at startup */ IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ @@ -196,7 +196,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) IX_ETH_PORT_2, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - FALSE, /**< Disable Q notification at startup */ + false, /**< Disable Q notification at startup */ IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ @@ -209,7 +209,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) IX_ETH_PORT_3, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /** Queue Entry Sizes - all Q entries are single ord entries */ - FALSE, /** Disable Q notification at startup */ + false, /** Disable Q notification at startup */ IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE, /** Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */ IX_QMGR_Q_WM_LEVEL64, /** Q High water mark - needed used */ @@ -222,7 +222,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) 0, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - TRUE, /**< Enable Q notification at startup */ + true, /**< Enable Q notification at startup */ IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL2, /**< Q High water mark - needed by NPE */ @@ -449,7 +449,7 @@ ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes) /* * Set notification condition for Q */ - if ( qInfoDes->qNotificationEnableAtStartup == TRUE ) + if (qInfoDes->qNotificationEnableAtStartup == true) { if ( ixQMgrNotificationEnable(qInfoDes->qId, qInfoDes->qConditionSource) @@ -513,7 +513,7 @@ IxEthAccStatus ixEthAccQMgrQueuesConfig(void) IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY; UINT32 ixEthDBParameter = 0; - BOOL completelySorted = FALSE; + BOOL completelySorted = false; /* Fill the corspondance between ports and queues * This defines the mapping from port to queue Ids. @@ -706,7 +706,7 @@ IxEthAccStatus ixEthAccQMgrQueuesConfig(void) do { sortIterations++; - completelySorted = TRUE; + completelySorted = true; for (rxQueue = 0; rxQueue < rxQueueCount - sortIterations; rxQueue++) @@ -732,7 +732,7 @@ IxEthAccStatus ixEthAccQMgrQueuesConfig(void) rxQueues[rxQueue+1].npeId = npeId; rxQueues[rxQueue+1].qId = qId; rxQueues[rxQueue+1].trafficClass = trafficClass; - completelySorted = FALSE; + completelySorted = false; } } } diff --git a/drivers/net/npe/IxEthAccDataPlane.c b/drivers/net/npe/IxEthAccDataPlane.c index b62f0d016..6df3307e5 100644 --- a/drivers/net/npe/IxEthAccDataPlane.c +++ b/drivers/net/npe/IxEthAccDataPlane.c @@ -948,7 +948,7 @@ IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId, for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++) { if ((ixEthAccMacState[port].portDisableState == ACTIVE) - && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == TRUE)) + && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == true)) { /* one of the active ports has a different rx callback type. * Changing the callback type when the port is enabled @@ -977,7 +977,7 @@ IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId, return (IX_ETH_ACC_INVALID_ARG); } - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = FALSE; + ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = false; return (IX_ETH_ACC_SUCCESS); } @@ -1025,7 +1025,7 @@ IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister( for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++) { if ((ixEthAccMacState[port].portDisableState == ACTIVE) - && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == FALSE)) + && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == false)) { /* one of the active ports has a different rx callback type. * Changing the callback type when the port is enabled @@ -1055,7 +1055,7 @@ IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister( return (IX_ETH_ACC_INVALID_ARG); } - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = TRUE; + ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = true; return (IX_ETH_ACC_SUCCESS); } @@ -1456,7 +1456,7 @@ ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr) IX_ETH_ACC_FATAL_LOG( "ixEthRxFrameProcess: Illegal port: %u\n", (UINT32)portId, 0, 0, 0, 0, 0); - return FALSE; + return false; } #endif @@ -1468,7 +1468,7 @@ ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr) if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0) { /* "best case" scenario : nothing special to do for this frame */ - return TRUE; + return true; } #ifdef CONFIG_IXP425_COMPONENT_ETHDB @@ -1540,10 +1540,10 @@ ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr) RX_STATS_INC(portId, rxFiltered); /* indicate that frame should not be subjected to further processing */ - return FALSE; + return false; } - return TRUE; + return true; } diff --git a/drivers/net/npe/IxEthAccMac.c b/drivers/net/npe/IxEthAccMac.c index 369ee91d9..5540b33ae 100644 --- a/drivers/net/npe/IxEthAccMac.c +++ b/drivers/net/npe/IxEthAccMac.c @@ -304,7 +304,7 @@ ixEthAccPortEnablePriv(IxEthAccPortId portId) /* set the global state */ ixEthAccMacState[portId].portDisableState = ACTIVE; - ixEthAccMacState[portId].enabled = TRUE; + ixEthAccMacState[portId].enabled = true; /* rewrite the setup (including mac filtering) depending * on current options @@ -515,7 +515,7 @@ ixEthAccPortDisableRxCallback (UINT32 cbTag, IxEthAccPortId portId = (IxEthAccPortId)cbTag; /* call the portDisable receive callback */ - (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, FALSE); + (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, false); } PRIVATE void @@ -527,7 +527,7 @@ ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag, while (*mBufPtr) { /* call the portDisable receive callback with one buffer at a time */ - (ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, TRUE); + (ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, true); } } @@ -820,7 +820,7 @@ ixEthAccPortDisablePriv(IxEthAccPortId portId) } /* disable MAC Tx and Rx services */ - ixEthAccMacState[portId].enabled = FALSE; + ixEthAccMacState[portId].enabled = false; ixEthAccMacStateUpdate(portId); /* restore the Rx and TxDone callbacks (within a critical section) */ @@ -869,14 +869,14 @@ ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled) IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0); /* Since Eth NPE is not available, port must be disabled */ - *enabled = FALSE ; + *enabled = false ; return IX_ETH_ACC_SUCCESS ; } if (!IX_ETH_IS_PORT_INITIALIZED(portId)) { /* Since Eth NPE is not available, port must be disabled */ - *enabled = FALSE ; + *enabled = false ; return (IX_ETH_ACC_PORT_UNINITIALIZED); } @@ -1259,7 +1259,7 @@ ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId) IX_ETH_ACC_MAC_RX_CNTRL1, regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN); - ixEthAccMacState[portId].promiscuous = FALSE; + ixEthAccMacState[portId].promiscuous = false; ixEthAccMulticastAddressSet(portId); @@ -1297,7 +1297,7 @@ ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId) IX_ETH_ACC_MAC_RX_CNTRL1, regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN); - ixEthAccMacState[portId].promiscuous = TRUE; + ixEthAccMacState[portId].promiscuous = true; ixEthAccMulticastAddressSet(portId); @@ -1361,7 +1361,7 @@ ixEthAccPortUnicastMacAddressSetPriv (IxEthAccPortId portId, IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32), macAddr->macAddress[i]); } - ixEthAccMacState[portId].initDone = TRUE; + ixEthAccMacState[portId].initDone = true; return IX_ETH_ACC_SUCCESS; } @@ -1552,7 +1552,7 @@ ixEthAccPortMulticastAddressJoinAllPriv (IxEthAccPortId portId) IX_IEEE803_MAC_ADDRESS_SIZE); ixEthAccMacState[portId].mcastAddrIndex = 1; - ixEthAccMacState[portId].joinAll = TRUE; + ixEthAccMacState[portId].joinAll = true; ixEthAccMulticastAddressSet(portId); @@ -1599,7 +1599,7 @@ ixEthAccPortMulticastAddressLeavePriv (IxEthAccPortId portId, { if(ixEthAccMacEqual(macAddr, &mcastMacAddr)) { - ixEthAccMacState[portId].joinAll = FALSE; + ixEthAccMacState[portId].joinAll = false; } /*Decrement the index into the multicast address table for the current port*/ @@ -1643,7 +1643,7 @@ ixEthAccPortMulticastAddressLeaveAllPriv (IxEthAccPortId portId) } ixEthAccMacState[portId].mcastAddrIndex = 0; - ixEthAccMacState[portId].joinAll = FALSE; + ixEthAccMacState[portId].joinAll = false; ixEthAccMulticastAddressSet(portId); @@ -1770,7 +1770,7 @@ ixEthAccPortDuplexModeSetPriv (IxEthAccPortId portId, REG_WRITE(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_RX_CNTRL1, rxregval | IX_ETH_ACC_RX_CNTRL1_PAUSE_EN); - ixEthAccMacState[portId].fullDuplex = TRUE; + ixEthAccMacState[portId].fullDuplex = true; } else if (mode == IX_ETH_ACC_HALF_DUPLEX) @@ -1786,7 +1786,7 @@ ixEthAccPortDuplexModeSetPriv (IxEthAccPortId portId, IX_ETH_ACC_MAC_RX_CNTRL1, rxregval & ~IX_ETH_ACC_RX_CNTRL1_PAUSE_EN); - ixEthAccMacState[portId].fullDuplex = FALSE; + ixEthAccMacState[portId].fullDuplex = false; } else { @@ -1876,7 +1876,7 @@ ixEthAccPortTxFrameAppendPaddingEnablePriv (IxEthAccPortId portId) regval | IX_ETH_ACC_TX_CNTRL1_PAD_EN); - ixEthAccMacState[portId].txPADAppend = TRUE; + ixEthAccMacState[portId].txPADAppend = true; return IX_ETH_ACC_SUCCESS; } @@ -1908,7 +1908,7 @@ ixEthAccPortTxFrameAppendPaddingDisablePriv (IxEthAccPortId portId) IX_ETH_ACC_MAC_TX_CNTRL1, regval & ~IX_ETH_ACC_TX_CNTRL1_PAD_EN); - ixEthAccMacState[portId].txPADAppend = FALSE; + ixEthAccMacState[portId].txPADAppend = false; return IX_ETH_ACC_SUCCESS; } @@ -1941,7 +1941,7 @@ ixEthAccPortTxFrameAppendFCSEnablePriv (IxEthAccPortId portId) IX_ETH_ACC_MAC_TX_CNTRL1, regval | IX_ETH_ACC_TX_CNTRL1_FCS_EN); - ixEthAccMacState[portId].txFCSAppend = TRUE; + ixEthAccMacState[portId].txFCSAppend = true; return IX_ETH_ACC_SUCCESS; } @@ -1973,7 +1973,7 @@ ixEthAccPortTxFrameAppendFCSDisablePriv (IxEthAccPortId portId) IX_ETH_ACC_MAC_TX_CNTRL1, regval & ~IX_ETH_ACC_TX_CNTRL1_FCS_EN); - ixEthAccMacState[portId].txFCSAppend = FALSE; + ixEthAccMacState[portId].txFCSAppend = false; return IX_ETH_ACC_SUCCESS; } @@ -2004,7 +2004,7 @@ ixEthAccPortRxFrameAppendFCSEnablePriv (IxEthAccPortId portId) IX_ETH_ACC_MAC_RX_CNTRL1, regval | IX_ETH_ACC_RX_CNTRL1_CRC_EN); - ixEthAccMacState[portId].rxFCSAppend = TRUE; + ixEthAccMacState[portId].rxFCSAppend = true; return IX_ETH_ACC_SUCCESS; } @@ -2035,7 +2035,7 @@ ixEthAccPortRxFrameAppendFCSDisablePriv (IxEthAccPortId portId) IX_ETH_ACC_MAC_RX_CNTRL1, regval & ~IX_ETH_ACC_RX_CNTRL1_CRC_EN); - ixEthAccMacState[portId].rxFCSAppend = FALSE; + ixEthAccMacState[portId].rxFCSAppend = false; return IX_ETH_ACC_SUCCESS; } @@ -2327,17 +2327,17 @@ ixEthAccMacInit(IxEthAccPortId portId) return IX_ETH_ACC_SUCCESS ; } - if(ixEthAccMacState[portId].macInitialised == FALSE) + if(ixEthAccMacState[portId].macInitialised == false) { - ixEthAccMacState[portId].fullDuplex = TRUE; - ixEthAccMacState[portId].rxFCSAppend = TRUE; - ixEthAccMacState[portId].txFCSAppend = TRUE; - ixEthAccMacState[portId].txPADAppend = TRUE; - ixEthAccMacState[portId].enabled = FALSE; - ixEthAccMacState[portId].promiscuous = TRUE; - ixEthAccMacState[portId].joinAll = FALSE; - ixEthAccMacState[portId].initDone = FALSE; - ixEthAccMacState[portId].macInitialised = TRUE; + ixEthAccMacState[portId].fullDuplex = true; + ixEthAccMacState[portId].rxFCSAppend = true; + ixEthAccMacState[portId].txFCSAppend = true; + ixEthAccMacState[portId].txPADAppend = true; + ixEthAccMacState[portId].enabled = false; + ixEthAccMacState[portId].promiscuous = true; + ixEthAccMacState[portId].joinAll = false; + ixEthAccMacState[portId].initDone = false; + ixEthAccMacState[portId].macInitialised = true; /* initialize MIB stats mutexes */ ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsLock); @@ -2417,7 +2417,7 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId) { UINT32 regval; - if ( ixEthAccMacState[portId].enabled == FALSE ) + if ( ixEthAccMacState[portId].enabled == false ) { /* Just disable both the transmitter and reciver in the MAC. */ REG_READ(ixEthAccMacBase[portId], @@ -2480,7 +2480,7 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId) ixEthAccPortPromiscuousModeClearPriv(portId); } - if ( ixEthAccMacState[portId].enabled == TRUE ) + if ( ixEthAccMacState[portId].enabled == true ) { /* Enable both the transmitter and reciver in the MAC. */ REG_READ(ixEthAccMacBase[portId], @@ -2509,10 +2509,10 @@ ixEthAccMacEqual(IxEthAccMacAddr *macAddr1, { if(macAddr1->macAddress[i] != macAddr2->macAddress[i]) { - return FALSE; + return false; } } - return TRUE; + return true; } PRIVATE void @@ -2554,7 +2554,7 @@ ixEthAccMulticastAddressSet(IxEthAccPortId portId) * are set in the result */ - if (ixEthAccMacState[portId].promiscuous == TRUE) + if (ixEthAccMacState[portId].promiscuous == true) { /* Promiscuous Mode is set, and filtering * allow all packets, and enable the mcast and @@ -2569,7 +2569,7 @@ ixEthAccMulticastAddressSet(IxEthAccPortId portId) } else { - if(ixEthAccMacState[portId].joinAll == TRUE) + if(ixEthAccMacState[portId].joinAll == true) { /* Join all is set. The mask and address are * the multicast settings. diff --git a/drivers/net/npe/IxEthDBAPI.c b/drivers/net/npe/IxEthDBAPI.c index b2bfb7260..d46c47c2e 100644 --- a/drivers/net/npe/IxEthDBAPI.c +++ b/drivers/net/npe/IxEthDBAPI.c @@ -60,7 +60,7 @@ IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDB IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - return ixEthDBTriggerAddPortUpdate(macAddr, portID, TRUE); + return ixEthDBTriggerAddPortUpdate(macAddr, portID, true); } IX_ETH_DB_PUBLIC @@ -74,7 +74,7 @@ IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthD IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - return ixEthDBTriggerAddPortUpdate(macAddr, portID, FALSE); + return ixEthDBTriggerAddPortUpdate(macAddr, portID, false); } IX_ETH_DB_PUBLIC @@ -102,7 +102,7 @@ void ixEthDBDatabaseMaintenance() { HashIterator iterator; UINT32 portIndex; - BOOL agingRequired = FALSE; + BOOL agingRequired = false; /* ports who will have deleted records and therefore will need updating */ IxEthDBPortMap triggerPorts; @@ -120,7 +120,7 @@ void ixEthDBDatabaseMaintenance() { if (ixEthDBPortInfo[portIndex].agingEnabled && ixEthDBPortInfo[portIndex].enabled) { - agingRequired = TRUE; + agingRequired = true; } } @@ -152,9 +152,9 @@ void ixEthDBDatabaseMaintenance() } else { - ixEthDBPortInfo[portIndex].agingEnabled = FALSE; - ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = FALSE; - ixEthDBPortInfo[portIndex].updateMethod.userControlled = TRUE; + ixEthDBPortInfo[portIndex].agingEnabled = false; + ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false; + ixEthDBPortInfo[portIndex].updateMethod.userControlled = true; ixOsalLog(IX_OSAL_LOG_LVL_FATAL, IX_OSAL_LOG_DEV_STDOUT, @@ -173,7 +173,7 @@ void ixEthDBDatabaseMaintenance() { MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; UINT32 *age = NULL; - BOOL staticEntry = TRUE; + BOOL staticEntry = true; if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) { @@ -187,10 +187,10 @@ void ixEthDBDatabaseMaintenance() } else { - staticEntry = TRUE; + staticEntry = true; } - if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == FALSE)) + if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == false)) { /* manually increment the age if the port has no such capability */ if ((ixEthDBPortDefinitions[descriptor->portID].capabilities & IX_ETH_ENTRY_AGING) == 0) @@ -341,7 +341,7 @@ IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID) IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - ixEthDBPortInfo[portID].agingEnabled = FALSE; + ixEthDBPortInfo[portID].agingEnabled = false; return IX_ETH_DB_SUCCESS; } @@ -355,7 +355,7 @@ IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID) IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - ixEthDBPortInfo[portID].agingEnabled = TRUE; + ixEthDBPortInfo[portID].agingEnabled = true; return IX_ETH_DB_SUCCESS; } @@ -442,7 +442,7 @@ IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING); ixEthDBPortInfo[portID].updateMethod.updateEnabled = enableUpdate; - ixEthDBPortInfo[portID].updateMethod.userControlled = TRUE; + ixEthDBPortInfo[portID].updateMethod.userControlled = true; return IX_ETH_DB_SUCCESS; } diff --git a/drivers/net/npe/IxEthDBAPISupport.c b/drivers/net/npe/IxEthDBAPISupport.c index 36bc200a3..1facb89fd 100644 --- a/drivers/net/npe/IxEthDBAPISupport.c +++ b/drivers/net/npe/IxEthDBAPISupport.c @@ -128,18 +128,18 @@ void ixEthDBPortInit(IxEthDBPortId portID) SET_DEPENDENCY_MAP(portInfo->dependencyPortMap, portID); /* default values */ - portInfo->agingEnabled = FALSE; - portInfo->enabled = FALSE; - portInfo->macAddressUploaded = FALSE; + portInfo->agingEnabled = false; + portInfo->enabled = false; + portInfo->macAddressUploaded = false; portInfo->maxRxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE; portInfo->maxTxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE; /* default update control values */ portInfo->updateMethod.searchTree = NULL; - portInfo->updateMethod.searchTreePendingWrite = FALSE; - portInfo->updateMethod.treeInitialized = FALSE; - portInfo->updateMethod.updateEnabled = FALSE; - portInfo->updateMethod.userControlled = FALSE; + portInfo->updateMethod.searchTreePendingWrite = false; + portInfo->updateMethod.treeInitialized = false; + portInfo->updateMethod.updateEnabled = false; + portInfo->updateMethod.userControlled = false; /* default WiFi parameters */ memset(portInfo->bbsid, 0, sizeof (portInfo->bbsid)); @@ -153,9 +153,9 @@ void ixEthDBPortInit(IxEthDBPortId portID) } /* initialize state save */ - ixEthDBPortState[portID].saved = FALSE; + ixEthDBPortState[portID].saved = false; - portInfo->initialized = TRUE; + portInfo->initialized = true; } /** @@ -190,7 +190,7 @@ IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) SET_DEPENDENCY_MAP(triggerPorts, portID); /* mark as enabled */ - portInfo->enabled = TRUE; + portInfo->enabled = true; /* Operation stops here when Ethernet Learning is not enabled */ if(IX_FEATURE_CTRL_SWCONFIG_DISABLED == @@ -214,7 +214,7 @@ IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) if (!portInfo->updateMethod.userControlled && ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0)) { - portInfo->updateMethod.updateEnabled = TRUE; + portInfo->updateMethod.updateEnabled = true; } /* if this is first time initialization then we already have @@ -227,7 +227,7 @@ IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) ixEthDBUpdatePortLearningTrees(triggerPorts); /* mark tree as being initialized */ - portInfo->updateMethod.treeInitialized = TRUE; + portInfo->updateMethod.treeInitialized = true; } } @@ -262,7 +262,7 @@ IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) ixEthDBFilteringPortMaximumTxFrameSizeSet(portID, ixEthDBPortState[portID].maxTxFrameSize); /* discard previous save */ - ixEthDBPortState[portID].saved = FALSE; + ixEthDBPortState[portID].saved = false; } IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Enabling succeeded for port %d\n", portID); @@ -321,7 +321,7 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) memcpy(ixEthDBPortState[portID].transmitTaggingInfo, portInfo->transmitTaggingInfo, sizeof (IxEthDBVlanSet)); memcpy(ixEthDBPortState[portID].priorityTable, portInfo->priorityTable, sizeof (IxEthDBPriorityTable)); - ixEthDBPortState[portID].saved = TRUE; + ixEthDBPortState[portID].saved = true; /* now turn off all EthDB filtering features on the port */ @@ -330,7 +330,7 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) { ixEthDBPortVlanMembershipRangeAdd((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID); - ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, FALSE); + ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, false); ixEthDBAcceptableFrameTypeSet((IxEthDBPortId) portID, IX_ETH_DB_ACCEPT_ALL_FRAMES); ixEthDBIngressVlanTaggingEnabledSet((IxEthDBPortId) portID, IX_ETH_DB_PASS_THROUGH); @@ -342,7 +342,7 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) /* STP */ if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) { - ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, FALSE); + ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, false); } /* Firewall */ @@ -350,7 +350,7 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) { ixEthDBFirewallModeSet((IxEthDBPortId) portID, IX_ETH_DB_FIREWALL_BLACK_LIST); ixEthDBFirewallTableDownload((IxEthDBPortId) portID); - ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, FALSE); + ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, false); } /* Frame size filter */ @@ -413,18 +413,18 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) } /* mark as disabled */ - portInfo->enabled = FALSE; + portInfo->enabled = false; /* disable updates unless the user has specifically altered the default behavior */ if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) { if (!portInfo->updateMethod.userControlled) { - portInfo->updateMethod.updateEnabled = FALSE; + portInfo->updateMethod.updateEnabled = false; } /* make sure we re-initialize the NPE learning tree when the port is re-enabled */ - portInfo->updateMethod.treeInitialized = FALSE; + portInfo->updateMethod.treeInitialized = false; } ixEthDBUpdateUnlock(); @@ -668,7 +668,7 @@ IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAdd if (result == IX_SUCCESS) { - ixEthDBPortInfo[portID].macAddressUploaded = TRUE; + ixEthDBPortInfo[portID].macAddressUploaded = true; } return result; diff --git a/drivers/net/npe/IxEthDBCore.c b/drivers/net/npe/IxEthDBCore.c index 25b7cbb8b..8b3c1d9a8 100644 --- a/drivers/net/npe/IxEthDBCore.c +++ b/drivers/net/npe/IxEthDBCore.c @@ -51,7 +51,7 @@ IX_ETH_DB_PUBLIC BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyType[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; /* private initialization flag */ -IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = FALSE; +IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = false; /** * @brief initializes EthDB @@ -124,7 +124,7 @@ IxEthDBStatus ixEthDBInit(void) ixEthDBFeatureCapabilityScan(); } - ethDBInitializationComplete = TRUE; + ethDBInitializationComplete = true; return result; } @@ -179,7 +179,7 @@ IxEthDBStatus ixEthDBUnload(void) ixOsalMutexDestroy(&ixEthDBPortInfo[portIndex].npeAckLock); } - ixEthDBPortInfo[portIndex].initialized = FALSE; + ixEthDBPortInfo[portIndex].initialized = false; } /* shutdown event processor */ @@ -188,7 +188,7 @@ IxEthDBStatus ixEthDBUnload(void) /* deallocate NPE update zones */ ixEthDBNPEUpdateAreasUnload(); - ethDBInitializationComplete = FALSE; + ethDBInitializationComplete = false; return IX_ETH_DB_SUCCESS; } diff --git a/drivers/net/npe/IxEthDBEvents.c b/drivers/net/npe/IxEthDBEvents.c index 4d44e0333..529063d1f 100644 --- a/drivers/net/npe/IxEthDBEvents.c +++ b/drivers/net/npe/IxEthDBEvents.c @@ -61,8 +61,8 @@ IX_ETH_DB_PRIVATE PortEventQueue eventQueue; IX_ETH_DB_PRIVATE IxOsalMutex eventQueueLock; IX_ETH_DB_PRIVATE IxOsalMutex portUpdateLock; -IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown = FALSE; -IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = FALSE; +IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown = false; +IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = false; /* imported data */ extern HashTable dbHashtable; @@ -143,7 +143,7 @@ IxEthDBStatus ixEthDBStartLearningFunction(void) return IX_ETH_DB_FAIL; } - ixEthDBLearningShutdown = FALSE; + ixEthDBLearningShutdown = false; /* create processor loop thread */ if (ixOsalThreadCreate(&eventProcessorThread, &threadAttr, ixEthDBEventProcessorLoop, NULL) != IX_SUCCESS) @@ -173,7 +173,7 @@ IxEthDBStatus ixEthDBStartLearningFunction(void) IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void) { - ixEthDBLearningShutdown = TRUE; + ixEthDBLearningShutdown = true; /* wake up event processing loop to actually process the shutdown event */ ixOsalSemaphorePost(&eventQueueSemaphore); @@ -253,13 +253,13 @@ void ixEthDBEventProcessorLoop(void *unused1) IxEthDBPortMap triggerPorts; IxEthDBPortId portIndex; - ixEthDBEventProcessorRunning = TRUE; + ixEthDBEventProcessorRunning = true; IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n"); while (!ixEthDBLearningShutdown) { - BOOL keepProcessing = TRUE; + BOOL keepProcessing = true; UINT32 processedEvents = 0; IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n"); @@ -302,7 +302,7 @@ void ixEthDBEventProcessorLoop(void *unused1) if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */ || ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */ { - keepProcessing = FALSE; + keepProcessing = false; } } @@ -313,10 +313,10 @@ void ixEthDBEventProcessorLoop(void *unused1) /* turn off automatic updates */ for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) { - ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = FALSE; + ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false; } - ixEthDBEventProcessorRunning = FALSE; + ixEthDBEventProcessorRunning = false; } /** @@ -381,7 +381,7 @@ void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts) * * @param macAddr MAC address of the new record * @param portID port ID of the new record - * @param staticEntry TRUE if record is static, FALSE if dynamic + * @param staticEntry true if record is static, false if dynamic * * @return IX_ETH_DB_SUCCESS if the event creation was * successfull or IX_ETH_DB_BUSY if the event queue is full @@ -430,7 +430,7 @@ IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPor { if (ixEthDBPeek(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS) != IX_ETH_DB_NO_SUCH_ADDR) { - return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, FALSE); + return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, false); } else { diff --git a/drivers/net/npe/IxEthDBFeatures.c b/drivers/net/npe/IxEthDBFeatures.c index 7a58d268c..c5b680a74 100644 --- a/drivers/net/npe/IxEthDBFeatures.c +++ b/drivers/net/npe/IxEthDBFeatures.c @@ -169,7 +169,7 @@ void ixEthDBFeatureCapabilityScan(void) /* enable port, VLAN and Firewall feature bits to initialize QoS/VLAN/Firewall configuration */ portInfo->featureStatus |= IX_ETH_DB_VLAN_QOS; portInfo->featureStatus |= IX_ETH_DB_FIREWALL; - portInfo->enabled = TRUE; + portInfo->enabled = true; #define CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ #ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ @@ -195,7 +195,7 @@ void ixEthDBFeatureCapabilityScan(void) ixEthDBPortVlanMembershipRangeRemove(portIndex, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID); /* clear TTI table - no VLAN tagged frames will be transmitted */ - ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, FALSE); + ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, false); /* set membership on 0, otherwise no Tx or Rx is working */ ixEthDBPortVlanMembershipAdd(portIndex, 0); @@ -221,12 +221,12 @@ void ixEthDBFeatureCapabilityScan(void) #endif /* by default we turn off invalid source MAC address filtering */ - ixEthDBFirewallInvalidAddressFilterEnable(portIndex, FALSE); + ixEthDBFirewallInvalidAddressFilterEnable(portIndex, false); /* disable port, VLAN, Firewall feature bits */ portInfo->featureStatus &= ~IX_ETH_DB_VLAN_QOS; portInfo->featureStatus &= ~IX_ETH_DB_FIREWALL; - portInfo->enabled = FALSE; + portInfo->enabled = false; /* enable filtering by default if present */ if ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0) @@ -271,7 +271,7 @@ IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature * * * @param portID ID of the port * @param feature feature to enable or disable - * @param enabled TRUE to enable the selected feature or FALSE to disable it + * @param enabled true to enable the selected feature or false to disable it * * Note that this function is documented in the main component * header file, IxEthDB.h. @@ -333,7 +333,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, } /* force port enabled */ - portInfo->enabled = TRUE; + portInfo->enabled = true; if (enable) { @@ -399,7 +399,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, /* enable TPID port extraction */ if (status == IX_ETH_DB_SUCCESS) { - status = ixEthDBVlanPortExtractionEnable(portID, TRUE); + status = ixEthDBVlanPortExtractionEnable(portID, true); } } else if (feature == IX_ETH_DB_FIREWALL) @@ -414,7 +414,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, if (status == IX_ETH_DB_SUCCESS) { - status = ixEthDBFirewallInvalidAddressFilterEnable(portID, FALSE); + status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false); } } } @@ -445,7 +445,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, if (status == IX_ETH_DB_SUCCESS) { - status = ixEthDBFirewallInvalidAddressFilterEnable(portID, FALSE); + status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false); } if (status == IX_ETH_DB_SUCCESS) @@ -515,7 +515,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, /* disable TPID port extraction */ if (status == IX_ETH_DB_SUCCESS) { - status = ixEthDBVlanPortExtractionEnable(portID, FALSE); + status = ixEthDBVlanPortExtractionEnable(portID, false); } } #endif @@ -538,9 +538,9 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, * * @param portID port ID * @param present location to store a boolean value indicating - * if the feature is present (TRUE) or not (FALSE) + * if the feature is present (true) or not (false) * @param enabled location to store a booleam value indicating - * if the feature is present (TRUE) or not (FALSE) + * if the feature is present (true) or not (false) * * Note that this function is documented in the main component * header file, IxEthDB.h. diff --git a/drivers/net/npe/IxEthDBFirewall.c b/drivers/net/npe/IxEthDBFirewall.c index eb46174b6..6fb5ab6ac 100644 --- a/drivers/net/npe/IxEthDBFirewall.c +++ b/drivers/net/npe/IxEthDBFirewall.c @@ -72,7 +72,7 @@ IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 UINT32 mode = 0; PortInfo *portInfo = &ixEthDBPortInfo[portID]; - mode = (portInfo->srcAddressFilterEnabled != FALSE) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST); + mode = (portInfo->srcAddressFilterEnabled != false) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST); FILL_SETFIREWALLMODE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), @@ -123,8 +123,8 @@ IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode m * @brief enables or disables the invalid source MAC address filter * * @param portID ID of the port - * @param enable TRUE to enable invalid source MAC address filtering - * or FALSE to disable it + * @param enable true to enable invalid source MAC address filtering + * or false to disable it * * The invalid source MAC address filter will discard, when enabled, * frames whose source MAC address is a multicast or the broadcast MAC diff --git a/drivers/net/npe/IxEthDBLearning.c b/drivers/net/npe/IxEthDBLearning.c index 2287dbe96..840674152 100644 --- a/drivers/net/npe/IxEthDBLearning.c +++ b/drivers/net/npe/IxEthDBLearning.c @@ -105,8 +105,8 @@ UINT32 ixEthDBKeyXORHash(void *key) * collisions, i.e. descriptors with different mac addresses and the same * hash value, where this function is used to differentiate entries. * - * @retval TRUE if the entry matches the reference key (equal addresses) - * @retval FALSE if the entry does not match the reference key + * @retval true if the entry matches the reference key (equal addresses) + * @retval false if the entry does not match the reference key * * @internal */ diff --git a/drivers/net/npe/IxEthDBNPEAdaptor.c b/drivers/net/npe/IxEthDBNPEAdaptor.c index 112a46c99..d47ffec8b 100644 --- a/drivers/net/npe/IxEthDBNPEAdaptor.c +++ b/drivers/net/npe/IxEthDBNPEAdaptor.c @@ -203,7 +203,7 @@ void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSi /* debug */ IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) checking node at offset %d...\n", eltEntryOffset / ELT_ENTRY_SIZE); - if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != TRUE) + if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != true) { IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is empty\n"); } diff --git a/drivers/net/npe/IxEthDBPortUpdate.c b/drivers/net/npe/IxEthDBPortUpdate.c index cdf114bfc..813e4ee6b 100644 --- a/drivers/net/npe/IxEthDBPortUpdate.c +++ b/drivers/net/npe/IxEthDBPortUpdate.c @@ -60,7 +60,7 @@ extern HashTable dbHashtable; * * @param typeArray array indexed on record types, each * element indicating whether the record type requires an - * automatic update (TRUE) or not (FALSE) + * automatic update (true) or not (false) * * Automatic updates are done for registered record types * upon adding, updating (that is, updating the record portID) @@ -70,7 +70,7 @@ extern HashTable dbHashtable; * * It is assumed that the typeArray parameter is allocated large * enough to hold all the user defined types. Also, the type - * array should be initialized to FALSE as this function only + * array should be initialized to false as this function only * caters for types which do require automatic updates. * * Note that this function should be called by the component @@ -84,8 +84,8 @@ extern HashTable dbHashtable; IX_ETH_DB_PUBLIC UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray) { - typeArray[IX_ETH_DB_FILTERING_RECORD] = TRUE; - typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = TRUE; + typeArray[IX_ETH_DB_FILTERING_RECORD] = true; + typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = true; return 2; } @@ -174,7 +174,7 @@ void ixEthDBCreateTrees(IxEthDBPortMap updatePorts) { UINT32 portIndex; BOOL result; - BOOL portsLeft = TRUE; + BOOL portsLeft = true; while (portsLeft) { @@ -305,11 +305,11 @@ void ixEthDBCreateTrees(IxEthDBPortMap updatePorts) } /* mark tree as valid */ - port->updateMethod.searchTreePendingWrite = TRUE; + port->updateMethod.searchTreePendingWrite = true; } else { - portsLeft = FALSE; + portsLeft = false; IX_ETH_DB_UPDATE_TRACE("DB: (Update) No trees to create this round\n"); } @@ -374,7 +374,7 @@ IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType ty /* forget last used search tree */ port->updateMethod.searchTree = NULL; - port->updateMethod.searchTreePendingWrite = FALSE; + port->updateMethod.searchTreePendingWrite = false; /* dependending on the update type we do different things */ if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD) @@ -393,9 +393,9 @@ IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType ty } else { - ixEthDBPortInfo[portID].agingEnabled = FALSE; - ixEthDBPortInfo[portID].updateMethod.updateEnabled = FALSE; - ixEthDBPortInfo[portID].updateMethod.userControlled = TRUE; + ixEthDBPortInfo[portID].agingEnabled = false; + ixEthDBPortInfo[portID].updateMethod.updateEnabled = false; + ixEthDBPortInfo[portID].updateMethod.userControlled = true; ERROR_LOG("EthDB: (PortUpdate) disabling aging and updates on port %d (assumed dead)\n", portID); diff --git a/drivers/net/npe/IxEthDBReports.c b/drivers/net/npe/IxEthDBReports.c index 9c7ae1cc6..912e60861 100644 --- a/drivers/net/npe/IxEthDBReports.c +++ b/drivers/net/npe/IxEthDBReports.c @@ -62,7 +62,7 @@ IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map) { UINT32 portIndex; - BOOL mapSelf = TRUE, mapNone = TRUE, firstPort = TRUE; + BOOL mapSelf = true, mapNone = true, firstPort = true; /* dependency port maps */ printf("Dependency port map: "); @@ -72,22 +72,22 @@ IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap { if (IS_PORT_INCLUDED(portIndex, map)) { - mapNone = FALSE; + mapNone = false; if (portIndex != portID) { - mapSelf = FALSE; + mapSelf = false; } printf("%s%d", firstPort ? "{" : ", ", portIndex); - firstPort = FALSE; + firstPort = false; } } if (mapNone) { - mapSelf = FALSE; + mapSelf = false; } printf("%s (%s)\n", firstPort ? "" : "}", mapSelf ? "self" : mapNone ? "none" : "group"); diff --git a/drivers/net/npe/IxEthDBSearch.c b/drivers/net/npe/IxEthDBSearch.c index 4a10878b6..75fdebe48 100644 --- a/drivers/net/npe/IxEthDBSearch.c +++ b/drivers/net/npe/IxEthDBSearch.c @@ -50,7 +50,7 @@ extern HashTable dbHashtable; * @param untypedReference record to match against * @param untypedEntry record to match * - * @return TRUE if the match is successful or FALSE otherwise + * @return true if the match is successful or false otherwise * * @internal */ @@ -61,7 +61,7 @@ BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry) MacDescriptor *reference = (MacDescriptor *) untypedReference; /* check accepted record types */ - if ((entry->type & reference->type) == 0) return FALSE; + if ((entry->type & reference->type) == 0) return false; return (ixEthDBAddressCompare((UINT8 *) entry->macAddress, (UINT8 *) reference->macAddress) == 0); } @@ -73,7 +73,7 @@ BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry) * @param untypedReference record to match against * @param untypedEntry record to match * - * @return TRUE if the match is successful or FALSE otherwise + * @return true if the match is successful or false otherwise * * @internal */ @@ -84,7 +84,7 @@ BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry) MacDescriptor *reference = (MacDescriptor *) untypedReference; /* check accepted record types */ - if ((entry->type & reference->type) == 0) return FALSE; + if ((entry->type & reference->type) == 0) return false; return (IX_ETH_DB_GET_VLAN_ID(entry->recordData.filteringVlanData.ieee802_1qTag) == IX_ETH_DB_GET_VLAN_ID(reference->recordData.filteringVlanData.ieee802_1qTag)) && @@ -98,7 +98,7 @@ BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry) * @param untypedReference record to match against * @param untypedEntry record to match * - * @return TRUE if the match is successful or FALSE otherwise + * @return true if the match is successful or false otherwise * * @internal */ @@ -109,7 +109,7 @@ BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry) MacDescriptor *reference = (MacDescriptor *) untypedReference; /* check accepted record types */ - if ((entry->type & reference->type) == 0) return FALSE; + if ((entry->type & reference->type) == 0) return false; return (entry->portID == reference->portID) && (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0); @@ -125,7 +125,7 @@ BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry) * array on invalid types. Calling it will display an * error message, indicating an error in the component logic. * - * @return FALSE + * @return false * * @internal */ @@ -137,7 +137,7 @@ BOOL ixEthDBNullMatch(void *reference, void *entry) ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, "DB: (Search) The NullMatch function was called, wrong key type?\n", 0, 0, 0, 0, 0, 0); - return FALSE; + return false; } /** diff --git a/drivers/net/npe/IxEthDBSpanningTree.c b/drivers/net/npe/IxEthDBSpanningTree.c index 6d9fd6ec1..029f7ac93 100644 --- a/drivers/net/npe/IxEthDBSpanningTree.c +++ b/drivers/net/npe/IxEthDBSpanningTree.c @@ -49,7 +49,7 @@ * @brief sets the STP blocking state of a port * * @param portID ID of the port - * @param blocked TRUE to block the port or FALSE to unblock it + * @param blocked true to block the port or false to unblock it * * Note that this function is documented in the main component * header file, IxEthDB.h. diff --git a/drivers/net/npe/IxEthDBUtil.c b/drivers/net/npe/IxEthDBUtil.c index e708bf1bc..24acc246b 100644 --- a/drivers/net/npe/IxEthDBUtil.c +++ b/drivers/net/npe/IxEthDBUtil.c @@ -94,13 +94,13 @@ BOOL ixEthDBCheckSingleBitValue(UINT32 value) while (value != 0) { - if (value == 1) return TRUE; - else if ((value & 1) == 1) return FALSE; + if (value == 1) return true; + else if ((value & 1) == 1) return false; value >>= 1; } - return FALSE; + return false; #endif } diff --git a/drivers/net/npe/IxEthDBVlan.c b/drivers/net/npe/IxEthDBVlan.c index e2efb9b33..522a30b1d 100644 --- a/drivers/net/npe/IxEthDBVlan.c +++ b/drivers/net/npe/IxEthDBVlan.c @@ -642,7 +642,7 @@ IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet * * @param portID ID of the port * @param vlanID VLAN ID to enable or disable Egress tagging on - * @param enabled TRUE to enable and FALSE to disable tagging + * @param enabled true to enable and false to disable tagging * * Note that this function is documented in the main component * header file, IxEthDB.h. @@ -670,7 +670,7 @@ IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEt * @param portID ID of the port * @param vlanID VLAN ID to retrieve the tagging status for * @param enabled location to store the tagging status - * (TRUE - tagging enabled, FALSE - tagging disabled) + * (true - tagging enabled, false - tagging disabled) * * Note that this function is documented in the main component * header file, IxEthDB.h. @@ -702,7 +702,7 @@ IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEt * @param portID ID of the port * @param vlanIDMin start of VLAN range * @param vlanIDMax end of VLAN range - * @param enabled TRUE to enable or FALSE to disable VLAN tagging + * @param enabled true to enable or false to disable VLAN tagging * * Note that this function is documented in the main component * header file, IxEthDB.h. @@ -1151,7 +1151,7 @@ IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriori * from the VLAN TPID field * * @param portID ID of the port - * @param enable TRUE to enable or FALSE to disable + * @param enable true to enable or false to disable * * Note that this function is documented in the main component * header file, IxEthDB.h. diff --git a/drivers/net/npe/IxEthMii.c b/drivers/net/npe/IxEthMii.c index 4d92f17ee..f8b439d9d 100644 --- a/drivers/net/npe/IxEthMii.c +++ b/drivers/net/npe/IxEthMii.c @@ -65,7 +65,7 @@ PRIVATE UINT32 ixEthMiiPhyId[IXP425_ETH_ACC_MII_MAX_ADDR]; * Scan for PHYs on the MII bus. This function returns * an array of booleans, one for each PHY address. * If a PHY is found at a particular address, the - * corresponding entry in the array is set to TRUE. + * corresponding entry in the array is set to true. * */ @@ -89,7 +89,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) i<IXP425_ETH_ACC_MII_MAX_ADDR; i++) { - phyPresent[i] = FALSE; + phyPresent[i] = false; } /* iterate through the PHY addresses */ @@ -119,7 +119,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) ) { /* supported phy */ - phyPresent[i] = TRUE; + phyPresent[i] = true; } /* end of if(ixEthMiiPhyId) */ else { @@ -131,7 +131,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) "ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n", ixEthMiiPhyId[i], 2, 3, 4, 5, 6); ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID; - phyPresent[i] = TRUE; + phyPresent[i] = true; } } } @@ -347,10 +347,10 @@ ixEthMiiLinkStatus(UINT32 phyAddr, return IX_FAIL; } - *linkUp = FALSE; - *speed100 = FALSE; - *fullDuplex = FALSE; - *autoneg = FALSE; + *linkUp = false; + *speed100 = false; + *fullDuplex = false; + *autoneg = false; if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) && (ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID)) @@ -406,20 +406,20 @@ ixEthMiiLinkStatus(UINT32 phyAddr, if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0) { /* 100 Base X full dplx */ - *speed100 = TRUE; - *fullDuplex = TRUE; + *speed100 = true; + *fullDuplex = true; return IX_SUCCESS; } if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0) { /* 100 Base X half dplx */ - *speed100 = TRUE; + *speed100 = true; return IX_SUCCESS; } if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0) { /* 10 mb full dplx */ - *fullDuplex = TRUE; + *fullDuplex = true; return IX_SUCCESS; } if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0) diff --git a/drivers/net/npe/IxFeatureCtrl.c b/drivers/net/npe/IxFeatureCtrl.c index 2e196a19a..b6728e4a4 100644 --- a/drivers/net/npe/IxFeatureCtrl.c +++ b/drivers/net/npe/IxFeatureCtrl.c @@ -72,7 +72,7 @@ IX_OSAL_WRITE_LONG(ixFeatureCtrlRegister, (value)); \ /* Boolean to mark the fact that the EXP_CONFIG address space was mapped */ -PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = FALSE; +PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = false; /* Pointer holding the virtual address of the Feature Control Register */ PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL; @@ -81,7 +81,7 @@ PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL; PRIVATE BOOL swConfiguration[IX_FEATURECTRL_SWCONFIG_MAX]; /* Flag to control swConfiguration[] is initialized once */ -PRIVATE BOOL swConfigurationFlag = FALSE ; +PRIVATE BOOL swConfigurationFlag = false ; /* Array containing component mask values */ #ifdef __ixp42X @@ -158,7 +158,7 @@ void ixFeatureCtrlExpMap(void) /* If the EXP Configuration space has already been mapped then * return */ - if (ixFeatureCtrlExpCfgRegionMapped == TRUE) + if (ixFeatureCtrlExpCfgRegionMapped == true) { return; } @@ -176,7 +176,7 @@ void ixFeatureCtrlExpMap(void) (VUINT32 *) (expCfgBaseAddress + IX_FEATURE_CTRL_REG_OFFSET); /* Mark the fact that the EXP_CONFIG space has already been mapped */ - ixFeatureCtrlExpCfgRegionMapped = TRUE; + ixFeatureCtrlExpCfgRegionMapped = true; } /** @@ -186,15 +186,15 @@ void ixFeatureCtrlExpMap(void) PRIVATE void ixFeatureCtrlSwConfigurationInit(void) { UINT32 i; - if (FALSE == swConfigurationFlag) + if (false == swConfigurationFlag) { for (i=0; i<IX_FEATURECTRL_SWCONFIG_MAX ; i++) { /* By default, all software configuration are enabled */ - swConfiguration[i]= TRUE ; + swConfiguration[i]= true ; } /*Make sure this function only initializes swConfiguration[] once*/ - swConfigurationFlag = TRUE ; + swConfigurationFlag = true ; } } @@ -326,7 +326,7 @@ ixFeatureCtrlProductIdRead () extern IxFeatureCtrlProductId AsmixFeatureCtrlProductIdRead(); #ifndef IN_KERNEL - mode = SetKMode(TRUE); + mode = SetKMode(true); #endif pdId = AsmixFeatureCtrlProductIdRead(); #ifndef IN_KERNEL @@ -372,7 +372,7 @@ ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType) ixFeatureCtrlSwConfigurationInit(); /* Check and return software configuration */ - return ((swConfiguration[(UINT32)swConfigType] == TRUE) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED); + return ((swConfiguration[(UINT32)swConfigType] == true) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED); } /** diff --git a/drivers/net/npe/IxNpeDl.c b/drivers/net/npe/IxNpeDl.c index 373833753..bfeac8779 100644 --- a/drivers/net/npe/IxNpeDl.c +++ b/drivers/net/npe/IxNpeDl.c @@ -89,9 +89,9 @@ typedef struct */ static IxNpeDlNpeState ixNpeDlNpeState[IX_NPEDL_NPEID_MAX] = { - {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, - {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, - {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}} + {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, + {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, + {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}} }; static IxNpeDlStats ixNpeDlStats; @@ -99,7 +99,7 @@ static IxNpeDlStats ixNpeDlStats; /* * Software guard to prevent NPE from being started multiple times. */ -static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={FALSE, FALSE, FALSE} ; +static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={false, false, false} ; /* @@ -195,7 +195,7 @@ ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr, if (IX_SUCCESS == status) { ixNpeDlNpeState[npeId].imageId = *imageIdPtr; - ixNpeDlNpeState[npeId].validImage = TRUE; + ixNpeDlNpeState[npeId].validImage = true; ixNpeDlStats.successfulDownloads++; status = ixNpeDlNpeExecutionStart (npeId); @@ -204,7 +204,7 @@ ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr, (status == IX_NPEDL_CRITICAL_MICROCODE_ERR)) { ixNpeDlNpeState[npeId].imageId = *imageIdPtr; - ixNpeDlNpeState[npeId].validImage = FALSE; + ixNpeDlNpeState[npeId].validImage = false; ixNpeDlStats.criticalFailDownloads++; } } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */ @@ -507,7 +507,7 @@ ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId) if (IX_SUCCESS == status) { /* Indicate NPE has been stopped */ - ixNpeDlNpeStarted[npeId] = FALSE ; + ixNpeDlNpeStarted[npeId] = false ; } return status; @@ -573,7 +573,7 @@ ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId) } /* end of if-else(IX_NPEDL_NPEID_NPEC) */ } /* end of if not IXP42x-A0 Silicon */ - if (TRUE == ixNpeDlNpeStarted[npeId]) + if (true == ixNpeDlNpeStarted[npeId]) { /* NPE has been started. */ return IX_SUCCESS ; @@ -588,7 +588,7 @@ ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId) if (IX_SUCCESS == status) { /* Indicate NPE has started */ - ixNpeDlNpeStarted[npeId] = TRUE ; + ixNpeDlNpeStarted[npeId] = true ; } IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, @@ -674,7 +674,7 @@ ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId) if (IX_SUCCESS == status) { /* Indicate NPE has been stopped */ - ixNpeDlNpeStarted[npeId] = FALSE ; + ixNpeDlNpeStarted[npeId] = false ; } return status; @@ -840,10 +840,10 @@ ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, * currently loaded images. If a critical error occured * during download, record that the NPE has an invalid image */ - status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, TRUE); + status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, true); if (IX_SUCCESS == status) { - ixNpeDlNpeState[npeId].validImage = TRUE; + ixNpeDlNpeState[npeId].validImage = true; ixNpeDlStats.successfulDownloads++; status = ixNpeDlNpeExecutionStart (npeId); @@ -851,7 +851,7 @@ ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) || (status == IX_NPEDL_CRITICAL_MICROCODE_ERR)) { - ixNpeDlNpeState[npeId].validImage = FALSE; + ixNpeDlNpeState[npeId].validImage = false; ixNpeDlStats.criticalFailDownloads++; } diff --git a/drivers/net/npe/IxNpeDlImageMgr.c b/drivers/net/npe/IxNpeDlImageMgr.c index 9bcdc9c0d..048448388 100644 --- a/drivers/net/npe/IxNpeDlImageMgr.c +++ b/drivers/net/npe/IxNpeDlImageMgr.c @@ -414,11 +414,11 @@ ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary) { IxNpeDlImageMgrImageLibraryHeader *header = (IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary; - BOOL result = TRUE; + BOOL result = true; if (!header || header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE) { - result = FALSE; + result = false; ixNpeDlImageMgrStats.invalidSignature++; } @@ -469,11 +469,11 @@ ixNpeDlImageMgrImageIdCompare ( (imageIdA->major == imageIdB->major) && (imageIdA->minor == imageIdB->minor)) { - return TRUE; + return true; } else { - return FALSE; + return false; } } @@ -491,11 +491,11 @@ ixNpeDlImageMgrNpeFunctionIdCompare ( if ((imageIdA->npeId == imageIdB->npeId) && (imageIdA->functionalityId == imageIdB->functionalityId)) { - return TRUE; + return true; } else { - return FALSE; + return false; } } @@ -550,7 +550,7 @@ ixNpeDlImageMgrImageFind_legacy ( UINT32 imageCount = 0; IX_STATUS status = IX_FAIL; IxNpeDlImageMgrImageLibraryHeader *header; - BOOL imageFound = FALSE; + BOOL imageFound = false; IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, "Entering ixNpeDlImageMgrImageFind\n"); @@ -584,7 +584,7 @@ ixNpeDlImageMgrImageFind_legacy ( /* get the image size */ *imageSize = header->entry[imageCount].image.size; status = IX_SUCCESS; - imageFound = TRUE; + imageFound = true; } imageCount++; } diff --git a/drivers/net/npe/IxNpeDlNpeMgr.c b/drivers/net/npe/IxNpeDlNpeMgr.c index a9ea8bc10..aaffeeb0c 100644 --- a/drivers/net/npe/IxNpeDlNpeMgr.c +++ b/drivers/net/npe/IxNpeDlNpeMgr.c @@ -229,7 +229,7 @@ static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] = static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats; /* Set when NPE register memory has been mapped */ -static BOOL ixNpeDlMemInitialised = FALSE; +static BOOL ixNpeDlMemInitialised = false; /* @@ -290,7 +290,7 @@ ixNpeDlNpeMgrInit (void) IX_OSAL_ASSERT(virtAddr); ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr; - ixNpeDlMemInitialised = TRUE; + ixNpeDlMemInitialised = true; } } @@ -314,7 +314,7 @@ ixNpeDlNpeMgrUninit (void) ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0; ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0; - ixNpeDlMemInitialised = FALSE; + ixNpeDlMemInitialised = false; return IX_SUCCESS; } @@ -662,7 +662,7 @@ ixNpeDlNpeMgrNpeReset ( { /* for each physical register in the NPE reg file, write 0 : */ status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr, - 0, TRUE); + 0, true); if (status != IX_SUCCESS) { return status; /* abort reset */ @@ -684,7 +684,7 @@ ixNpeDlNpeMgrNpeReset ( { regVal = ixNpeDlCtxtRegResetValues[ctxtReg]; status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, - ctxtReg, regVal, TRUE); + ctxtReg, regVal, true); if (status != IX_SUCCESS) { return status; /* abort reset */ diff --git a/drivers/net/npe/IxNpeMh.c b/drivers/net/npe/IxNpeMh.c index 8703def8b..2870ff7da 100644 --- a/drivers/net/npe/IxNpeMh.c +++ b/drivers/net/npe/IxNpeMh.c @@ -79,7 +79,7 @@ * static variables. */ -PRIVATE BOOL ixNpeMhInitialized = FALSE; +PRIVATE BOOL ixNpeMhInitialized = false; /* * Extern function prototypes. @@ -128,7 +128,7 @@ PUBLIC IX_STATUS ixNpeMhInitialize ( */ ixNpeMhConfigInitialize (npeInterrupts); - ixNpeMhInitialized = TRUE; + ixNpeMhInitialized = true; IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " "ixNpeMhInitialize\n"); @@ -153,7 +153,7 @@ PUBLIC IX_STATUS ixNpeMhUnload (void) /* Uninitialize the Configuration module */ ixNpeMhConfigUninit (); - ixNpeMhInitialized = FALSE; + ixNpeMhInitialized = false; IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " "ixNpeMhUnload\n"); diff --git a/drivers/net/npe/IxNpeMhConfig.c b/drivers/net/npe/IxNpeMhConfig.c index 50c8f2113..092d480c6 100644 --- a/drivers/net/npe/IxNpeMhConfig.c +++ b/drivers/net/npe/IxNpeMhConfig.c @@ -105,7 +105,7 @@ IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] = 0, 0, NULL, - FALSE + false }, { 0, @@ -116,7 +116,7 @@ IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] = 0, 0, NULL, - FALSE + false }, { 0, @@ -127,7 +127,7 @@ IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] = 0, 0, NULL, - FALSE + false } }; diff --git a/drivers/net/npe/IxNpeMhSend.c b/drivers/net/npe/IxNpeMhSend.c index 318913ac8..27bc9b730 100644 --- a/drivers/net/npe/IxNpeMhSend.c +++ b/drivers/net/npe/IxNpeMhSend.c @@ -124,7 +124,7 @@ BOOL ixNpeMhSendInFifoIsFull( IxNpeMhNpeId npeId, UINT32 maxSendRetries) { - BOOL isFull = FALSE; + BOOL isFull = false; UINT32 numRetries = 0; /* check the NPE's inFIFO */ diff --git a/drivers/net/npe/IxOsalOsSemaphore.c b/drivers/net/npe/IxOsalOsSemaphore.c index 443aefd4f..672bec118 100644 --- a/drivers/net/npe/IxOsalOsSemaphore.c +++ b/drivers/net/npe/IxOsalOsSemaphore.c @@ -135,10 +135,10 @@ static void drv_mutex_destroy(IxOsalMutex *mutex) static int drv_mutex_trylock(IxOsalMutex *mutex) { - int result = TRUE; + int result = true; if (*mutex == 1) - result = FALSE; + result = false; return result; } diff --git a/drivers/net/npe/IxQMgrDispatcher.c b/drivers/net/npe/IxQMgrDispatcher.c index 9cb143998..25a3e8539 100644 --- a/drivers/net/npe/IxQMgrDispatcher.c +++ b/drivers/net/npe/IxQMgrDispatcher.c @@ -160,7 +160,7 @@ static IxQMgrQId priorityTable[IX_QMGR_MAX_NUM_QUEUES]; /* * This flag indicates to the dispatcher that the priority table needs to be rebuilt. */ -static BOOL rebuildTable = FALSE; +static BOOL rebuildTable = false; /* Dispatcher statistics */ static IxQMgrDispatcherStats dispatcherStats; @@ -197,7 +197,7 @@ ixQMgrDispatcherInit (void) int i; IxFeatureCtrlProductId productId = 0; IxFeatureCtrlDeviceId deviceId = 0; - BOOL stickyIntSilicon = TRUE; + BOOL stickyIntSilicon = true; /* Set default priorities */ for (i=0; i< IX_QMGR_MAX_NUM_QUEUES; i++) @@ -226,7 +226,7 @@ ixQMgrDispatcherInit (void) dispatcherStats.queueStats[i].priorityChangeCnt = 0; dispatcherStats.queueStats[i].intNoCallbackCnt = 0; dispatcherStats.queueStats[i].intLostCallbackCnt = 0; - dispatcherStats.queueStats[i].notificationEnabled = FALSE; + dispatcherStats.queueStats[i].notificationEnabled = false; dispatcherStats.queueStats[i].srcSel = 0; } @@ -258,7 +258,7 @@ ixQMgrDispatcherInit (void) (IX_FEATURE_CTRL_SILICON_TYPE_A0 == (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId))) { - stickyIntSilicon = FALSE; + stickyIntSilicon = false; } /* @@ -293,7 +293,7 @@ ixQMgrDispatcherPrioritySet (IxQMgrQId qId, /* Change priority */ dispatchQInfo[qId].priority = priority; /* Set flag */ - rebuildTable = TRUE; + rebuildTable = true; ixOsalIrqUnlock(ixQMgrLockKey); @@ -364,7 +364,7 @@ ixQMgrNotificationEnable (IxQMgrQId qId, #endif #ifndef NDEBUG - dispatcherStats.queueStats[qId].notificationEnabled = TRUE; + dispatcherStats.queueStats[qId].notificationEnabled = true; dispatcherStats.queueStats[qId].srcSel = srcSel; #endif @@ -428,7 +428,7 @@ ixQMgrNotificationDisable (IxQMgrQId qId) * so need critical section */ #ifndef NDEBUG - dispatcherStats.queueStats[qId].notificationEnabled = FALSE; + dispatcherStats.queueStats[qId].notificationEnabled = false; #endif ixQMgrLockKey = ixOsalIrqLock(); @@ -593,7 +593,7 @@ ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group) qIndex += IX_QMGR_MIN_QUEUPP_QID; } - if (statusChangeFlag == FALSE) + if (statusChangeFlag == false) { /* check if the interrupt register contains * only 1 bit set (happy day scenario) @@ -800,7 +800,7 @@ ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group) * For example: * intRegVal = 0x0010 * currDispatchQInfo->intRegCheckMask = 0x0010 - * intRegVal == currDispatchQInfo->intRegCheckMask is TRUE. + * intRegVal == currDispatchQInfo->intRegCheckMask is true. */ currDispatchQInfo = &dispatchQInfo[qIndex]; if (intRegVal == currDispatchQInfo->intRegCheckMask) @@ -955,7 +955,7 @@ ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group) * For example: * intRegVal = 0x0010 * currDispatchQInfo->intRegCheckMask = 0x0010 - * intRegVal == currDispatchQInfo->intRegCheckMask is TRUE. + * intRegVal == currDispatchQInfo->intRegCheckMask is true. */ currDispatchQInfo = &dispatchQInfo[qIndex]; if (intRegVal == currDispatchQInfo->intRegCheckMask) @@ -1118,7 +1118,7 @@ ixQMgrDispatcherReBuildPriorityTable (void) int uppQuePriorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; /* Reset the rebuild flag */ - rebuildTable = FALSE; + rebuildTable = false; /* initialize the mak used to identify the queues in the first half * of the priority table @@ -1266,7 +1266,7 @@ ixQMgrPeriodicDone (void) * Update statistics */ dispatcherStats.queueStats[i].enableCount++; - dispatcherStats.queueStats[i].notificationEnabled = TRUE; + dispatcherStats.queueStats[i].notificationEnabled = true; #endif } } diff --git a/drivers/net/npe/IxQMgrInit.c b/drivers/net/npe/IxQMgrInit.c index b00c22d08..61ca96c97 100644 --- a/drivers/net/npe/IxQMgrInit.c +++ b/drivers/net/npe/IxQMgrInit.c @@ -66,7 +66,7 @@ * Set to true if initialized * N.B. global so integration/unit tests can reinitialize */ -BOOL qMgrIsInitialized = FALSE; +BOOL qMgrIsInitialized = false; /* * Function definitions. @@ -90,7 +90,7 @@ ixQMgrInit (void) ixQMgrQAccessInit (); /* Initialization complete */ - qMgrIsInitialized = TRUE; + qMgrIsInitialized = true; return IX_SUCCESS; } @@ -107,7 +107,7 @@ ixQMgrUnload (void) ixQMgrQCfgUninit (); /* Uninitialization complete */ - qMgrIsInitialized = FALSE; + qMgrIsInitialized = false; return IX_SUCCESS; } diff --git a/drivers/net/npe/IxQMgrQCfg.c b/drivers/net/npe/IxQMgrQCfg.c index ec7d837c3..26ec327a8 100644 --- a/drivers/net/npe/IxQMgrQCfg.c +++ b/drivers/net/npe/IxQMgrQCfg.c @@ -94,7 +94,7 @@ typedef struct char qName[IX_QMGR_MAX_QNAME_LEN+1]; /* Textual description of a queue*/ IxQMgrQSizeInWords qSizeInWords; /* The number of words in the queue */ IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/ - BOOL isConfigured; /* This flag is TRUE if the queue has + BOOL isConfigured; /* This flag is true if the queue has * been configured */ } IxQMgrCfgQ; @@ -120,7 +120,7 @@ static UINT32 freeSramAddress=0; /* 4 words of zeroed memory for inline access */ static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 }; -static BOOL cfgInitialized = FALSE; +static BOOL cfgInitialized = false; static IxOsalMutex ixQMgrQCfgMutex; @@ -177,10 +177,10 @@ ixQMgrQCfgInit (void) strcpy (cfgQueueInfo[loopIndex].qName, ""); cfgQueueInfo[loopIndex].qSizeInWords = 0; cfgQueueInfo[loopIndex].qEntrySizeInWords = 0; - cfgQueueInfo[loopIndex].isConfigured = FALSE; + cfgQueueInfo[loopIndex].isConfigured = false; /* Statistics */ - stats.qStats[loopIndex].isConfigured = FALSE; + stats.qStats[loopIndex].isConfigured = false; stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName; } @@ -191,13 +191,13 @@ ixQMgrQCfgInit (void) ixOsalMutexInit(&ixQMgrQCfgMutex); - cfgInitialized = TRUE; + cfgInitialized = true; } void ixQMgrQCfgUninit (void) { - cfgInitialized = FALSE; + cfgInitialized = false; /* Uninitialise the AqmIf component */ ixQMgrAqmIfUninit (); @@ -281,13 +281,13 @@ ixQMgrQConfig (char *qName, IX_QMGR_QUE_BUFFER_SPACE_SIZE); /* The queue is now configured */ - cfgQueueInfo[qId].isConfigured = TRUE; + cfgQueueInfo[qId].isConfigured = true; ixOsalMutexUnlock(&ixQMgrQCfgMutex); #ifndef NDEBUG /* Update statistics */ - stats.qStats[qId].isConfigured = TRUE; + stats.qStats[qId].isConfigured = true; stats.qStats[qId].qName = cfgQueueInfo[qId].qName; #endif return IX_SUCCESS; @@ -417,7 +417,7 @@ ixQMgrQIsConfigured (IxQMgrQId qId) { if (!IX_QMGR_QID_IS_VALID(qId)) { - return FALSE; + return false; } return cfgQueueInfo[qId].isConfigured; @@ -487,7 +487,7 @@ watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level) case IX_QMGR_Q_WM_LEVEL64: break; default: - return FALSE; + return false; } /* Check watermark is not bigger than the qSizeInEntries */ @@ -495,10 +495,10 @@ watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level) if ((unsigned)level > qSizeInEntries) { - return FALSE; + return false; } - return TRUE; + return true; } PRIVATE BOOL @@ -512,10 +512,10 @@ qSizeInWordsIsOk (IxQMgrQSizeInWords qSize) case IX_QMGR_Q_SIZE32: case IX_QMGR_Q_SIZE64: case IX_QMGR_Q_SIZE128: - status = TRUE; + status = true; break; default: - status = FALSE; + status = false; break; } @@ -532,10 +532,10 @@ qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize) case IX_QMGR_Q_ENTRY_SIZE1: case IX_QMGR_Q_ENTRY_SIZE2: case IX_QMGR_Q_ENTRY_SIZE4: - status = TRUE; + status = true; break; default: - status = FALSE; + status = false; break; } diff --git a/drivers/net/npe/include/IxAtmdAccCtrl.h b/drivers/net/npe/include/IxAtmdAccCtrl.h index 50ef582f7..7b8734563 100644 --- a/drivers/net/npe/include/IxAtmdAccCtrl.h +++ b/drivers/net/npe/include/IxAtmdAccCtrl.h @@ -1933,12 +1933,12 @@ PUBLIC IX_STATUS ixAtmdAccPortDisable (IxAtmLogicalPort port); * @brief disable a PHY logical port * * This function indicates if the port disable for a port has completed. This -* function will return TRUE if the port has never been enabled. +* function will return true if the port has never been enabled. * * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] * -* @return @li TRUE disable is complete -* @return @li FALSE disable failed, wrong parameter . +* @return @li true disable is complete +* @return @li false disable failed, wrong parameter . * * @note - This function needs internal locks and should not be called * from an interrupt context diff --git a/drivers/net/npe/include/IxEthAcc_p.h b/drivers/net/npe/include/IxEthAcc_p.h index 4e0de8235..eda3e303b 100644 --- a/drivers/net/npe/include/IxEthAcc_p.h +++ b/drivers/net/npe/include/IxEthAcc_p.h @@ -92,7 +92,7 @@ #define IX_ETH_ACC_PUBLIC -#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? TRUE : FALSE ) +#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? true : false ) @@ -286,7 +286,7 @@ extern IxEthAccPortDataInfo ixEthAccPortData[]; #define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized) extern BOOL ixEthAccServiceInit; -#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == TRUE ) +#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == true ) /* * Maximum number of frames to consume from the Rx Frame Q. diff --git a/drivers/net/npe/include/IxEthDB.h b/drivers/net/npe/include/IxEthDB.h index 1189c9a14..dfdfe1ae5 100644 --- a/drivers/net/npe/include/IxEthDB.h +++ b/drivers/net/npe/include/IxEthDB.h @@ -229,7 +229,7 @@ typedef enum IX_ETH_DB_INTEGER_PROPERTY = 0x1, /**< 4 byte unsigned integer type */ IX_ETH_DB_STRING_PROPERTY = 0x2, /**< NULL-terminated string type of maximum 255 characters (including the terminator) */ IX_ETH_DB_MAC_ADDR_PROPERTY = 0x3, /**< 6 byte MAC address type */ - IX_ETH_DB_BOOL_PROPERTY = 0x4 /**< 4 byte boolean type; can contain only TRUE and FALSE values */ + IX_ETH_DB_BOOL_PROPERTY = 0x4 /**< 4 byte boolean type; can contain only true and false values */ } IxEthDBPropertyType; /* list of supported properties for the IX_ETH_DB_VLAN_QOS feature */ @@ -1427,8 +1427,8 @@ IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriori * * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be matched against outgoing frames - * @param enabled BOOL [in] - TRUE to enable Egress VLAN tagging on the port and given VLAN, and - * FALSE to disable Egress VLAN tagging + * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN, and + * false to disable Egress VLAN tagging * * @retval IX_ETH_DB_SUCCESS operation completed successfully * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier @@ -1450,8 +1450,8 @@ IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEt * @param portID [in] - ID of the port to extract the Egress VLAN ID tagging status from * @param vlanID VLAN [in] - ID whose tagging status is to be extracted * @param enabled [in] - user-specifed location where the status is copied to; following - * the successfull execution of this function the value will be TRUE if Egress VLAN - * tagging is enabled for the given port and VLAN ID, and FALSE otherwise + * the successfull execution of this function the value will be true if Egress VLAN + * tagging is enabled for the given port and VLAN ID, and false otherwise * * - Reentrant - no * - ISR Callable - no @@ -1486,8 +1486,8 @@ IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEt * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN range to be matched against outgoing frames * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN range to be matched against outgoing frames - * @param enabled BOOL [in] - TRUE to enable Egress VLAN tagging on the port and given VLAN range, - * and FALSE to disable Egress VLAN tagging + * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN range, + * and false to disable Egress VLAN tagging * * @retval IX_ETH_DB_SUCCESS operation completed successfully * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier @@ -1640,7 +1640,7 @@ IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBT * This feature is disabled by default. * * @param portID ID of the port to configure port ID extraction on - * @param enable TRUE to enable port ID extraction and FALSE to disable it + * @param enable true to enable port ID extraction and false to disable it * * @retval IX_ETH_DB_SUCCESS operation completed successfully * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier @@ -1759,7 +1759,7 @@ IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature * * * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the features on (use IX_ETH_DB_ALL_PORTS for all the ports) * @param feature @ref IxEthDBFeature [in] - feature or feature set to enable or disable - * @param enabled BOOL [in] - TRUE to enable the feature and FALSE to disable it + * @param enabled BOOL [in] - true to enable the feature and false to disable it * * @note Certain features, from a functional point of view, cannot be disabled as such at NPE level; * when such features are set to <i>disabled</i> using the EthDB API they will be configured in such @@ -1786,7 +1786,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, * * This function returns the availability and status for a feature set. * Note that if more than one feature is selected (e.g. IX_ETH_DB_LEARNING | IX_ETH_DB_FILTERING) - * the "present" and "enabled" return values will be set to TRUE only if all the features in the + * the "present" and "enabled" return values will be set to true only if all the features in the * feature set are present and enabled (not only some). * * @param portID @ref IxEthDBPortId [in] - ID of the port @@ -1873,7 +1873,7 @@ IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature fea * - IX_ETH_DB_INTEGER_PROPERTY - 4 bytes are copied from the source location * - IX_ETH_DB_STRING_PROPERTY - the source string will be copied up to the NULL '\0' string terminator, maximum of 255 characters * - IX_ETH_DB_MAC_ADDR_PROPERTY - 6 bytes are copied from the source location - * - IX_ETH_DB_BOOL_PROPERTY - 4 bytes are copied from the source location; the only allowed values are TRUE (1L) and false (0L) + * - IX_ETH_DB_BOOL_PROPERTY - 4 bytes are copied from the source location; the only allowed values are true (1L) and false (0L) * * @see ixEthDBFeaturePropertySet * @@ -2134,7 +2134,7 @@ IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid); * @brief Sets the STP blocked/unblocked state for a port * * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param blocked BOOL [in] - TRUE to set the port as STP blocked, FALSE to set it as unblocked + * @param blocked BOOL [in] - true to set the port as STP blocked, false to set it as unblocked * * @retval IX_ETH_DB_SUCCESS operation completed successfully * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier @@ -2153,7 +2153,7 @@ IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blo * @brief Retrieves the STP blocked/unblocked state for a port * * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param blocked BOOL * [in] - set to TRUE if the port is STP blocked, FALSE otherwise + * @param blocked BOOL * [in] - set to true if the port is STP blocked, false otherwise * * @retval IX_ETH_DB_SUCCESS operation completed successfully * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier @@ -2214,7 +2214,7 @@ IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode m * NPE image. * * @param portID ID of the port - * @param enable TRUE to enable invalid MAC address filtering and FALSE to disable it + * @param enable true to enable invalid MAC address filtering and false to disable it * * @retval IX_ETH_DB_SUCCESS operation completed successfully * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier diff --git a/drivers/net/npe/include/IxEthDB_p.h b/drivers/net/npe/include/IxEthDB_p.h index ccec7ea7b..d173d1208 100644 --- a/drivers/net/npe/include/IxEthDB_p.h +++ b/drivers/net/npe/include/IxEthDB_p.h @@ -169,9 +169,9 @@ extern int overflowEvent; #define TREE_POOL_SIZE (4000) /**< number of MacTreeNode objects; each entry has 16 bytes */ /* retry policies */ -#define BUSY_RETRY_ENABLED (TRUE) /**< if set to TRUE the API will retry automatically calls returning BUSY */ -#define FOREVER_RETRY (TRUE) /**< if set to TRUE the API will retry forever BUSY calls */ -#define MAX_RETRIES (400) /**< upper retry limit - used only when FOREVER_RETRY is FALSE */ +#define BUSY_RETRY_ENABLED (true) /**< if set to true the API will retry automatically calls returning BUSY */ +#define FOREVER_RETRY (true) /**< if set to true the API will retry forever BUSY calls */ +#define MAX_RETRIES (400) /**< upper retry limit - used only when FOREVER_RETRY is false */ #define BUSY_RETRY_YIELD (5) /**< ticks to yield for every failed retry */ /* event management */ @@ -179,8 +179,8 @@ extern int overflowEvent; #define EVENT_PROCESSING_LIMIT (100) /**< batch processing control size (how many events are extracted from the queue at once) */ /* MAC descriptors */ -#define STATIC_ENTRY (TRUE) -#define DYNAMIC_ENTRY (FALSE) +#define STATIC_ENTRY (true) +#define DYNAMIC_ENTRY (false) /* age reset on next maintenance - incrementing by 1 will reset to 0 */ #define AGE_RESET (0xFFFFFFFF) @@ -270,7 +270,7 @@ extern int overflowEvent; /* gives an empty dependency map */ #define SET_EMPTY_DEPENDENCY_MAP(map) { int i = 0; for (; i < 32 ; i++) map[i] = 0; } -#define IS_EMPTY_DEPENDENCY_MAP(result, map) { int i = 0 ; result = TRUE; for (; i < 32 ; i++) if (map[i] != 0) { result = FALSE; break; }} +#define IS_EMPTY_DEPENDENCY_MAP(result, map) { int i = 0 ; result = true; for (; i < 32 ; i++) if (map[i] != 0) { result = false; break; }} /** * gives a map consisting only of 'portID' @@ -293,12 +293,12 @@ extern int overflowEvent; #define EXCLUDE_PORT_FROM_MAP(map, portID) { map[portID >> 3] &= ~(1 << (portID & 0x7); } /** - * returns TRUE if map1 is a subset of map2 and FALSE otherwise + * returns true if map1 is a subset of map2 and false otherwise */ -#define IS_MAP_SUBSET(result, map1, map2) { int i = 0; result = TRUE; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = FALSE; } +#define IS_MAP_SUBSET(result, map1, map2) { int i = 0; result = true; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = false; } /** - * returns TRUE is portID is part of map and FALSE otherwise + * returns true is portID is part of map and false otherwise */ #define IS_PORT_INCLUDED(portID, map) ((map[portID >> 3] & (1 << (portID & 0x7))) != 0) @@ -308,9 +308,9 @@ extern int overflowEvent; #define DIFF_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] ^ (map1[i] & map2[i]); } /** - * returns TRUE if the maps collide (have at least one port in common) and FALSE otherwise + * returns true if the maps collide (have at least one port in common) and false otherwise */ -#define MAPS_COLLIDE(result, map1, map2) { int i = 0; result = FALSE; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = TRUE; } +#define MAPS_COLLIDE(result, map1, map2) { int i = 0; result = false; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = true; } /* size (number of ports) of a dependency map */ #define GET_MAP_SIZE(map, size) { int i = 0, b = 0; size = 0; for (; i < 32 ; i++) { char y = map[i]; for (; b < 8 && (y >>= 1); b++) size += (y & 1); }} @@ -415,7 +415,7 @@ typedef union struct { UINT32 age; - BOOL staticEntry; /**< TRUE if this address is static (doesn't age) */ + BOOL staticEntry; /**< true if this address is static (doesn't age) */ } filteringData; struct @@ -492,26 +492,26 @@ typedef void (*IxEthDBNoteWriteFn)(void *address, MacTreeNode *node); typedef struct { - BOOL updateEnabled; /**< TRUE if updates are enabled for port */ - BOOL userControlled; /**< TRUE if the user has manually used ixEthDBPortUpdateEnableSet */ - BOOL treeInitialized; /**< TRUE if the NPE has received an initial tree */ + BOOL updateEnabled; /**< true if updates are enabled for port */ + BOOL userControlled; /**< true if the user has manually used ixEthDBPortUpdateEnableSet */ + BOOL treeInitialized; /**< true if the NPE has received an initial tree */ IxEthDBPortUpdateHandler updateHandler; /**< port update handler routine */ void *npeUpdateZone; /**< port update memory zone */ void *npeGwUpdateZone; /**< port update memory zone for gateways */ void *vlanUpdateZone; /**< port update memory zone for VLAN tables */ MacTreeNode *searchTree; /**< internal search tree, in MacTreeNode representation */ - BOOL searchTreePendingWrite; /**< TRUE if searchTree holds a tree pending write to the port */ + BOOL searchTreePendingWrite; /**< true if searchTree holds a tree pending write to the port */ } PortUpdateMethod; typedef struct { IxEthDBPortId portID; /**< port ID */ - BOOL enabled; /**< TRUE if the port is enabled */ - BOOL agingEnabled; /**< TRUE if aging on this port is enabled */ + BOOL enabled; /**< true if the port is enabled */ + BOOL agingEnabled; /**< true if aging on this port is enabled */ BOOL initialized; IxEthDBPortMap dependencyPortMap; /**< dependency port map for this port */ PortUpdateMethod updateMethod; /**< update method structure */ - BOOL macAddressUploaded; /**< TRUE if the MAC address was uploaded into the port */ + BOOL macAddressUploaded; /**< true if the MAC address was uploaded into the port */ UINT32 maxRxFrameSize; /**< maximum Rx frame size for this port */ UINT32 maxTxFrameSize; /**< maximum Rx frame size for this port */ diff --git a/drivers/net/npe/include/IxEthMii.h b/drivers/net/npe/include/IxEthMii.h index 397253a94..93d3b790b 100644 --- a/drivers/net/npe/include/IxEthMii.h +++ b/drivers/net/npe/include/IxEthMii.h @@ -83,7 +83,7 @@ * * @brief Scan the MDIO bus for PHYs * This function scans PHY addresses 0 through 31, and sets phyPresent[n] to - * TRUE if a phy is discovered at address n. + * true if a phy is discovered at address n. * * - Reentrant - no * - ISR Callable - no @@ -120,9 +120,9 @@ PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount); * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. * * @param phyAddr UINT32 [in] - * @param speed100 BOOL [in] - set to TRUE for 100Mbit/s operation, FALSE for 10Mbit/s - * @param fullDuplex BOOL [in] - set to TRUE for Full Duplex, FALSE for Half Duplex - * @param autonegotiate BOOL [in] - set to TRUE to enable autonegotiation + * @param speed100 BOOL [in] - set to true for 100Mbit/s operation, false for 10Mbit/s + * @param fullDuplex BOOL [in] - set to true for Full Duplex, false for Half Duplex + * @param autonegotiate BOOL [in] - set to true to enable autonegotiation * * @return IX_STATUS * - IX_SUCCESS @@ -223,10 +223,10 @@ PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr); * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. * * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * @param linkUp BOOL [out] - set to TRUE if the link is up - * @param speed100 BOOL [out] - set to TRUE indicates 100Mbit/s, FALSE indicates 10Mbit/s - * @param fullDuplex BOOL [out] - set to TRUE indicates Full Duplex, FALSE indicates Half Duplex - * @param autoneg BOOL [out] - set to TRUE indicates autonegotiation is enabled, FALSE indicates autonegotiation is disabled + * @param linkUp BOOL [out] - set to true if the link is up + * @param speed100 BOOL [out] - set to true indicates 100Mbit/s, false indicates 10Mbit/s + * @param fullDuplex BOOL [out] - set to true indicates Full Duplex, false indicates Half Duplex + * @param autoneg BOOL [out] - set to true indicates autonegotiation is enabled, false indicates autonegotiation is disabled * * @return IX_STATUS * - IX_SUCCESS diff --git a/drivers/net/npe/include/IxFeatureCtrl.h b/drivers/net/npe/include/IxFeatureCtrl.h index dabc38e25..1662a0013 100644 --- a/drivers/net/npe/include/IxFeatureCtrl.h +++ b/drivers/net/npe/include/IxFeatureCtrl.h @@ -706,14 +706,14 @@ ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType); * @brief This function enable/disable the specified software configuration. * * Usage Example:<br> - * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, TRUE) is used + * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, true) is used * to enable Ethernet Learning Feature <br> - * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, FALSE) is used + * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false) is used * to disable Ethernet Learning Feature <br> * * @param swConfigType IxFeatureCtrlSwConfig [in] - the type of a software configuration * defined in IxFeatureCtrlSwConfig enumeration. - * @param enabled BOOL [in] - To enable(TRUE) / disable (FALSE) the specified software + * @param enabled BOOL [in] - To enable(true) / disable (false) the specified software * configuration. * * @return none diff --git a/drivers/net/npe/include/IxHssAcc.h b/drivers/net/npe/include/IxHssAcc.h index 07bb119b0..52d5716f7 100644 --- a/drivers/net/npe/include/IxHssAcc.h +++ b/drivers/net/npe/include/IxHssAcc.h @@ -583,12 +583,12 @@ typedef struct */ typedef struct { - BOOL hdlc56kMode; /**< 56kbps(TRUE)/64kbps(FALSE) HDLC */ + BOOL hdlc56kMode; /**< 56kbps(true)/64kbps(false) HDLC */ IxHssAcc56kEndianness hdlc56kEndian; /**< 56kbps data endianness - - ignored if hdlc56kMode is FALSE*/ - BOOL hdlc56kUnusedBitPolarity0; /**< The polarity '0'(TRUE)/'1'(FALSE) of the unused + - ignored if hdlc56kMode is false*/ + BOOL hdlc56kUnusedBitPolarity0; /**< The polarity '0'(true)/'1'(false) of the unused bit while in 56kbps mode - - ignored if hdlc56kMode is FALSE*/ + - ignored if hdlc56kMode is false*/ } IxHssAccHdlcMode; /** @@ -1006,9 +1006,9 @@ ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId, * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 * * @return - * - TRUE The state of this HSS/HDLC port combination is disconnected, + * - true The state of this HSS/HDLC port combination is disconnected, * so if a disconnect was called, it is now completed. - * - FALSE The state of this HSS/HDLC port combination is connected, + * - false The state of this HSS/HDLC port combination is connected, * so if a disconnect was called, it is not yet completed. */ PUBLIC BOOL @@ -1259,7 +1259,7 @@ ixHssAccChanDisconnect (IxHssAccHssPort hssPortId); * identical ports (0-1). * @param *dataRecvd BOOL [out] - This BOOL indicates to the client whether * or not the access component has read any data for the client. If - * FALSE, the other output parameters will not have been written to. + * false, the other output parameters will not have been written to. * @param *rxOffset unsigned [out] - An offset to indicate to the client * where within the receive buffers the NPE has just written the received * data to. diff --git a/drivers/net/npe/include/IxNpeDl.h b/drivers/net/npe/include/IxNpeDl.h index 86f69f414..f514c2e7d 100644 --- a/drivers/net/npe/include/IxNpeDl.h +++ b/drivers/net/npe/include/IxNpeDl.h @@ -637,7 +637,7 @@ ixNpeDlMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary); * @param imageIdPtr @ref IxNpeDlImageId* [in] - Pointer to Id of the microcode * image to download. * @param verify BOOL [in] - ON/OFF option to verify the download. If ON - * (verify == TRUE), the Downloader will read back + * (verify == true), the Downloader will read back * each word written to the NPE registers to * ensure the download operation was successful. * diff --git a/drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h b/drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h index a752f26e8..876a438ce 100644 --- a/drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h +++ b/drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h @@ -81,7 +81,7 @@ * @param UINT32 [in] npeBaseAddress - Base Address of NPE * @param UINT32 [in] insMemAddress - NPE instruction memory address to write * @param UINT32 [in] insMemData - data to write to instruction memory - * @param BOOL [in] verify - if TRUE, verify the memory location is + * @param BOOL [in] verify - if true, verify the memory location is * written successfully. * * This function is used to write a single word of data to a location in NPE @@ -93,7 +93,7 @@ * @post * * @return - * - IX_FAIL if verify is TRUE and the memory location was not written + * - IX_FAIL if verify is true and the memory location was not written * successfully * - IX_SUCCESS otherwise */ @@ -113,7 +113,7 @@ ixNpeDlNpeMgrInsMemWrite (UINT32 npeBaseAddress, UINT32 insMemAddress, * @param UINT32 [in] npeBaseAddress - Base Address of NPE * @param UINT32 [in] dataMemAddress - NPE data memory address to write * @param UINT32 [in] dataMemData - data to write to NPE data memory - * @param BOOL [in] verify - if TRUE, verify the memory location is + * @param BOOL [in] verify - if true, verify the memory location is * written successfully. * * This function is used to write a single word of data to a location in NPE @@ -125,7 +125,7 @@ ixNpeDlNpeMgrInsMemWrite (UINT32 npeBaseAddress, UINT32 insMemAddress, * @post * * @return - * - IX_FAIL if verify is TRUE and the memory location was not written + * - IX_FAIL if verify is true and the memory location was not written * successfully * - IX_SUCCESS otherwise */ @@ -304,7 +304,7 @@ ixNpeDlNpeMgrDebugInstructionPostExec (UINT32 npeBaseAddress); * @param UINT32 [in] npeBaseAddress - Base Address of NPE * @param UINT32 [in] regAddr - number of the physical register (0-31)* * @param UINT32 [in] regValue - value to write to the physical register - * @param BOOL [in] verify - if TRUE, verify the register is written + * @param BOOL [in] verify - if true, verify the register is written * successfully. * * This function writes a physical register in the NPE data register file. @@ -324,7 +324,7 @@ ixNpeDlNpeMgrDebugInstructionPostExec (UINT32 npeBaseAddress); * a sequence of calls to this function * * @return - * - IX_FAIL if verify is TRUE and the Context Register was not written + * - IX_FAIL if verify is true and the Context Register was not written * successfully * - IX_SUCCESS if Context Register was written successfully * - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written @@ -349,7 +349,7 @@ ixNpeDlNpeMgrPhysicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr, * @param IxNpeDlCtxtRegNum [in] ctxtReg - which Context Store reg to write * @param UINT32 [in] ctxtRegVal - value to write to the Context Store * register - * @param BOOL [in] verify - if TRUE, verify the register is + * @param BOOL [in] verify - if true, verify the register is * written successfully. * * This function writes the contents of a Context Store register in the NPE @@ -366,7 +366,7 @@ ixNpeDlNpeMgrPhysicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr, * a sequence of calls to this function * * @return - * - IX_FAIL if verify is TRUE and the Context Register was not written + * - IX_FAIL if verify is true and the Context Register was not written * successfully * - IX_SUCCESS if Context Register was written successfully * - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written diff --git a/drivers/net/npe/include/IxNpeDlNpeMgr_p.h b/drivers/net/npe/include/IxNpeDlNpeMgr_p.h index b7fb0f021..e25e532b1 100644 --- a/drivers/net/npe/include/IxNpeDlNpeMgr_p.h +++ b/drivers/net/npe/include/IxNpeDlNpeMgr_p.h @@ -126,7 +126,7 @@ IX_STATUS ixNpeDlNpeMgrUninit (void); * @param IxNpeDlNpeId [in] npeId - Id of target NPE * @param UINT32* [in] imageCodePtr - pointer to image code in image to be * downloaded - * @param BOOL [in] verify - if TRUE, verify each word written to + * @param BOOL [in] verify - if true, verify each word written to * NPE memory. * * This function loads a image containing blocks of microcode onto a diff --git a/drivers/net/npe/include/IxNpeMhConfig_p.h b/drivers/net/npe/include/IxNpeMhConfig_p.h index 375b3468e..8c8b9ab7f 100644 --- a/drivers/net/npe/include/IxNpeMhConfig_p.h +++ b/drivers/net/npe/include/IxNpeMhConfig_p.h @@ -110,7 +110,7 @@ typedef struct UINT32 inFifoRegister; /**< inFIFO register virutal address */ UINT32 outFifoRegister; /**< outFIFO register virtual address */ IxNpeMhConfigIsr isr; /**< isr routine for handling interrupt */ - BOOL oldInterruptState; /**< old interrupt state (TRUE => enabled) */ + BOOL oldInterruptState; /**< old interrupt state (true => enabled) */ } IxNpeMhConfigNpeInfo; @@ -250,7 +250,7 @@ void ixNpeMhConfigIsrRegister ( * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will * be enabled. * - * @return Returns the previous state of the interrupt (TRUE => enabled). + * @return Returns the previous state of the interrupt (true => enabled). */ BOOL ixNpeMhConfigNpeInterruptEnable ( @@ -265,7 +265,7 @@ BOOL ixNpeMhConfigNpeInterruptEnable ( * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will * be disabled. * - * @return Returns the previous state of the interrupt (TRUE => enabled). + * @return Returns the previous state of the interrupt (true => enabled). */ BOOL ixNpeMhConfigNpeInterruptDisable ( @@ -293,7 +293,7 @@ IxNpeMhMessageId ixNpeMhConfigMessageIdGet ( * * @param IxNpeMhNpeId npeId (in) - the NPE ID to validate. * - * @return True if the NPE ID is valid, otherwise False. + * @return true if the NPE ID is valid, otherwise false. */ BOOL ixNpeMhConfigNpeIdIsValid ( @@ -340,7 +340,7 @@ void ixNpeMhConfigLockRelease ( * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO * will be checked. * - * @return True if the inFIFO is empty, otherwise False. + * @return true if the inFIFO is empty, otherwise false. */ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsEmpty ( @@ -355,7 +355,7 @@ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsEmpty ( * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO * will be checked. * - * @return True if the inFIFO is full, otherwise False. + * @return true if the inFIFO is full, otherwise false. */ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsFull ( @@ -370,7 +370,7 @@ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsFull ( * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO * will be checked. * - * @return True if the outFIFO is empty, otherwise False. + * @return true if the outFIFO is empty, otherwise false. */ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsEmpty ( @@ -385,7 +385,7 @@ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsEmpty ( * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO * will be checked. * - * @return True if the outFIFO is full, otherwise False. + * @return true if the outFIFO is full, otherwise false. */ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsFull ( diff --git a/drivers/net/npe/include/IxOsal.h b/drivers/net/npe/include/IxOsal.h index 4ca2e45f6..28c44af32 100644 --- a/drivers/net/npe/include/IxOsal.h +++ b/drivers/net/npe/include/IxOsal.h @@ -1204,8 +1204,8 @@ PUBLIC void ixOsalTicksToTimeval (UINT32 ticks, IxOsalTimeval * pTv); * @li Reentrant: yes * @li IRQ safe: yes * - * @return - TRUE if the structures are equal - * - FALSE otherwise + * @return - true if the structures are equal + * - false otherwise * Note: This function is OS-independant */ #define IX_OSAL_TIME_EQ(tvA, tvB) \ @@ -1225,8 +1225,8 @@ PUBLIC void ixOsalTicksToTimeval (UINT32 ticks, IxOsalTimeval * pTv); * @li Reentrant: yes * @li IRQ safe: yes * - * @return - TRUE if tvA < tvB - * - FALSE otherwise + * @return - true if tvA < tvB + * - false otherwise * Note: This function is OS-independent. Implemented by core. */ #define IX_OSAL_TIME_LT(tvA,tvB) \ @@ -1247,8 +1247,8 @@ PUBLIC void ixOsalTicksToTimeval (UINT32 ticks, IxOsalTimeval * pTv); * @li Reentrant: yes * @li IRQ safe: yes * - * @return - TRUE if tvA > tvB - * - FALSE otherwise + * @return - true if tvA > tvB + * - false otherwise * Note: This function is OS-independent. */ #define IX_OSAL_TIME_GT(tvA, tvB) \ diff --git a/drivers/net/npe/include/IxOsalTypes.h b/drivers/net/npe/include/IxOsalTypes.h index a190a707e..06e71debf 100644 --- a/drivers/net/npe/include/IxOsalTypes.h +++ b/drivers/net/npe/include/IxOsalTypes.h @@ -107,22 +107,6 @@ typedef volatile INT32 VINT32; */ #define IX_OSAL_BILLION (1000000000) -#ifndef TRUE -#define TRUE 1L -#endif - -#if TRUE != 1 -#error TRUE is not defined to 1 -#endif - -#ifndef FALSE -#define FALSE 0L -#endif - -#if FALSE != 0 -#error FALSE is not defined to 0 -#endif - #ifndef NULL #define NULL 0L #endif diff --git a/drivers/net/npe/include/IxPerfProfAcc.h b/drivers/net/npe/include/IxPerfProfAcc.h index 65c0ba96a..7e4527a05 100644 --- a/drivers/net/npe/include/IxPerfProfAcc.h +++ b/drivers/net/npe/include/IxPerfProfAcc.h @@ -1281,8 +1281,8 @@ ixPerfProfAccXcycleResultsGet ( * Check if Xcycle measuring task is running. * * @return - * - TRUE - Xcycle is running - * - FALSE - Xcycle is not running + * - true - Xcycle is running + * - false - Xcycle is not running * * @li Reentrant : no * @li ISR Callable : no diff --git a/drivers/net/npe/include/IxQMgrAqmIf_p.h b/drivers/net/npe/include/IxQMgrAqmIf_p.h index 4f0f64d27..b63c4a9ef 100644 --- a/drivers/net/npe/include/IxQMgrAqmIf_p.h +++ b/drivers/net/npe/include/IxQMgrAqmIf_p.h @@ -606,10 +606,10 @@ ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords, (newQStatusWords[statusWordOffset] & mask)) && ((newQStatusWords[statusWordOffset] & mask) == checkValue)) { - return TRUE; + return true; } - return FALSE; + return false; } /* @@ -665,7 +665,7 @@ ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group, /* * This inline function will read the status bit of a queue - * specified by qId. If reset is TRUE the bit is cleared. + * specified by qId. If reset is true the bit is cleared. */ IX_QMGR_AQMIF_INLINE BOOL ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, @@ -707,11 +707,11 @@ ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, { ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset)); } - return TRUE; + return true; } /* Bit not set */ - return FALSE; + return false; } @@ -733,12 +733,12 @@ ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId) IX_QMGR_QUEUOSTAT0_OFFSET, IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD, IX_QMGR_UNDERFLOW_BIT_OFFSET, - TRUE/*reset*/)); + true/*reset*/)); } else { /* Qs 32-63 have no underflow status */ - return FALSE; + return false; } } @@ -755,12 +755,12 @@ ixQMgrAqmIfOverflowCheck (IxQMgrQId qId) IX_QMGR_QUEUOSTAT0_OFFSET, IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD, IX_QMGR_OVERFLOW_BIT_OFFSET, - TRUE/*reset*/)); + true/*reset*/)); } else { /* Qs 32-63 have no overflow status */ - return FALSE; + return false; } } @@ -870,7 +870,7 @@ ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId, IX_QMGR_QUEUPPSTAT0_OFFSET, IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD, 0/*relativeBitOffset*/, - FALSE/*!reset*/)) + false/*!reset*/)) { *status |= IX_QMGR_Q_STATUS_NE_BIT_MASK; } @@ -884,7 +884,7 @@ ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId, IX_QMGR_QUEUPPSTAT1_OFFSET, IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD, 0/*relativeBitOffset*/, - FALSE/*!reset*/)) + false/*!reset*/)) { *status |= IX_QMGR_Q_STATUS_F_BIT_MASK; } diff --git a/drivers/net/npe/include/IxSspAcc.h b/drivers/net/npe/include/IxSspAcc.h index 35e7abf06..61d911b9a 100644 --- a/drivers/net/npe/include/IxSspAcc.h +++ b/drivers/net/npe/include/IxSspAcc.h @@ -898,7 +898,7 @@ ixSspAccTxFIFOIntDisable ( * * @brief Enables/disables the loopback mode * - * @param "BOOL [in] loopbackEnable" - True to enable and false to disable. + * @param "BOOL [in] loopbackEnable" - true to enable and false to disable. * * Global Data : * - None. diff --git a/drivers/net/npe/include/IxTimeSyncAcc.h b/drivers/net/npe/include/IxTimeSyncAcc.h index 25effed90..52c4c1cfa 100644 --- a/drivers/net/npe/include/IxTimeSyncAcc.h +++ b/drivers/net/npe/include/IxTimeSyncAcc.h @@ -497,8 +497,8 @@ ixTimeSyncAccTargetTimeInterruptDisable(void); * the Target Time in the IEEE 1588 hardware assist block. If the condition is * true an event flag is set in the hardware. * - * @param ttmPollFlag [out] - TRUE if the target time reached/hit condition event set - * FALSE if the target time reached/hit condition event is + * @param ttmPollFlag [out] - true if the target time reached/hit condition event set + * false if the target time reached/hit condition event is not set * @param targetTime [out] - Capture current targetTime into client provided buffer * @@ -656,9 +656,9 @@ ixTimeSyncAccAuxTimeInterruptDisable(IxTimeSyncAccAuxMode auxMode); * (Master or Slave) * * @param auxMode [in] - Auxiliary Snapshot Register (Slave or Master) to be checked - * @param auxPollFlag [out] - TRUE if the time stamp captured in auxiliary + * @param auxPollFlag [out] - true if the time stamp captured in auxiliary snapshot register - * FALSE if the time stamp not captured in + * false if the time stamp not captured in auxiliary snapshot register * @param auxTime [out] - Copy the current Auxiliary Snapshot Register value into the * client provided buffer diff --git a/drivers/net/npe/npe.c b/drivers/net/npe/npe.c index 1fe3a95ea..6fc9f86e5 100644 --- a/drivers/net/npe/npe.c +++ b/drivers/net/npe/npe.c @@ -322,7 +322,7 @@ static int npe_csr_load(void) } /* don't need this for U-Boot */ - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, FALSE); + ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false); if (ixEthAccInit() != IX_ETH_ACC_SUCCESS) { printf("Error initialising Ethernet access driver!\n"); @@ -647,29 +647,29 @@ int npe_initialize(bd_t * bis) */ if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_1] = TRUE; + npe_exists[IX_ETH_PORT_1] = true; if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_2] = TRUE; + npe_exists[IX_ETH_PORT_2] = true; break; case IX_FEATURE_CTRL_SILICON_TYPE_A0: /* * If it is A0 Silicon, we enable both as both Eth Coprocessors * are available. */ - npe_exists[IX_ETH_PORT_1] = TRUE; - npe_exists[IX_ETH_PORT_2] = TRUE; + npe_exists[IX_ETH_PORT_1] = true; + npe_exists[IX_ETH_PORT_2] = true; break; } } else if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X) { if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_1] = TRUE; + npe_exists[IX_ETH_PORT_1] = true; if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_2] = TRUE; + npe_exists[IX_ETH_PORT_2] = true; } npe_used[IX_ETH_PORT_1] = 1; diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c index d61a2289f..ec04ec895 100644 --- a/drivers/rtc/ds1374.c +++ b/drivers/rtc/ds1374.c @@ -84,15 +84,6 @@ #define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */ #define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */ -typedef unsigned char boolean_t; - -#ifndef TRUE -#define TRUE ((boolean_t)(0==0)) -#endif -#ifndef FALSE -#define FALSE (!TRUE) -#endif - const char RtcTodAddr[] = { RTC_TOD_CNT_BYTE0_ADDR, RTC_TOD_CNT_BYTE1_ADDR, @@ -101,7 +92,7 @@ const char RtcTodAddr[] = { }; static uchar rtc_read (uchar reg); -static void rtc_write (uchar reg, uchar val, boolean_t set); +static void rtc_write(uchar reg, uchar val, bool set); static void rtc_write_raw (uchar reg, uchar val); /* @@ -185,7 +176,7 @@ int rtc_set (struct rtc_time *tmp){ } /* Start clock */ - rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, FALSE); + rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, false); return 0; } @@ -202,18 +193,18 @@ void rtc_reset (void){ struct rtc_time tmp; /* clear status flags */ - rtc_write (RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), FALSE); /* clearing OSF and AF */ + rtc_write(RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), false); /* clearing OSF and AF */ /* Initialise DS1374 oriented to MPC8349E-ADS */ rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC |RTC_CTL_BIT_WACE - |RTC_CTL_BIT_AIE), FALSE);/* start osc, disable WACE, clear AIE + |RTC_CTL_BIT_AIE), false);/* start osc, disable WACE, clear AIE - set to 0 */ rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM |RTC_CTL_BIT_WDSTR |RTC_CTL_BIT_RS1 |RTC_CTL_BIT_RS2 - |RTC_CTL_BIT_BBSQW), TRUE);/* disable WD/ALM, WDSTR set to INT-pin, + |RTC_CTL_BIT_BBSQW), true);/* disable WD/ALM, WDSTR set to INT-pin, set BBSQW and SQW to 32k - set to 1 */ tmp.tm_year = 1970; @@ -229,9 +220,9 @@ void rtc_reset (void){ tmp.tm_year, tmp.tm_mon, tmp.tm_mday, tmp.tm_hour, tmp.tm_min, tmp.tm_sec); - rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAC, TRUE); - rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR,0xDE, TRUE); - rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAD, TRUE); + rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAC, true); + rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR, 0xDE, true); + rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAD, true); } /* @@ -242,9 +233,9 @@ static uchar rtc_read (uchar reg) return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); } -static void rtc_write (uchar reg, uchar val, boolean_t set) +static void rtc_write(uchar reg, uchar val, bool set) { - if (set == TRUE) { + if (set == true) { val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg); i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } else { diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c index 148d1a6dd..8e0815334 100644 --- a/drivers/serial/usbtty.c +++ b/drivers/serial/usbtty.c @@ -971,8 +971,8 @@ static void usbtty_event_handler (struct usb_device_instance *device, /* * is_usbd_high_speed routine needs to be defined by * specific gadget driver - * It returns TRUE if device enumerates at High speed - * Retuns FALSE otherwise + * It returns true if device enumerates at High speed + * Retuns false otherwise */ for (i = 0; i < NUM_ENDPOINTS; i++) { if (((ep_descriptor_ptrs[i]->bmAttributes & diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 8865df5be..468d356a8 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -455,7 +455,7 @@ static int spi_setup_offset(struct spi_trans *trans) /* * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write + * below is true) or 0. In case the wait was for the bit(s) to set - write * those bits back, which would cause resetting them. * * Return the last read status value on success or -1 on failure. diff --git a/drivers/usb/musb-new/linux-compat.h b/drivers/usb/musb-new/linux-compat.h index 5c126ef9c..72c8c2bad 100644 --- a/drivers/usb/musb-new/linux-compat.h +++ b/drivers/usb/musb-new/linux-compat.h @@ -12,8 +12,6 @@ #define __iomem #define __deprecated -typedef enum { false = 0, true = 1 } bool; - struct unused {}; typedef struct unused unused_t; diff --git a/drivers/video/Makefile b/drivers/video/Makefile index e8cecca55..53952ab07 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -35,11 +35,12 @@ COBJS-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ exynos_mipi_dsi_lowlevel.o COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o +COBJS-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o +COBJS-$(CONFIG_PXA_LCD) += pxa_lcd.o COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o COBJS-$(CONFIG_S6E63D6) += s6e63d6.o COBJS-$(CONFIG_LD9040) += ld9040.o COBJS-$(CONFIG_SED156X) += sed156x.o -COBJS-$(CONFIG_VIDEO_AMBA) += amba.o COBJS-$(CONFIG_VIDEO_BCM2835) += bcm2835.o COBJS-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o diff --git a/drivers/video/amba.c b/drivers/video/amba.c deleted file mode 100644 index ffa1c399e..000000000 --- a/drivers/video/amba.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Driver for AMBA PrimeCell CLCD - * - * Copyright (C) 2009 Alessandro Rubini - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <lcd.h> -#include <amba_clcd.h> - -/* These variables are required by lcd.c -- although it sets them by itself */ -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; -void *lcd_base; -void *lcd_console_address; -short console_col; -short console_row; - -/* - * To use this driver you need to provide the following in board files: - * a panel_info definition - * an lcd_enable function (can't define a weak default with current code) - */ - -/* There is nothing to do with color registers, we use true color */ -void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) -{ - return; -} - -/* Low level initialization of the logic cell: depends on panel_info */ -void lcd_ctrl_init(void *lcdbase) -{ - struct clcd_config *config; - struct clcd_registers *regs; - u32 cntl; - - config = panel_info.priv; - regs = config->address; - cntl = config->cntl & ~CNTL_LCDEN; - - /* Lazily, just copy the registers over: first control with disable */ - writel(cntl, ®s->cntl); - - writel(config->tim0, ®s->tim0); - writel(config->tim1, ®s->tim1); - writel(config->tim2, ®s->tim2); - writel(config->tim3, ®s->tim3); - writel((u32)lcdbase, ®s->ubas); - /* finally, enable */ - writel(cntl | CNTL_LCDEN, ®s->cntl); -} - -/* This is trivial, and copied from atmel_lcdfb.c */ -ulong calc_fbsize(void) -{ - return ((panel_info.vl_col * panel_info.vl_row * - NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; -} diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index b10ca4b67..fc9589774 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -29,16 +29,6 @@ #include <lcd.h> #include <atmel_hlcdc.h> -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; - -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - /* configurable parameters */ #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 #define ATMEL_LCDC_DMA_BURST_LEN 8 diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index c02ffd803..2afeab2ff 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -29,16 +29,6 @@ #include <lcd.h> #include <atmel_lcdc.h> -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; - -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - /* configurable parameters */ #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 #define ATMEL_LCDC_DMA_BURST_LEN 8 diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index 1e9a84ac1..0c77d17b4 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -23,17 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Global variables that lcd.c expects to exist */ -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; -void *lcd_base; -void *lcd_console_address; -short console_col; -short console_row; vidinfo_t panel_info; -char lcd_cursor_enabled; -ushort lcd_cursor_width; -ushort lcd_cursor_height; struct msg_query { struct bcm2835_mbox_hdr hdr; @@ -119,7 +109,6 @@ void lcd_ctrl_init(void *lcdbase) panel_info.vl_bpix = LCD_COLOR16; gd->fb_base = msg_setup->allocate_buffer.body.resp.fb_address; - lcd_base = (void *)gd->fb_base; } void lcd_enable(void) diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 26f673a96..61e1058ad 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1515,13 +1515,6 @@ int video_display_bitmap(ulong bmp_image, int x, int y) padded_line = (((width * bpp + 7) / 8) + 3) & ~0x3; - /* - * Just ignore elements which are completely beyond screen - * dimensions. - */ - if ((x >= VIDEO_VISIBLE_COLS) || (y >= VIDEO_VISIBLE_ROWS)) - return 0; - #ifdef CONFIG_SPLASH_SCREEN_ALIGN if (x == BMP_ALIGN_CENTER) x = max(0, (VIDEO_VISIBLE_COLS - width) / 2); @@ -1534,6 +1527,13 @@ int video_display_bitmap(ulong bmp_image, int x, int y) y = max(0, VIDEO_VISIBLE_ROWS - height + y + 1); #endif /* CONFIG_SPLASH_SCREEN_ALIGN */ + /* + * Just ignore elements which are completely beyond screen + * dimensions. + */ + if ((x >= VIDEO_VISIBLE_COLS) || (y >= VIDEO_VISIBLE_ROWS)) + return 0; + if ((x + width) > VIDEO_VISIBLE_COLS) width = VIDEO_VISIBLE_COLS - x; if ((y + height) > VIDEO_VISIBLE_ROWS) diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index dfe329fbc..ed0823bf9 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -38,16 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; - -void *lcd_base; -void *lcd_console_address; - -short console_col; -short console_row; - static unsigned int panel_width, panel_height; /* @@ -71,11 +61,9 @@ static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid) fb_size = vid->vl_row * vid->vl_col * (NBITS(vid->vl_bpix) >> 3); - lcd_base = lcdbase; - palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16; - exynos_fimd_lcd_init_mem((unsigned long)lcd_base, + exynos_fimd_lcd_init_mem((unsigned long)lcdbase, (unsigned long)fb_size, palette_size); } @@ -346,7 +334,7 @@ void lcd_ctrl_init(void *lcdbase) void lcd_enable(void) { if (panel_info.logo_on) { - memset(lcd_base, 0, panel_width * panel_height * + memset((void *) gd->fb_base, 0, panel_width * panel_height * (NBITS(panel_info.vl_bpix) >> 3)); #ifdef CONFIG_CMD_BMP draw_logo(); diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c new file mode 100644 index 000000000..f0f728e22 --- /dev/null +++ b/drivers/video/mpc8xx_lcd.c @@ -0,0 +1,564 @@ +/* + * (C) Copyright 2001-2002 + * Wolfgang Denk, DENX Software Engineering -- wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************/ +/* ** HEADER FILES */ +/************************************************************************/ + +/* #define DEBUG */ + +#include <config.h> +#include <common.h> +#include <command.h> +#include <watchdog.h> +#include <version.h> +#include <stdarg.h> +#include <lcdvideo.h> +#include <linux/types.h> +#include <stdio_dev.h> +#if defined(CONFIG_POST) +#include <post.h> +#endif +#include <lcd.h> + +#ifdef CONFIG_LCD + +/************************************************************************/ +/* ** CONFIG STUFF -- should be moved to board config file */ +/************************************************************************/ +#ifndef CONFIG_LCD_INFO +#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */ +#endif + +#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10) +#undef CONFIG_LCD_LOGO +#undef CONFIG_LCD_INFO +#endif + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_KYOCERA_KCS057QV1AJ +/* + * Kyocera KCS057QV1AJ-G23. Passive, color, single scan. + */ +#define LCD_BPP LCD_COLOR4 + +vidinfo_t panel_info = { + 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, + LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_KYOCERA_KCS057QV1AJ */ +/*----------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_HITACHI_SP19X001_Z1A +/* + * Hitachi SP19X001-. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, + LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_HITACHI_SP19X001_Z1A */ +/*----------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_NEC_NL6448AC33 +/* + * NEC NL6448AC33-18. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 144, 2, 0, 33 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_NEC_NL6448AC33 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_NEC_NL6448BC20 +/* + * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 144, 2, 0, 33 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_NEC_NL6448BC20 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_NEC_NL6448BC33_54 +/* + * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 144, 2, 0, 33 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_NEC_NL6448BC33_54 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_SHARP_LQ104V7DS01 +/* + * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, + 3, 0, 0, 1, 1, 25, 1, 0, 33 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_SHARP_LQ104V7DS01 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_SHARP_16x9 +/* + * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am + * not sure what it is....... + */ +vidinfo_t panel_info = { + 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 15, 4, 0, 3 +}; +#endif /* CONFIG_SHARP_16x9 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_SHARP_LQ057Q3DC02 +/* + * Sharp LQ057Q3DC02 display. Active, color, single scan. + */ +#undef LCD_DF +#define LCD_DF 12 + +vidinfo_t panel_info = { + 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 15, 4, 0, 3 + /* wbl, vpw, lcdac, wbf */ +}; +#define CONFIG_LCD_INFO_BELOW_LOGO +#endif /* CONFIG_SHARP_LQ057Q3DC02 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_SHARP_LQ64D341 +/* + * Sharp LQ64D341 display, 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 128, 16, 0, 32 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_SHARP_LQ64D341 */ + +#ifdef CONFIG_SHARP_LQ065T9DR51U +/* + * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan. + */ +vidinfo_t panel_info = { + 400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 248, 4, 0, 35 + /* wbl, vpw, lcdac, wbf */ +}; +#define CONFIG_LCD_INFO_BELOW_LOGO +#endif /* CONFIG_SHARP_LQ065T9DR51U */ + +#ifdef CONFIG_SHARP_LQ084V1DG21 +/* + * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, + 3, 0, 0, 1, 1, 160, 3, 0, 48 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_SHARP_LQ084V1DG21 */ + +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_HLD1045 +/* + * HLD1045 display, 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 160, 3, 0, 48 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_HLD1045 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_PRIMEVIEW_V16C6448AC +/* + * Prime View V16C6448AC + */ +vidinfo_t panel_info = { + 640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 144, 2, 0, 35 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_PRIMEVIEW_V16C6448AC */ + +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_OPTREX_BW +/* + * Optrex CBL50840-2 NF-FW 99 22 M5 + * or + * Hitachi LMG6912RPFC-00T + * or + * Hitachi SP14Q002 + * + * 320x240. Black & white. + */ +#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */ + /* 1 - 4 grey levels, 2 bpp */ + /* 2 - 16 grey levels, 4 bpp */ +vidinfo_t panel_info = { + 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, + OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4 +}; +#endif /* CONFIG_OPTREX_BW */ + +/*-----------------------------------------------------------------*/ +#ifdef CONFIG_EDT32F10 +/* + * Emerging Display Technologies 320x240. Passive, monochrome, single scan. + */ +#define LCD_BPP LCD_MONOCHROME +#define LCD_DF 10 + +vidinfo_t panel_info = { + 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, + LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0 +}; +#endif + +/************************************************************************/ +/* ----------------- chipset specific functions ----------------------- */ +/************************************************************************/ + +/* + * Calculate fb size for VIDEOLFB_ATAG. + */ +ulong calc_fbsize (void) +{ + ulong size; + int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; + + size = line_length * panel_info.vl_row; + + return size; +} + +void lcd_ctrl_init (void *lcdbase) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile lcd823_t *lcdp = &immr->im_lcd; + + uint lccrtmp; + uint lchcr_hpc_tmp; + + /* Initialize the LCD control register according to the LCD + * parameters defined. We do everything here but enable + * the controller. + */ + +#ifdef CONFIG_RPXLITE + /* This is special for RPXlite_DW Software Development Platform **[Sam]** */ + panel_info.vl_dp = CONFIG_SYS_LOW; +#endif + + lccrtmp = LCDBIT (LCCR_BNUM_BIT, + (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128)); + + lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) | + LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) | + LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) | + LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) | + LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) | + LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) | + LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) | + LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) | + LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) | + LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft); + +#if 0 + lccrtmp |= ((SIU_LEVEL5 / 2) << 12); + lccrtmp |= LCCR_EIEN; +#endif + + lcdp->lcd_lccr = lccrtmp; + lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */ + + /* Initialize LCD controller bus priorities. + */ +#ifdef CONFIG_RBC823 + immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */ +#else + immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */ + + /* set SHFT/CLOCK division factor 4 + * This needs to be set based upon display type and processor + * speed. The TFT displays run about 20 to 30 MHz. + * I was running 64 MHz processor speed. + * The value for this divider must be chosen so the result is + * an integer of the processor speed (i.e., divide by 3 with + * 64 MHz would be bad). + */ + immr->im_clkrst.car_sccr &= ~0x1F; + immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */ + +#endif /* CONFIG_RBC823 */ + +#if defined(CONFIG_RBC823) + /* Enable LCD on port D. + */ + immr->im_ioport.iop_pddat &= 0x0300; + immr->im_ioport.iop_pdpar |= 0x1CFF; + immr->im_ioport.iop_pddir |= 0x1CFF; + + /* Configure LCD_ON, VEE_ON, CCFL_ON on port B. + */ + immr->im_cpm.cp_pbdat &= ~0x00005001; + immr->im_cpm.cp_pbpar &= ~0x00005001; + immr->im_cpm.cp_pbdir |= 0x00005001; +#elif !defined(CONFIG_EDT32F10) + /* Enable LCD on port D. + */ + immr->im_ioport.iop_pdpar |= 0x1FFF; + immr->im_ioport.iop_pddir |= 0x1FFF; + + /* Enable LCD_A/B/C on port B. + */ + immr->im_cpm.cp_pbpar |= 0x00005001; + immr->im_cpm.cp_pbdir |= 0x00005001; +#else + /* Enable LCD on port D. + */ + immr->im_ioport.iop_pdpar |= 0x1DFF; + immr->im_ioport.iop_pdpar &= ~0x0200; + immr->im_ioport.iop_pddir |= 0x1FFF; + immr->im_ioport.iop_pddat |= 0x0200; +#endif + + /* Load the physical address of the linear frame buffer + * into the LCD controller. + * BIG NOTE: This has to be modified to load A and B depending + * upon the split mode of the LCD. + */ + lcdp->lcd_lcfaa = (ulong)lcdbase; + lcdp->lcd_lcfba = (ulong)lcdbase; + + /* MORE HACKS...This must be updated according to 823 manual + * for different panels. + * Udi Finkelstein - done - see below: + * Note: You better not try unsupported combinations such as + * 4-bit wide passive dual scan LCD at 4/8 Bit color. + */ + lchcr_hpc_tmp = + (panel_info.vl_col * + (panel_info.vl_tft ? 8 : + (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */ + /* use << to mult by: single scan = 1, dual scan = 2 */ + panel_info.vl_splt) * + (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */ + + lcdp->lcd_lchcr = LCHCR_BO | + LCDBIT (LCHCR_AT_BIT, 4) | + LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) | + panel_info.vl_wbl; + + lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) | + LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) | + LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) | + panel_info.vl_wbf; + +} + +/*----------------------------------------------------------------------*/ + +#if LCD_BPP == LCD_COLOR8 +void +lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile cpm8xx_t *cp = &(immr->im_cpm); + unsigned short colreg, *cmap_ptr; + + cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; + + colreg = ((red & 0x0F) << 8) | + ((green & 0x0F) << 4) | + (blue & 0x0F) ; +#ifdef CONFIG_SYS_INVERT_COLORS + colreg ^= 0x0FFF; +#endif + *cmap_ptr = colreg; + + debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n", + regno, &(cp->lcd_cmap[regno * 2]), + red, green, blue, + cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]); +} +#endif /* LCD_COLOR8 */ + +/*----------------------------------------------------------------------*/ + +#if LCD_BPP == LCD_MONOCHROME +static +void lcd_initcolregs (void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile cpm8xx_t *cp = &(immr->im_cpm); + ushort regno; + + for (regno = 0; regno < 16; regno++) { + cp->lcd_cmap[regno * 2] = 0; + cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f; + } +} +#endif + +/*----------------------------------------------------------------------*/ + +void lcd_enable (void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile lcd823_t *lcdp = &immr->im_lcd; + + /* Enable the LCD panel */ +#ifndef CONFIG_RBC823 + immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */ +#endif + lcdp->lcd_lccr |= LCCR_PON; + +#ifdef CONFIG_V37 + /* Turn on display backlight */ + immr->im_cpm.cp_pbpar |= 0x00008000; + immr->im_cpm.cp_pbdir |= 0x00008000; +#elif defined(CONFIG_RBC823) + /* Turn on display backlight */ + immr->im_cpm.cp_pbdat |= 0x00004000; +#endif + +#if defined(CONFIG_LWMON) + { uchar c = pic_read (0x60); +#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON) + /* Enable LCD later in sysmon test, only if temperature is OK */ +#else + c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */ +#endif + pic_write (0x60, c); + } +#endif /* CONFIG_LWMON */ + +#if defined(CONFIG_R360MPI) + { + extern void r360_i2c_lcd_write (uchar data0, uchar data1); + unsigned long bgi, ctr; + char *p; + + if ((p = getenv("lcdbgi")) != NULL) { + bgi = simple_strtoul (p, 0, 10) & 0xFFF; + } else { + bgi = 0xFFF; + } + + if ((p = getenv("lcdctr")) != NULL) { + ctr = simple_strtoul (p, 0, 10) & 0xFFF; + } else { + ctr=0x7FF; + } + + r360_i2c_lcd_write(0x10, 0x01); + r360_i2c_lcd_write(0x20, 0x01); + r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF); + r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF); + } +#endif /* CONFIG_R360MPI */ +#ifdef CONFIG_RBC823 + udelay(200000); /* wait 200ms */ + /* Turn VEE_ON first */ + immr->im_cpm.cp_pbdat |= 0x00000001; + udelay(200000); /* wait 200ms */ + /* Now turn on LCD_ON */ + immr->im_cpm.cp_pbdat |= 0x00001000; +#endif +#ifdef CONFIG_RRVISION + debug ("PC4->Output(1): enable LVDS\n"); + debug ("PC5->Output(0): disable PAL clock\n"); + immr->im_ioport.iop_pddir |= 0x1000; + immr->im_ioport.iop_pcpar &= ~(0x0C00); + immr->im_ioport.iop_pcdir |= 0x0C00 ; + immr->im_ioport.iop_pcdat |= 0x0800 ; + immr->im_ioport.iop_pcdat &= ~(0x0400); + debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", + immr->im_ioport.iop_pdpar, + immr->im_ioport.iop_pddir, + immr->im_ioport.iop_pddat); + debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", + immr->im_ioport.iop_pcpar, + immr->im_ioport.iop_pcdir, + immr->im_ioport.iop_pcdat); +#endif +} + +/*----------------------------------------------------------------------*/ + +#if defined (CONFIG_RBC823) +void lcd_disable (void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile lcd823_t *lcdp = &immr->im_lcd; + +#if defined(CONFIG_LWMON) + { uchar c = pic_read (0x60); + c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */ + pic_write (0x60, c); + } +#elif defined(CONFIG_R360MPI) + { + extern void r360_i2c_lcd_write (uchar data0, uchar data1); + + r360_i2c_lcd_write(0x10, 0x00); + r360_i2c_lcd_write(0x20, 0x00); + r360_i2c_lcd_write(0x30, 0x00); + r360_i2c_lcd_write(0x40, 0x00); + } +#endif /* CONFIG_LWMON */ + /* Disable the LCD panel */ + lcdp->lcd_lccr &= ~LCCR_PON; +#ifdef CONFIG_RBC823 + /* Turn off display backlight, VEE and LCD_ON */ + immr->im_cpm.cp_pbdat &= ~0x00005001; +#else + immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */ +#endif /* CONFIG_RBC823 */ +} +#endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */ + + +/************************************************************************/ + +#endif /* CONFIG_LCD */ diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c new file mode 100644 index 000000000..b40ec3689 --- /dev/null +++ b/drivers/video/pxa_lcd.c @@ -0,0 +1,609 @@ +/* + * PXA LCD Controller + * + * (C) Copyright 2001-2002 + * Wolfgang Denk, DENX Software Engineering -- wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************/ +/* ** HEADER FILES */ +/************************************************************************/ + +#include <config.h> +#include <common.h> +#include <version.h> +#include <stdarg.h> +#include <linux/types.h> +#include <stdio_dev.h> +#include <lcd.h> +#include <asm/arch/pxa-regs.h> +#include <asm/io.h> + +/* #define DEBUG */ + +#ifdef CONFIG_LCD + +/*----------------------------------------------------------------------*/ +/* + * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for + * your display. + */ + +#ifdef CONFIG_PXA_VGA +/* LCD outputs connected to a video DAC */ +# define LCD_BPP LCD_COLOR8 + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x003008f8 +# define REG_LCCR3 0x0300FF01 + +/* 640x480x16 @ 61 Hz */ +vidinfo_t panel_info = { + .vl_col = 640, + .vl_row = 480, + .vl_width = 640, + .vl_height = 480, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_HIGH, + .vl_vsp = CONFIG_SYS_HIGH, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 0, + .vl_clor = 0, + .vl_tft = 1, + .vl_hpw = 40, + .vl_blw = 56, + .vl_elw = 56, + .vl_vpw = 20, + .vl_bfw = 8, + .vl_efw = 8, +}; +#endif /* CONFIG_PXA_VIDEO */ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_SHARP_LM8V31 + +# define LCD_BPP LCD_COLOR8 +# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */ + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x0030087C +# define REG_LCCR3 0x0340FF08 + +vidinfo_t panel_info = { + .vl_col = 640, + .vl_row = 480, + .vl_width = 157, + .vl_height = 118, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_HIGH, + .vl_vsp = CONFIG_SYS_HIGH, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 1, + .vl_clor = 1, + .vl_tft = 0, + .vl_hpw = 1, + .vl_blw = 3, + .vl_elw = 3, + .vl_vpw = 1, + .vl_bfw = 0, + .vl_efw = 0, +}; +#endif /* CONFIG_SHARP_LM8V31 */ +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_VOIPAC_LCD + +# define LCD_BPP LCD_COLOR8 +# define LCD_INVERT_COLORS + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x043008f8 +# define REG_LCCR3 0x0340FF08 + +vidinfo_t panel_info = { + .vl_col = 640, + .vl_row = 480, + .vl_width = 157, + .vl_height = 118, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_HIGH, + .vl_vsp = CONFIG_SYS_HIGH, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 1, + .vl_clor = 1, + .vl_tft = 1, + .vl_hpw = 32, + .vl_blw = 144, + .vl_elw = 32, + .vl_vpw = 2, + .vl_bfw = 13, + .vl_efw = 30, +}; +#endif /* CONFIG_VOIPAC_LCD */ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_HITACHI_SX14 +/* Hitachi SX14Q004-ZZA color STN LCD */ +#define LCD_BPP LCD_COLOR8 + +/* you have to set lccr0 and lccr3 (including pcd) */ +#define REG_LCCR0 0x00301079 +#define REG_LCCR3 0x0340FF20 + +vidinfo_t panel_info = { + .vl_col = 320, + .vl_row = 240, + .vl_width = 167, + .vl_height = 109, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_HIGH, + .vl_vsp = CONFIG_SYS_HIGH, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 1, + .vl_splt = 0, + .vl_clor = 1, + .vl_tft = 0, + .vl_hpw = 1, + .vl_blw = 1, + .vl_elw = 1, + .vl_vpw = 7, + .vl_bfw = 0, + .vl_efw = 0, +}; +#endif /* CONFIG_HITACHI_SX14 */ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_LMS283GF05 + +# define LCD_BPP LCD_COLOR8 +/*# define LCD_INVERT_COLORS*/ + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x043008f8 +# define REG_LCCR3 0x03b00009 + +vidinfo_t panel_info = { + .vl_col = 240, + .vl_row = 320, + .vl_width = 240, + .vl_height = 320, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_LOW, + .vl_hsp = CONFIG_SYS_LOW, + .vl_vsp = CONFIG_SYS_LOW, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 1, + .vl_clor = 1, + .vl_tft = 1, + .vl_hpw = 4, + .vl_blw = 4, + .vl_elw = 8, + .vl_vpw = 4, + .vl_bfw = 4, + .vl_efw = 8, +}; +#endif /* CONFIG_LMS283GF05 */ + +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_ACX517AKN + +# define LCD_BPP LCD_COLOR8 + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x003008f9 +# define REG_LCCR3 0x03700006 + +vidinfo_t panel_info = { + .vl_col = 320, + .vl_row = 320, + .vl_width = 320, + .vl_height = 320, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_LOW, + .vl_hsp = CONFIG_SYS_LOW, + .vl_vsp = CONFIG_SYS_LOW, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 1, + .vl_clor = 1, + .vl_tft = 1, + .vl_hpw = 0x04, + .vl_blw = 0x1c, + .vl_elw = 0x08, + .vl_vpw = 0x01, + .vl_bfw = 0x07, + .vl_efw = 0x08, +}; +#endif /* CONFIG_ACX517AKN */ + +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_LQ038J7DH53 + +# define LCD_BPP LCD_COLOR8 + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x003008f9 +# define REG_LCCR3 0x03700004 + +vidinfo_t panel_info = { + .vl_col = 320, + .vl_row = 480, + .vl_width = 320, + .vl_height = 480, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_LOW, + .vl_hsp = CONFIG_SYS_LOW, + .vl_vsp = CONFIG_SYS_LOW, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 1, + .vl_clor = 1, + .vl_tft = 1, + .vl_hpw = 0x04, + .vl_blw = 0x20, + .vl_elw = 0x01, + .vl_vpw = 0x01, + .vl_bfw = 0x04, + .vl_efw = 0x01, +}; +#endif /* CONFIG_ACX517AKN */ + +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_LITTLETON_LCD +# define LCD_BPP LCD_COLOR8 + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x003008f8 +# define REG_LCCR3 0x0300FF04 + +vidinfo_t panel_info = { + .vl_col = 480, + .vl_row = 640, + .vl_width = 480, + .vl_height = 640, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_HIGH, + .vl_vsp = CONFIG_SYS_HIGH, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 0, + .vl_clor = 0, + .vl_tft = 1, + .vl_hpw = 9, + .vl_blw = 8, + .vl_elw = 24, + .vl_vpw = 2, + .vl_bfw = 2, + .vl_efw = 4, +}; +#endif /* CONFIG_LITTLETON_LCD */ + +/*----------------------------------------------------------------------*/ + +static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid); +static void pxafb_setup_gpio (vidinfo_t *vid); +static void pxafb_enable_controller (vidinfo_t *vid); +static int pxafb_init (vidinfo_t *vid); + +/************************************************************************/ +/* --------------- PXA chipset specific functions ------------------- */ +/************************************************************************/ + +void lcd_ctrl_init (void *lcdbase) +{ + pxafb_init_mem(lcdbase, &panel_info); + pxafb_init(&panel_info); + pxafb_setup_gpio(&panel_info); + pxafb_enable_controller(&panel_info); +} + +/*----------------------------------------------------------------------*/ +#if LCD_BPP == LCD_COLOR8 +void +lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) +{ + struct pxafb_info *fbi = &panel_info.pxa; + unsigned short *palette = (unsigned short *)fbi->palette; + u_int val; + + if (regno < fbi->palette_size) { + val = ((red << 8) & 0xf800); + val |= ((green << 4) & 0x07e0); + val |= (blue & 0x001f); + +#ifdef LCD_INVERT_COLORS + palette[regno] = ~val; +#else + palette[regno] = val; +#endif + } + + debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n", + regno, &palette[regno], + red, green, blue, + palette[regno]); +} +#endif /* LCD_COLOR8 */ + +/*----------------------------------------------------------------------*/ +#if LCD_BPP == LCD_MONOCHROME +void lcd_initcolregs (void) +{ + struct pxafb_info *fbi = &panel_info.pxa; + cmap = (ushort *)fbi->palette; + ushort regno; + + for (regno = 0; regno < 16; regno++) { + cmap[regno * 2] = 0; + cmap[(regno * 2) + 1] = regno & 0x0f; + } +} +#endif /* LCD_MONOCHROME */ + +/*----------------------------------------------------------------------*/ +void lcd_enable (void) +{ +} + +/************************************************************************/ +/* ** PXA255 specific routines */ +/************************************************************************/ + +/* + * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb, + * descriptors and palette areas. + */ +ulong calc_fbsize (void) +{ + ulong size; + int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; + + size = line_length * panel_info.vl_row; + size += PAGE_SIZE; + + return size; +} + +static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid) +{ + u_long palette_mem_size; + struct pxafb_info *fbi = &vid->pxa; + int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; + + fbi->screen = (u_long)lcdbase; + + fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16; + palette_mem_size = fbi->palette_size * sizeof(u16); + + debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); + /* locate palette and descs at end of page following fb */ + fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; + + return 0; +} +#ifdef CONFIG_CPU_MONAHANS +static inline void pxafb_setup_gpio (vidinfo_t *vid) {} +#else +static void pxafb_setup_gpio (vidinfo_t *vid) +{ + u_long lccr0; + + /* + * setup is based on type of panel supported + */ + + lccr0 = vid->pxa.reg_lccr0; + + /* 4 bit interface */ + if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD)) + { + debug("Setting GPIO for 4 bit data\n"); + /* bits 58-61 */ + writel(readl(GPDR1) | (0xf << 26), GPDR1); + writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20), + GAFR1_U); + + /* bits 74-77 */ + writel(readl(GPDR2) | (0xf << 10), GPDR2); + writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), + GAFR2_L); + } + + /* 8 bit interface */ + else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) || + (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS))) + { + debug("Setting GPIO for 8 bit data\n"); + /* bits 58-65 */ + writel(readl(GPDR1) | (0x3f << 26), GPDR1); + writel(readl(GPDR2) | (0x3), GPDR2); + + writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), + GAFR1_U); + writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L); + + /* bits 74-77 */ + writel(readl(GPDR2) | (0xf << 10), GPDR2); + writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), + GAFR2_L); + } + + /* 16 bit interface */ + else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS))) + { + debug("Setting GPIO for 16 bit data\n"); + /* bits 58-77 */ + writel(readl(GPDR1) | (0x3f << 26), GPDR1); + writel(readl(GPDR2) | 0x00003fff, GPDR2); + + writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), + GAFR1_U); + writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L); + } + else + { + printf("pxafb_setup_gpio: unable to determine bits per pixel\n"); + } +} +#endif + +static void pxafb_enable_controller (vidinfo_t *vid) +{ + debug("Enabling LCD controller\n"); + + /* Sequence from 11.7.10 */ + writel(vid->pxa.reg_lccr3, LCCR3); + writel(vid->pxa.reg_lccr2, LCCR2); + writel(vid->pxa.reg_lccr1, LCCR1); + writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0); + writel(vid->pxa.fdadr0, FDADR0); + writel(vid->pxa.fdadr1, FDADR1); + writel(readl(LCCR0) | LCCR0_ENB, LCCR0); + +#ifdef CONFIG_CPU_MONAHANS + writel(readl(CKENA) | CKENA_1_LCD, CKENA); +#else + writel(readl(CKEN) | CKEN16_LCD, CKEN); +#endif + + debug("FDADR0 = 0x%08x\n", readl(FDADR0)); + debug("FDADR1 = 0x%08x\n", readl(FDADR1)); + debug("LCCR0 = 0x%08x\n", readl(LCCR0)); + debug("LCCR1 = 0x%08x\n", readl(LCCR1)); + debug("LCCR2 = 0x%08x\n", readl(LCCR2)); + debug("LCCR3 = 0x%08x\n", readl(LCCR3)); +} + +static int pxafb_init (vidinfo_t *vid) +{ + struct pxafb_info *fbi = &vid->pxa; + + debug("Configuring PXA LCD\n"); + + fbi->reg_lccr0 = REG_LCCR0; + fbi->reg_lccr3 = REG_LCCR3; + + debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n", + vid->vl_col, vid->vl_hpw, + vid->vl_blw, vid->vl_elw); + debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n", + vid->vl_row, vid->vl_vpw, + vid->vl_bfw, vid->vl_efw); + + fbi->reg_lccr1 = + LCCR1_DisWdth(vid->vl_col) + + LCCR1_HorSnchWdth(vid->vl_hpw) + + LCCR1_BegLnDel(vid->vl_blw) + + LCCR1_EndLnDel(vid->vl_elw); + + fbi->reg_lccr2 = + LCCR2_DisHght(vid->vl_row) + + LCCR2_VrtSnchWdth(vid->vl_vpw) + + LCCR2_BegFrmDel(vid->vl_bfw) + + LCCR2_EndFrmDel(vid->vl_efw); + + fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP); + fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH) + | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH); + + + /* setup dma descriptors */ + fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); + fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); + fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); + + #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \ + (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \ + (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)) + + /* populate descriptors */ + fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow; + fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL; + fbi->dmadesc_fblow->fidr = 0; + fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL; + + fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */ + + fbi->dmadesc_fbhigh->fsadr = fbi->screen; + fbi->dmadesc_fbhigh->fidr = 0; + fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL; + + fbi->dmadesc_palette->fsadr = fbi->palette; + fbi->dmadesc_palette->fidr = 0; + fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL; + + if( NBITS(vid->vl_bpix) < 12) + { + /* assume any mode with <12 bpp is palette driven */ + fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh; + fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette; + /* flips back and forth between pal and fbhigh */ + fbi->fdadr0 = (u_long)fbi->dmadesc_palette; + } + else + { + /* palette shouldn't be loaded in true-color mode */ + fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh; + fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */ + } + + debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow); + debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh); + debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette); + + debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr); + debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr); + debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr); + + debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr); + debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr); + debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr); + + debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd); + debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd); + debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd); + + return 0; +} + +/************************************************************************/ +/************************************************************************/ + +#endif /* CONFIG_LCD */ diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index afcb00881..8d533955a 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -60,77 +60,15 @@ enum { LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ }; -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; - -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - vidinfo_t panel_info = { /* Insert a value here so that we don't end up in the BSS */ .vl_col = -1, }; -char lcd_cursor_enabled; - -ushort lcd_cursor_width; -ushort lcd_cursor_height; - #ifndef CONFIG_OF_CONTROL #error "You must enable CONFIG_OF_CONTROL to get Tegra LCD support" #endif -void lcd_cursor_size(ushort width, ushort height) -{ - lcd_cursor_width = width; - lcd_cursor_height = height; -} - -void lcd_toggle_cursor(void) -{ - ushort x, y; - uchar *dest; - ushort row; - - x = console_col * lcd_cursor_width; - y = console_row * lcd_cursor_height; - dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / - 8); - - for (row = 0; row < lcd_cursor_height; ++row, dest += lcd_line_length) { - ushort *d = (ushort *)dest; - ushort color; - int i; - - for (i = 0; i < lcd_cursor_width; ++i) { - color = *d; - color ^= lcd_color_fg; - *d = color; - ++d; - } - } -} - -void lcd_cursor_on(void) -{ - lcd_cursor_enabled = 1; - lcd_toggle_cursor(); -} -void lcd_cursor_off(void) -{ - lcd_cursor_enabled = 0; - lcd_toggle_cursor(); -} - -char lcd_is_cursor_enabled(void) -{ - return lcd_cursor_enabled; -} - static void update_panel_size(struct fdt_disp_config *config) { panel_info.vl_col = config->width; @@ -150,8 +88,6 @@ void lcd_ctrl_init(void *lcdbase) assert(disp_config); - lcd_base = (void *)disp_config->frame_buffer; - /* Make sure that we can acommodate the selected LCD */ assert(disp_config->width <= LCD_MAX_WIDTH); assert(disp_config->height <= LCD_MAX_HEIGHT); @@ -172,7 +108,7 @@ void lcd_ctrl_init(void *lcdbase) /* Enable flushing after LCD writes if requested */ lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH); - debug("LCD frame buffer at %p\n", lcd_base); + debug("LCD frame buffer at %08X\n", disp_config->frame_buffer); } ulong calc_fbsize(void) |